KR20030087744A - Method for forming contact hole in integrated circuit - Google Patents

Abstract

PURPOSE: A method for forming a contact hole of an integrated circuit is provided to be capable of defining the contact hole without using a photolithography process. CONSTITUTION: After preparing a semiconductor substrate, a plurality of bit lines(130) are spaced apart from each other at the upper portion of the semiconductor substrate. At this time, the first width of the bit line is smaller than the second width of a bit line tap(130a). A bit line spacer(145) is formed at both sides of each bit line. A contact hole(150) is formed by contacting neighboring bit line spacers with each other. Preferably, the bit line spacer is completed by forming an insulating layer at the upper portion of the semiconductor substrate and carrying out an anisotropic etching process at the insulating layer.

Description

Method for forming contact hole in integrated circuit

The present invention relates to a method of forming a contact hole in an integrated circuit, and more particularly, to a method of forming a contact hole in an integrated circuit capable of defining a fine contact hole without performing a photolithography process.

Recently, in order to realize high speed and large capacity, the degree of integration is continuously increasing in semiconductor memory devices. In particular, as the integration degree of the DRAM, which is one of the memory devices, becomes more than a giga bit, a design rule is reduced to 0.18 μm or less. As such, if the design rule is reduced to 0.18 μm or less, the horizontal direction, for example, the distance between the device and the device, and the vertical direction, that is, the contact hole size and the misalign margin connecting the layers are also the design rule. In addition to being reduced in proportion to the risk of poor contact filling and misalignment, it is very difficult to form contact holes of fine size suitable for the design rule using a photolithography process.

Accordingly, an object of the present invention is to provide a method for forming a contact hole in an integrated circuit capable of defining a contact hole without using a photolithography process.

1 to 3 are cross-sectional views of integrated circuits for respective processes for explaining an embodiment of the present invention.

4 to 6 are perspective views of integrated circuits for respective processes for explaining an embodiment of the present invention.

7 is a perspective view of an integrated circuit for explaining another embodiment of the present invention.

8 is a cross-sectional view of an integrated circuit for explaining another embodiment of the present invention.

9 is a graph showing the thickness of the third interlayer insulating layer and the width of the contact region in the integrated circuit according to the present invention.

10 is a graph showing the thickness of the third interlayer insulating layer according to the line width of the bit line structure and the line width of the tab of the bit line structure in the integrated circuit according to the present invention.

11 to 16 are cross-sectional views of integrated circuits for respective processes for describing still another exemplary embodiment of the present invention.

17 is a perspective view of an integrated circuit for explaining another embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100 semiconductor substrate 130 bit line structure

130a: tab of the bit line structure 140: third interlayer insulating film

145: bit line spacer 150: contact hole

160: fourth interlayer insulating film 170: etch stopper

Other objects and novel features as well as the objects of the present invention will become apparent from the description of the specification and the accompanying drawings.

Among the inventions disclosed herein, an outline of representative features is briefly described as follows.

First, in the method for forming a contact of an integrated circuit according to an embodiment of the present invention, first, a plurality of wires are formed to cover an insulating material on the semiconductor substrate while being spaced by a predetermined distance. At this time, the wiring includes a tab portion having a first width and having a second width larger than the first width for every predetermined length. Thereafter, spacers are formed on both side walls of the wiring. In this case, the spacers on both side walls of the tab contact the adjacent spacers to form contact holes.

Here, the width of the tab of the wiring is B + 0.02 µm <width of the tab <2A-0.02 µm (where A is a design rule of the integrated circuit and B is the width of the wiring). Satisfies.

In addition, the spacer is formed by forming an insulating layer on the semiconductor substrate on which the wiring is formed, and forming the spacer by anisotropic integrated circuit angles of the insulating layer.

In this case, the insulating layer is a condition of 2 (2A-B) <thickness of the insulating layer <2 (2A-C), where A is the design rule of the integrated circuit, B is the width of the tab of the wiring, C is the wiring Is formed to satisfy the width).

The insulating layer is preferably formed of a material having a step coverage of 80% or more, and the material may include a silicon nitride film.

In addition, after forming the spacer, an insulating film for preventing voids may be further deposited on the resultant product on which the spacer is formed, and the void preventing insulating film may be etched back to the anisotropic blanket.

At this time, the thickness of the void prevention insulating film is formed so as to satisfy the condition of 0.005 占 퐉 <void prevention insulating film thickness <D / 2 (where D represents a gap between spacers on both sides of the wiring).

In addition, a method for forming a contact hole in an integrated circuit according to another embodiment of the present invention is as follows. First, a cell region and a peripheral region (core region) are defined, and a first interlayer insulating layer formed on a word line structure, a source drain region formed on both substrates of the word line structure, and the word line structure and the source and drain regions. And a self-aligned contact pad formed in the first interlayer insulating layer and in contact with the source and drain regions, respectively. A plurality of bit lines parallel to each other are formed on the semiconductor substrate. The bit lines include insulators on the top, spaced at regular intervals, and include tabs having a relatively wide width at certain lengths. Thereafter, spacers are formed on both side walls of the bit line structure. In this case, forming the spacer, a predetermined space is secured in a portion where the relatively narrow width is facing, both side walls of the tab having a relatively wide width is formed to be in contact with the spacer of another adjacent bit line structure, contact Holes are formed.

In this case, between forming the bit line structure and forming the spacer, forming an etch stopper on the bit line structure, and forming a planarization layer to expose the etch stopper of the cell region. The spacer may be formed on sidewalls of the planarization layer.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, a layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. Can be done.

1 to 3 are cross-sectional views of integrated circuits for respective processes for explaining an embodiment of the present invention. 4 to 6 are perspective views of integrated circuits for respective processes for explaining an embodiment of the present invention. 7 is a perspective view of an integrated circuit for explaining another embodiment of the present invention, and FIG. 8 is a cross-sectional view of an integrated circuit for explaining another embodiment of the present invention. FIG. 9 is a graph illustrating a thickness of a third interlayer insulating layer and a width of a contact region in an integrated circuit according to the present invention, and FIG. 10 is a line width of a bit line structure and a line width of a tab of a bit line structure in an integrated circuit according to the present invention. It is a graph which shows the thickness of a 3rd interlayer insulation film. 11 to 16 are cross-sectional views of integrated circuits of respective processes for describing still another embodiment of the present invention, and FIG. 17 is a perspective view of an integrated circuit for explaining another embodiment of the present invention.

The present embodiment is a method of defining a contact hole without a photolithography process, and a method of defining a region (hereinafter, referred to as a contact hole region) on which a storage contact pad is to be formed without a photolithography process will be described.

Referring to FIG. 1, in order to define an active region on a semiconductor substrate 100, an isolation layer 105 is formed in a known manner. The device isolation layer 105 forms a word line structure 110 at a predetermined interval on the semiconductor substrate 100 on which the device isolation layer 105 is formed, for example, by a shallow trench isolation (STI) method. The word line structure 110, as is known, deposits and patterns the gate insulating layer 112, the conductive layer 114, and the hard mask layer 116, and then patterns the patterned hard mask layer 116 and the conductive layer 114. And spacers 118 on the sidewalls of the gate insulating film 112. Then, impurities are implanted into the semiconductor substrate 100 on both sides of the word line structure 110 to form source and drain regions (not shown). Thereafter, the first interlayer insulating layer 115 is deposited on the semiconductor substrate 100 to sufficiently fill the space between the word line structures 110. The first interlayer insulating layer 115 may be formed of a material having a different etching selectivity from the hard mask layer 116 and the spacer 118, and the first interlayer insulating layer 115 may be partially etched to expose the source and drain regions. do. In this case, the word line conductive layer 114 is surrounded by the hard mask layer 116 and the spacer 118, and the first interlayer insulating layer 115 is etched with the hard mask layer 116 and the spacer 118. Since the ratios are different, holes are formed in a self-aligned manner along the side surfaces of the hard mask layer 116 and the spacer 118 when the first interlayer insulating layer 115 is etched to expose the source and drain regions. Then, the conductive layer is formed to contact the exposed source drain region, and then the conductive layer is chemically mechanically polished to expose the first interlayer insulating film 115, thereby forming a self align contact pad 120 (hereinafter, SAC pad). ).

Next, a second interlayer insulating layer 125 is deposited on the semiconductor substrate 100. A bit line contact pad (not shown) is then formed in the second interlayer insulating film 125 in a known manner. A bit line contact pad (not shown) is in contact with the SAC pad 120 in contact with the drain region. The bit line conductive layer 132 and the hard mask layer 134 are sequentially stacked on the second interlayer insulating layer 125 provided with the bit line contact pads (not shown). The hard mask layer 134 and the bit line conductive layer 132 are partially patterned to form the bit line structure 130. In this case, as shown in FIG. 4, the bit line structure 130 has a relatively wide width at a portion contacted with the bit line contact pad in order to secure an overlap margin with the lower bit line contact pad. And a tab 130a having an area, and the tab 130a is formed at a predetermined length. Each bit line structure 130 is disposed in parallel at equal intervals. In this case, the width of the tab 130a may be, for example, about 0.02 μm larger than the design rule and less than about 0.02 μm at twice the width of the bit line structure 130. Here, the X area of the figure is a cross-sectional part shown by cutting in the direction parallel to the word line, and the Y area of the figure is a cross-sectional part shown by cutting in the direction parallel to the bit line.

Next, as shown in FIGS. 2 and 5, a third interlayer insulating layer 140 is deposited on the semiconductor substrate 100 on which the bit line structure 130 is formed. At this time, in the present embodiment, the following conditions are required in order to provide a storage contact pad space (contact hole) by only depositing the third interlayer insulating layer 140 without a photolithography process.

That is, the third interlayer insulating layer 140 may be formed of a silicon nitride film (SiN) having a high step coverage, preferably, a step coverage of 80% or more, for example, the following conditions: Should be satisfied.

(Condition 1)

2 (2A-B) <t1 <2 (2A-C)

Here, A is a design rule of the device, B is the width of the tab 130a of the bit line structure, C is the line width of the bit line structure 130, t1 represents the thickness of the third interlayer insulating film 140. As such, when the third interlayer insulating layer 140 is formed, the third interlayer insulating layer 140 is evenly deposited over all regions along the bend of the bit line structure 130, and the third interlayer insulating layer 140 is deposited by deposition. A space is secured between the bit line structure 130 and the bit line structure 130, and the third interlayer insulating layer 140 is in contact with the bit line structure 130 and the tab 130a.

As shown in FIGS. 3 and 6, the third interlayer insulating layer 140 formed as described above is anisotropic blanket etched back and remains on the sidewalls of the bit line structure 130. The remaining third interlayer insulating layer 140 is referred to as a bit line spacer 145. Accordingly, a contact space (contact hole) 150 in which the storage contact pads are to be formed between the adjacent bit line structures 130 is secured, and the bit line structure 130 and the tab 130a of the adjacent bit line structures may be formed. It is embedded by the three interlayer insulating film 140. In this case, since the bit line spacer 145, that is, the third interlayer insulating layer 140 is formed in accordance with the condition 1 to secure the storage contact pad space, the bit line spacer 145 has a storage contact pad space of a desired size and a bit line structure. It is possible to sufficiently insulate the 130 and the storage contact pad (not shown) to be formed later.

However, in some cases, the third interlayer insulating film 140 may be formed of a film having poor step coverage. In this case, as shown in FIG. 7, when the bit line spacer 145 is formed, the contact forming space 150 is provided between the bit line structures 130, but the bit line adjacent to the bit line structure 130 is provided. The void 155 may be generated without filling the third interlayer insulating layer 140 between the tabs 130a of the structure 130. This condition can cause a short between subsequent storage contact pads (not shown). Accordingly, in another embodiment of the present invention, as shown in FIG. 8, the bit line spacer 145 is formed on the sidewall of the bit line structure 130, and then the fourth interlayer insulating layer 160 is deposited. Then, the fourth interlayer insulating layer 160 may fill the void 155 or may cover the void 155. In this case, the thickness of the fourth interlayer insulating layer 160 may be defined by the following condition 2.

(Condition 2)

0.005 μm <t2 <D / 2

Here, t2 is the thickness of the fourth interlayer insulating film 160, D represents the width (width between spacers) of the contact predetermined region, and the contact predetermined region is defined by the following condition 3.

(Condition 3)

0.01 μm <D <C-B

Here, B and C represent the bit line line width and the line width of the tap, respectively, as described above. That is, the fourth interlayer insulating layer 160 is deposited to be larger than the minimum thickness capable of maintaining the insulation between the conductors and not to fill the contact predetermined region. Thereafter, the fourth interlayer insulating layer 160 is etched back to leave the fourth interlayer insulating layer 160 on both sides of the bit line sidewall spacer 145 and the portion of the void 155 (see FIG. 8).

9 is a graph showing the thickness of the third interlayer insulating layer and the width of the contact region in the integrated circuit according to the present invention. Referring to FIG. 9, the third interlayer insulating layer needs to be thinner as the width of the contact region becomes narrower to secure the contact region. For example, in the case where the line width of the bit line structure, that is, the line width of the conductive layer for the bit line is 60 nm and the width of the tab of the bit line structure is 110 nm, as a result of simulation, the third interlayer insulating film must be 275 kV or more between the conductive layers in the contact region. Insulation can be ensured and contact area should be secured at 400Å or less.

10 is a graph showing the thickness of the third interlayer insulating film according to the line width of the bit line structure (line width of the conductive layer for the bit line) and the line width of the tab of the bit line structure. It can be seen that as the line width of the tab of the line structure increases, the gap between the bit line structure and the adjacent bit line structure becomes narrower, thereby reducing the thickness of the third interlayer insulating film. Here, ①-⑦ of the drawing shows the thickness range of the third interlayer insulating film according to the line width of each bit line structure (line width of the conductive layer for bit lines) and the line width of the tab of the bit line structure, and ⑧ is the bit line structure. The tap area of the bit line structure is set to have a smaller width than the line width of, which is a meaningless area.

11 to 16 are cross-sectional views of respective processes illustrating an integrated circuit according to another exemplary embodiment of the present invention, and FIG. 17 is a perspective view of each process illustrating an integrated circuit according to another exemplary embodiment of the present invention. Here, the present embodiment is the same until the process of forming the bit line structure of FIGS. 1 and 4, and the subsequent steps will be described. In addition, the drawing of this embodiment shows a core region instead of showing a cross section parallel to the bit line of the cell region.

As illustrated in FIG. 11, an etch stopper 170 is formed on the result of the semiconductor substrate 100 on which the bit line structure 130 including the tab region 130a (see FIG. 4) is formed. The etch stopper 170 may be, for example, silicon nitride (SiN), and is formed of a thin film. In this case, the region marked Z in the drawing represents a core region of the semiconductor memory device, and the bit line structure 130 on the core region Z is used as a local electrical wiring of the semiconductor memory device.

Next, as shown in FIG. 12, the planarization insulating layer 175 is formed on the etch stopper 130. The planarization insulating layer 175 is formed to a thickness such that the space between the bit line structures 130 is sufficiently filled.

As shown in FIG. 13, the planarization insulating layer 175 is etched so that the cell region X is exposed. The planarization insulating layer 175 may be removed by, for example, a wet etching method, and since the etch stopper 170 is formed under the planarization insulating layer 175, the lower structures are protected when the planarization insulating layer 175 is etched.

Referring to FIG. 14, a third interlayer insulating layer 180 is formed on the etch stopper 170 and the planarization insulating layer 175 of the exposed cell region X. In the third interlayer insulating layer 180 of the present embodiment, a space is formed between the bit line structure 130 and the bit line, and the space between the bit line structure and the tab of the bit line structure is formed to a thickness sufficient to fill. The third interlayer insulating film 180 of the present embodiment is also deposited to satisfy the condition 1. In this case, the third interlayer insulating film 180 preferably uses a film quality having a step coverage of 80% or more, for example, a silicon nitride film (SiN). ) Can be used.

As described above, the contact formation space is naturally provided as shown in FIG. 17 by the deposition of the third interlayer insulating layer 180. That is, in the formation of the third interlayer insulating layer 180, a contact forming space is provided between the bit line structure 130, and a third interlayer insulating film is formed between the bit line structure 130 and the tab 130a of the bit line structure. By filling 180, the contact forming space is naturally limited.

Here, when the step coverage of the third interlayer insulating layer 180 is not excellent, a fourth interlayer insulating layer (not shown) may be further deposited as described above.

Next, as shown in FIG. 15, the anisotropic blanket is etched from the third interlayer insulating layer 180 to form bit line spacers 185 on both sidewalls of the bit line structure 130 having the etch stopper 170 coated on the surface thereof. To form.

Then, a conductive layer (not shown) is formed on the semiconductor substrate 100 resultant to sufficiently fill the space between the bit line structures 130. As shown in FIG. 16, the conductive layer is chemically mechanically polished or etched back to form a storage contact pad 190.

The present invention is not limited to the above-described embodiment.

For example, in the present exemplary embodiment, a method of forming a contact hole in which a storage contact pad is to be formed is described. However, the present invention is not limited thereto and may be applied to various contact holes.

As described above in detail, according to the present invention, an insulating spacer is formed between two wirings which are spaced apart at regular intervals and have partially different widths. Accordingly, a contact forming space is provided between the wiring portions having a relatively narrow width, and the portions having the relatively wide width are in contact with the insulating spacers of the adjacent wirings to surround the contact forming space.

Therefore, the contact hole can be defined without the photolithography process, and thus it can be applied to a highly integrated semiconductor device.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (17)

Providing a semiconductor substrate; Forming a plurality of wires to cover an insulating material on the semiconductor substrate while being spaced apart by a predetermined distance, wherein the wires have a first width, and each tab has a tab portion having a second width greater than the first width. Forming a wiring to include; And Forming spacers on both side walls of the wiring; The contact hole forming method of the integrated circuit of claim 2, wherein the spacers on both sidewalls of the tab are in contact with adjacent spacers. The method of claim 1, The width of the tab of the wiring satisfies the following conditions. B + 0.02 μm <Width of tap <2A-0.02 μm Here, A is a design rule of the integrated circuit, and B represents the width of the wiring. The method of claim 1, Forming the spacers, Forming an insulating layer on the semiconductor substrate on which the wiring is formed; And anisotropically etching the insulating layer to form a spacer. The method of claim 3, wherein And the insulating layer is formed to have a thickness satisfying the following conditions. 2 (2A-B) <thickness of insulation layer <2 (2A-C) Here, A is the design rule of the integrated circuit, B is the width of the tab of the wiring, and C is the width of the wiring. The method of claim 3, wherein And the insulating layer is formed of a material having a step coverage of 80% or more. 6. The method of claim 5, wherein the insulating layer is a silicon nitride film. The method of claim 1, After forming the spacer, Depositing an insulating film for preventing voids on the resultant material on which the spacer is formed; And And anisotropic blanket etching back said void preventing insulating film. The method of claim 7, wherein The thickness of the void prevention insulating film is deposited to meet the following conditions, the contact hole forming method of the integrated circuit. 0.005 탆 <Insulation thickness for void prevention <D / 2 Here, D represents an interval between spacers on both sides of the wiring. A cell region and a peripheral region (core region) are defined, and a word line structure, a source drain region formed on both substrates of the word line structure, a first interlayer insulating layer formed on the word line structure and the source and drain regions, and the Providing a semiconductor substrate formed in a first interlayer insulating film, the self-aligned contact pads being in contact with the source and drain regions, respectively; Forming a plurality of bit lines parallel to each other on the semiconductor substrate, wherein the bit lines include a tab having an insulating layer thereon, the tabs having a relatively wide width at predetermined lengths, spaced at regular intervals Forming a structure; And Forming spacers on both sidewalls of the bit line structure; In the forming of the spacer, a predetermined space is secured in a portion where a relatively narrow width faces each other, and both side walls of the tab having a relatively wide width are formed to be in contact with a spacer of another adjacent bit line structure. Forming a contact hole in an integrated circuit. The method of claim 9, And a width of the tab of the bit line structure satisfies the following condition. B + 0.02 μm <Width of tap <2A-0.02 μm Here, A is a design rule of the integrated circuit, and B represents the line width of the bit line structure. The method of claim 9, Forming the spacers, Forming an insulating layer on the semiconductor substrate on which the bit line structure is formed; And anisotropically etching the insulating layer to form a spacer. The method of claim 11, And the insulating layer is formed to have a thickness satisfying the following conditions. 2 (2A-B) <thickness of insulation layer <2 (2A-C) Here, A is the design rule of the integrated circuit, B is the width of the tab of the bit line structure, C is the line width of the bit line structure. The method of claim 11, And the insulating layer is formed of a material having a step coverage of 80% or more. The method of claim 13, wherein the insulating layer is a silicon nitride film. The method of claim 9, After forming the spacer, Depositing an insulating film for preventing voids on the resultant material on which the spacer is formed; And And anisotropic blanket etching back said void preventing insulating film. The method of claim 15, The thickness of the void prevention insulating film is deposited to meet the following conditions, the contact hole forming method of the integrated circuit. 0.005 탆 <Insulation thickness for void prevention <D / 2 Here, D represents an interval between spacers on both sides of the wiring. The method of claim 9, Between forming the bit line structure and forming the spacer, forming an etch stopper on the bit line structure, and forming a planarization film to expose the etch stopper of the cell region, And forming a spacer on the sidewalls of the planarization layer.