KR20030093818A - Method for forming contact holes in semiconductor devices - Google Patents

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided to be capable of easily forming the contact hole without using photolithographic processing. CONSTITUTION: A semiconductor substrate is prepared. Oxide patterns(50a) for a mold are formed on the semiconductor substrate for forming interconnections, wherein the oxide patterns(50a) have the first width(W11) and a contact hole forming region has the second width(W12). The second width(W12) is wider than the first width(W11). Damascene interconnections are then formed between the oxide patterns(50a). A contact hole is formed by selectively etching the remaining oxide patterns.

Description

Method for forming contact holes in semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole without using a photolithography process.

As the degree of integration of semiconductor devices increases, the spacing between the devices becomes narrower and the area in which each device can be formed becomes smaller. This result reduces contact area and reduces alignment margin in the photolithography process, thereby making contact defects more likely to occur.

As is well known, a method of forming a self-aligned contact (SAC) is widely used as a method of forming a contact of a highly integrated semiconductor device while securing a photolithography process margin. However, since the photolithography process still needs to be performed to form the SAC, misalignment margin with the underlying layer must be managed very important. To this end, it is necessary to design a semiconductor device in consideration of process margins that can be managed by a device performing a photolithography process, and thus, there are many limitations in making the semiconductor device more highly integrated.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for forming a contact hole in a semiconductor device capable of forming contact holes without using a photolithography process in order to solve the problems of the conventional process described above.

1 is a layout of a DRAM cell to be implemented in the first embodiment of the present invention.

2 is a view for explaining a process step according to the first embodiment of the present invention corresponding to the section II-II 'of FIG.

3 to 8 are top views of respective processes following the process steps of FIG. 2.

9 to 14 are cross-sectional views corresponding to respective process steps of FIGS. 3 to 8.

Figure 15 is a layout of a DRAM cell to be implemented in the second embodiment of the present invention.

16 to 20 are cross-sectional views for each process proceeding according to the layout of FIG. 15 in a second embodiment of the present invention.

21A and 21B are top views corresponding to the process steps of FIG. 17.

22 and 23 are perspective views corresponding to the process steps of FIG. 18.

24 is a perspective view corresponding to the process step of FIG. 19.

<Explanation of symbols for the main parts of the drawings>

5, 105: semiconductor substrate, 20, 220: etch stopper,

45a, 45b, 145: contact region, 50, 250: oxide film,

47a, 47b, 147: contact hole, 60: gate,

50a, 50c, 50d, 250a, 250c, 250d: oxide film pattern,

62, 162: tap area, 80, 280: mask film,

160: bit line.

In the method for forming a contact hole according to the present invention for achieving the above technical problem, to form a mold oxide film pattern for forming parallel wirings on a semiconductor substrate. In this case, the oxide layer pattern has a first width and is formed to have a second width larger than the first width for each portion where the contact hole is to be formed. Then, a portion of the conductive material is embedded between the oxide patterns to form damascene wires parallel to each other, and only the portion having the second width in the oxide pattern remains above the wiring. The oxide pattern is etched. In this way, if a mask layer is formed on the wiring so as to be parallel to the upper surface of the remaining oxide film pattern, and if the remaining oxide film pattern is selectively removed with respect to the mask film, a contact hole may be formed at a position where the remaining oxide film pattern is present. Is formed.

Here, in order to form the wirings and etch the oxide pattern on the wiring, a conductive material is deposited to cover the top surface of the oxide pattern and fill the gaps between the oxide patterns, and then recess the conductive material from the oxide pattern. In order to form the damascene wires, the upper surface of the resultant material on which the conductive material is deposited is etched back such that the width of the oxide pattern above the wires is reduced as a whole. Then, the oxide film pattern having the reduced width is etched so that only the portion having the second width in the oxide film pattern remains above the wiring.

When the etch back is sufficiently performed in the step of etching back the upper surface of the resultant material on which the conductive material is deposited, only a portion having the second width in the oxide pattern may remain above the wiring, and thus subsequent steps of etching the oxide pattern. May be omitted. That is, the etch back step and the subsequent etching step may be performed by merging.

According to the present invention, since the contact hole can be formed without photolithography, the contact hole can be formed accurately aligned in position without considering the process margin.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. The shape and the like of the elements in the drawings are exaggerated in order to emphasize a more clear description, elements denoted by the same reference numerals in the drawings means the same elements.

(First embodiment)

In the present embodiment, a case in which a cell pad contact hole is formed while the gate of the DRAM is formed by the damascene method will be described with reference to FIGS. 1 is a layout of a DRAM cell to be implemented in this embodiment. FIG. 2 corresponds to the section II-II 'of FIG. 1 and is a view for explaining the process steps according to the present embodiment. 3 to 8 are top views of respective processes following the process steps of FIG. 2. 9 to 14 are cross-sectional views corresponding to the respective process steps of FIGS. 3 to 8. (A), (b) and (c) in FIGS. 9 to 14 correspond to a-a ', b-b' and c-c 'cross sections in FIGS. 3 to 8.

Referring first to FIG. 1, an active region 15 having a long axis and a short axis is repeatedly arranged along rows and columns on a semiconductor substrate. Portions other than the active region 15 are device isolation films 10 made of an insulating material. Two gate lines 30 extending in the short direction of the active region 15 are disposed per active region 15. Contact regions 45a and 45b formed by cell pads are provided in the active regions 15 on both sides of the gate line 30.

Referring now to Figure 2 looks at the process steps according to an embodiment of the present invention. First, in order to define the active regions 15 in the semiconductor substrate 5 in the shape as shown in FIG. 1, the device isolation layer 10 is formed by a shallow trench isolation (STI) method, and then the front surface of the semiconductor substrate 5 is formed. An etch stopper 20 having a thickness of about 500 kPa is formed. Subsequently, an oxide film 50 having a thickness of about 500 to 6000 GPa is formed. The etch stopper 20 may be formed by depositing a material having a different etching selectivity from the oxide film 50, such as silicon nitride.

Next, as illustrated in FIGS. 3 and 9, the oxide film 50 is patterned to form oxide film patterns 50a exposing the etch stopper 20. The oxide film patterns 50a are mold oxide film patterns for forming a gate to be placed on the gate line 30 of FIG. 1 by the damascene method. In this case, the oxide layer pattern 50a has a first width W11 and the first width W11 wherever the cell pad contact hole is to be formed, that is, the contact area 45a or 45b of FIG. 1. Rather than having a larger second width (W12).

4 and 10, the etch stopper 20 that is exposed as the oxide pattern 50a is formed is removed, and then the gate oxide layer 22 is formed on the removed portion. As the gate oxide film 22, a thin thermal oxide film can be grown.

Referring now to FIGS. 5 and 11, the conductive material is partially filled between the oxide layer patterns 50a to form damascene gates 60 parallel to each other. The oxide pattern of the upper portion of the gate 60 is etched so that only the portion of the oxide pattern 50a having the second width W12 remains above the gate 60, thereby reducing the width of the upper pattern as a whole. To form 50b.

As described with reference to FIG. 3, since the oxide film pattern 50a is formed to have a jagged shape by having the first width W11 and the second width W12, a conductive material is formed between the oxide film patterns 50a. The gate 60 formed therein is substantially a line type but has a wider tab area 62 than the periphery.

Looking at the step of forming the damascene gates 60 and the oxide layer pattern 50b having a reduced width in detail, first, as shown in FIG. 4, a conductive material such as polysilicon doped on the entire surface of the gate oxide layer 22 is formed. Deposit. The conductive material is deposited to cover the top surface of the oxide pattern 50a and to fill the gaps between the oxide pattern 50a. Subsequently, by etching back the upper surface of the resultant material on which the conductive material is deposited, the conductive material is recessed from the oxide layer pattern 50a to form gates 60. By etch back, the width of the oxide film pattern above the gate 60 is also reduced as a whole. As a result, the gap between the oxide layer patterns 50b on the gate 60 is wider than before the etch back is performed.

6 and 12, the oxide patterns 50b having the reduced width are etched to leave only portions of the oxide patterns 50a having the second width W12 above the gate 60. This can be understood that the thin oxide pattern portion between the tab regions 62 facing each other in the neighboring gates 60 is removed, and the thicker oxide layer pattern portions are left behind because the tab regions 62 do not face each other. Can be. It can be seen that the portion above the gate 60 among the remaining oxide layer patterns 50c is located only on the portions 45a and 45b where the contact holes are to be formed. When etching the oxide layer patterns 50b having a reduced width, dry etching, wet etching, or plasma etching may be used. If the etching back is sufficiently performed in the steps described with reference to FIGS. 5 and 11, the second width (i) in the oxide layer pattern 50a may be omitted even if the subsequent etching of the oxide layer patterns 50b having the reduced width is omitted. Only the part that had W12) can be left.

7 and 13, a mask film 80 is formed on the gate 60 to be parallel to the top surface of the oxide film pattern 50c thus left. First, a mask material covering the upper surface of the oxide film pattern 50c and completely filling the oxide film patterns 50c is deposited. The deposition thickness of the mask material may be 500 to 10000 kPa. The mask material is different from the oxide film pattern 50c in etching selectivity and is preferably a material having excellent step coverage. For example, the mask material may be a silicon nitride film.

Next, the upper surface of the resultant material on which the mask material is deposited is planarized by dry etching or chemical mechanical polishing (CMP) until the upper surface of the remaining oxide layer pattern 50c is exposed. Then, as illustrated, the entire cell portion is covered with the mask layer 80, and the oxide layer pattern 50c is exposed only on the regions 45a and 45b where the contact holes are to be formed.

8 and 14, by selectively removing the remaining oxide film pattern 50c with respect to the mask film 80, contact holes 47a and 47b are formed in the place where the remaining oxide film pattern 50c was located. . As such, since the contact holes 47a and 47b are not formed by photolithography, the process can be performed without considering the misalignment margin. When removing the remaining oxide layer pattern 50c, anisotropic etching may be used to leave the oxide layer pattern 50d in the form of a spacer around the gate 60. When the etch stopper 20 is removed in the contact holes 47a and 47b thus formed and then filled with a conductive material, the cell pads are aligned properly at the desired positions 45a and 45b as shown in FIG. 1. .

(2nd Example)

In the present embodiment, a case in which a contact hole for a storage node contact plug is formed while a bit line of a DRAM is formed by a damascene method will be described with reference to FIGS. 15 to 24. 15 is a layout of a DRAM cell to be implemented in the second embodiment of the present invention. 16 to 20 are cross-sectional views of processes according to the layout of FIG. 15 in the second embodiment of the present invention. (A) and (b) in FIGS. 16 to 20 correspond to cross sections a-a 'and b-b' of FIG. 15, respectively. 21A and 21B are top views corresponding to the process steps of FIG. 17. 22 and 23 are perspective views corresponding to the process steps of FIG. 18. 24 is a perspective view corresponding to the process step of FIG. 19.

First, referring to FIG. 15, an active region 115 having a long axis and a short axis is repeatedly arranged along a row and a column on a semiconductor substrate. Portions other than the active region 115 are the device isolation layers 110. Two gates 130 per active region 115 are disposed to extend in a short direction of the active region 115. Cell pads 140a and 140b are formed at both sides of the gate 130. The bit line contact pads 142 are formed on the cell pads 140b facing the drain side, and the bit lines 160 are disposed on the bit line contact pads 142 perpendicular to the extending direction of the gate 130. A contact region 145 is formed on the cell pad 140a facing the source by a storage node contact plug.

Referring to FIG. 16, an isolation layer 110 is formed on the semiconductor substrate 105 to define the active regions 115 as shown in FIG. 15. A gate 130 is formed on the semiconductor substrate 105 on which the device isolation layer 110 is formed. The gate 130 forms a gate insulating film 112, a conductive layer 114, and a hard mask film 116 and patterns the pattern, and then patterned the hard mask film 116, a conductive layer 114, and a gate insulating film 112. ) By forming spacers 118 on the sidewalls. Impurities are implanted into the semiconductor substrate 105 at both sides of the gate 130 to form a source / drain region (not shown). The first interlayer insulating layer 120 is formed on the semiconductor substrate 105 by depositing a material having a different etching selectivity from the hard mask layer 116 and the spacer 118 so that the space between the gates 130 is sufficiently filled. . Next, the first interlayer insulating layer 120 is partially etched to expose the source / drain regions. In this case, the conductive layer 114 is surrounded by the hard mask layer 116 and the spacer 118, and the first interlayer insulating layer 120 has an etching selectivity different from that of the hard mask layer 116 and the spacer 118. Therefore, holes are formed along the side surfaces of the hard mask layer 116 and the spacer 118 in a self-aligning manner. Then, the conductive layer is filled to contact the exposed source / drain regions to form cell pads 140a and 140b.

Subsequently, the second interlayer insulating layer 125 is formed on the semiconductor substrate 105, and then the bit line contact pads 142 are formed in the second interlayer insulating layer 125 as shown in FIG. 15. The etch stopper 220 having a thickness of about 10 to 500 mW is formed on the second interlayer insulating layer 125 having the bit line contact pad 142 and the oxide film 250 having a thickness of about 500 to 6000 mW is formed.

As shown in FIG. 17, the oxide film 250 is patterned to form oxide film patterns 250a exposing the etch stoppers 220, and the etch stoppers 220 exposed by the oxide film patterns 250a are removed. The second interlayer insulating film 125 is exposed. The oxide film patterns 250a are mold oxide film patterns for forming the bit line 160 arranged as shown in FIG. 15 by the damascene method. Looking at these results should look like Figure 21a or 21b. As shown in FIGS. 21A and 21B, the oxide layer pattern 250a has a first width W21, and the first width (wherever the contact hole is formed, that is, the contact area 145 of FIG. 15). It is formed to have a larger second width (W22) than W21.

Referring to FIG. 18, a portion of the conductive material is buried between the oxide pattern 250a to form bit lines 160 parallel to each other, and only the portion of the oxide pattern 250a having the second width W22 is bit. By etching the oxide pattern on the bit line 160 so as to remain above the line 160, the oxide pattern 250b having a reduced overall width is formed. This step may be accomplished by depositing a conductive material and then performing etch back as described with reference to FIGS. 5 and 11.

22 and 23 are perspective views corresponding to the process steps of FIG. 18 and correspond to the case where the oxide film patterns 250a are formed in the same shape as that of FIG. 21A. For convenience of illustration, only the bit line 160 and the narrowed oxide pattern 250b are shown. As shown in FIG. 21A, since the oxide pattern 250a is jagged to have the first width W21 and the second width W22, the bit line 160 is formed by the damascene method between the oxide pattern 250a. Is substantially a line type and has a relatively wide tap area 162.

Referring to FIG. 23, the oxide pattern patterns 250b having the reduced width are etched so that only the portion of the oxide pattern 250a having the second width W22 remains above the bit line 160. This can be understood that the thin oxide pattern portions that were between the tab regions 162 facing each other in the neighboring bit lines 160 are removed, and the remaining portions are left behind. The portion of the remaining oxide pattern 250c remaining above the bit line 160 is positioned directly on the portion 145 where the contact hole is to be formed. The etching of the oxide layer patterns 250b having the reduced width may be performed similarly to the steps described with reference to FIGS. 6 and 12, and thus a detailed description thereof will be omitted.

Next, referring to FIGS. 19 and 24, a mask film 280 is formed on the bit line 160 to be parallel to the top surface of the oxide film pattern 250c thus left. Then, the entire cell portion is covered with the mask layer 280, and the oxide layer pattern 250c is only visible on the region 145 where the contact hole is to be formed. Since this step may be performed similarly to the steps described with reference to FIGS. 7 and 13, a detailed description thereof will be omitted.

Referring to FIG. 20, a contact hole 147 is formed at a position where the remaining oxide layer pattern 250c is located by selectively removing the remaining oxide layer pattern 250c from the mask layer 280. When anisotropic etching is used to remove the remaining oxide pattern 250c, an oxide layer pattern 250d having a spacer shape is left around the bit line 160. If the etch stopper 220 exposed in the contact hole 147 is removed and the conductive material is filled, the contact can be completed by forming a storage node contact plug that is properly aligned as shown in FIG. 15. Since the contact hole 147 is not formed by photolithography, the process may be performed without considering the misalignment margin.

As mentioned above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical idea of the present invention. It is obvious. In the above embodiments, a case where a contact hole for a gate and a cell pad is formed in a DRAM and a case where a contact hole for a bit line and a storage node contact plug are formed is described as an example. Since the contact hole is formed while the damascene method is formed, it is applicable to the manufacture of semiconductor devices of any structure as long as it includes parallel wirings and contacts.

According to the present invention described above, if the photolithography is omitted and the etching is performed as it is along the pattern of the lower layer, a contact hole is formed by itself, so that the contact hole can be formed without having to consider a misalignment margin. Since the process is simplified and no misalignment margin needs to be considered, rapid design rules can be reduced, contributing to higher integration of semiconductor devices.

Claims (12)

(a) providing a semiconductor substrate; (b) forming an oxide pattern for a mold for forming interconnections parallel to each other on the semiconductor substrate, wherein the oxide pattern has a first width and has a second width greater than the first width for each portion where a contact hole is to be formed; Forming to have a width; (c) forming a damascene interconnection parallel to each other by partially filling a conductive material between the oxide layer patterns, and forming an oxide layer pattern above the interconnection so that only the portion having the second width in the oxide layer pattern remains above the interconnection line. Etching; (d) forming a mask film on the wiring to be parallel to the top surface of the oxide film pattern left after the step (c); And and (e) forming a contact hole in a place where the remaining oxide film pattern is located by selectively removing the remaining oxide film pattern with respect to the mask film. The method of claim 1, wherein step (c) comprises: Depositing a conductive material to cover the top surface of the oxide pattern and fill the gaps between the oxide pattern; And Etching back the upper surface of the resultant material on which the conductive material is deposited so as to recess the conductive material from the oxide pattern to form the damascene wires, and to leave only a portion of the oxide pattern having the second width above the wiring. Contact hole forming method comprising a. The method of claim 1, wherein step (c) comprises: Depositing a conductive material to cover the top surface of the oxide pattern and fill the gaps between the oxide pattern; And Etching back the upper surface of the resultant material on which the conductive material is deposited so as to recess the conductive material from the oxide pattern to form the damascene interconnects and simultaneously reduce the width of the oxide pattern above the interconnects; And And etching an oxide pattern having a reduced width so that only a portion of the oxide pattern having a second width remains above the wiring. The method of claim 3, wherein the etching of the oxide layer pattern having the reduced width is performed by dry etching, wet etching, or plasma etching. According to claim 1, wherein step (b), Forming an etch stopper on the semiconductor substrate; Forming an oxide film on the etch stopper; Patterning the oxide film to form the oxide film patterns exposing the etch stopper; And Removing the exposed etch stopper, and then forming a gate insulating film therein, wherein the wiring is a gate of a DRAM and the contact hole is formed to be a contact hole for a cell pad of the DRAM. Hole formation method. According to claim 1, wherein step (b), Forming an etch stopper on the semiconductor substrate; Forming an oxide film on the etch stopper; Patterning the oxide film to form the oxide film patterns exposing the etch stopper; And And removing the exposed etch stopper, wherein the wiring is a bit line of a DRAM and the contact hole is a contact hole for a storage node contact plug of the DRAM. The contact hole forming method according to claim 5 or 6, wherein the etch stopper has a thickness of 10 to 500 kPa and the oxide film has a thickness of 500 to 6000 kPa. The method of claim 1, wherein step (d) Depositing a mask material covering an upper surface of the remaining oxide pattern and completely filling the remaining oxide pattern; And And planarizing the top surface of the resultant material on which the mask material is deposited until the top surface of the remaining oxide pattern is exposed. The method of claim 8, wherein the planarization comprises dry etching or chemical mechanical polishing. The method of claim 8, wherein the mask material is deposited to a thickness of 500 to 10000 100. The method of claim 8, wherein the mask material is a material having a different etching selectivity from the oxide layer pattern and having excellent step coverage. 12. The method of claim 11, wherein the mask material is a silicon nitride film.