KR100257159B1 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
KR100257159B1
KR100257159B1 KR1019970044893A KR19970044893A KR100257159B1 KR 100257159 B1 KR100257159 B1 KR 100257159B1 KR 1019970044893 A KR1019970044893 A KR 1019970044893A KR 19970044893 A KR19970044893 A KR 19970044893A KR 100257159 B1 KR100257159 B1 KR 100257159B1
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South Korea
Prior art keywords
contact hole
forming
insulating
wiring
contact
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KR1019970044893A
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Korean (ko)
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KR19990021357A (en
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곽국희
정인술
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is to form a spacer on the sidewall of a contact hole, thereby isolating a gate electrode from the contact hole by the spacer. CONSTITUTION: A gate oxide layer(21) is formed on a semiconductor substrate(20). A gate electrode(22) is formed on the gate oxide layer. A gate sidewall spacer(23) is formed on the sidewall of the gate electrode. A source/drain(24) is formed in the semiconductor substrate on both side of the gate electrode. The first insulating layer(25) is formed on the entire structure. An interconnection mask is formed on the first insulating layer by a photolithography. An interconnection groove is formed by etching the first insulating layer. Then the interconnection mask is removed. The second insulating layer(29) is deposited on the entire structure at a predetermined thickness. A contact hole mask is formed on the second insulating layer. After etching the second and first insulating layer to be provided with a contact hole, the contact hole mask is removed. A spacer(29') of the second insulting layer is formed on the sidewall of the contact hole.

Description

반도체 소자의 제조 방법Manufacturing Method of Semiconductor Device

본 발명은 반도체 소자의 제조 방법에 관한 것으로써, 보다 구체적으로는 반도체 소자의 콘택홀 및 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming contact holes and metal wirings in a semiconductor device.

최근 반도체 소자의 제조 기술의 발달과 메모리 소자의 응용 분야가 확장되어감에 따라 대용량의 메모리 소자 개발이 진척되고 있는데, 이러한 메모리 소자의 대용량화는 각 세대 마다 2배로 진행하는 미세 프로세스 기술을 기본으로한 메모리 셀 연구에 의해 추진되어 오고 있다.Recently, as the development of semiconductor device manufacturing technology and the application of memory devices are expanded, the development of large-capacity memory devices is progressing, and the increase in the capacity of such memory devices is based on the micro process technology that is doubled for each generation. It has been promoted by memory cell research.

특히 반도체 장치에 있어서의 배선 기술은 메모리 소자의 미세화 기술에 있어서 중요한 항목중의 하나이며, 이러한 배선 기술은 메모리의 워드선과 같은 배선으로 사용되는 게이트 전극, 소오스/드레인 영역과 콘택 및 각 소자를 상호 접속하는 금속배선등으로 분류된다.In particular, the wiring technology in the semiconductor device is one of the important items in the miniaturization technology of the memory device, which is a gate electrode, a source / drain region and a contact used as wiring such as a word line of the memory, and each device It is classified as metal wiring etc. to connect.

종래의 콘택 홀 형성 방법 및 금속 배선 형성 방법에 대하여 제1a도 내지 1e도를 참조하여 설명하면 다음과 같다.A conventional method for forming a contact hole and a method for forming a metal wiring will be described below with reference to FIGS. 1A to 1E.

제1a도는 반도체 기판(10) 상의 게이트 산화막(11)상부에 형성된 게이트 전극(12)과, 게이트 전극의 측벽에 형성된 게이트 측벽 스페이서(13)와, 게이트 전극(12) 양측 하부의 반도체 기판(10)내에 형성된 소오스/드레인(14)과, 반도체 기판(10)의 상부 전면에 형성된 제1절연막(15)이 차례로 형성된다.FIG. 1A illustrates a gate electrode 12 formed on the gate oxide film 11 on the semiconductor substrate 10, a gate sidewall spacer 13 formed on sidewalls of the gate electrode, and a semiconductor substrate 10 below both sides of the gate electrode 12. ), The source / drain 14 formed therein and the first insulating film 15 formed over the upper surface of the semiconductor substrate 10 are sequentially formed.

제1b도에 도시된 바와 같이, 제1절연막(15)상의 소정 부분에 공지의 포토리소그래피 방식에 의하여 감광 물질로 된 배선 마스크(16)를 형성하고, 이의 형태로 절연막을 부분 식각하여 배선 홈(BH)을 형성한 후, 상기 마스크(16)을 공지의 방식으로 제거한다.As shown in FIG. 1B, a wiring mask 16 made of a photosensitive material is formed on a predetermined portion of the first insulating film 15 by a known photolithography method, and the insulating film is partially etched to form a wiring groove ( After forming BH), the mask 16 is removed in a known manner.

제1c도에서는 제1b도에 이어서 콘택홀(CH)을 형성하는 과정을 도시한다. 즉, 콘택홀 마스크(17)를 사용하여 콘택홀(CH)이 형성될 부분의 제1절연막(15)을 식각한다.FIG. 1C illustrates a process of forming the contact hole CH following FIG. 1B. That is, the first insulating layer 15 of the portion where the contact hole CH is to be formed is etched using the contact hole mask 17.

이어 제1d도와 1e도에서는 제1c도에 도시된 반도체 기판 상부 표면에 전도물질(18)을 침착한 후, 에치 백(Etch-Back) 등의 방법을 사용하여 상기 배선 홈(BH)와 콘택홀(CH)내에만 전도물질(18)이 존재하도록 다른 부분의 전도물질(18)을 제거하여 금속 배선을 형성하게 된다.Next, in FIGS. 1D and 1E, the conductive material 18 is deposited on the upper surface of the semiconductor substrate illustrated in FIG. 1C, and then the wiring groove BH and the contact hole are etched using a method such as an etch back. The conductive material 18 is removed so that the conductive material 18 exists only in the CH to form the metal wiring.

이러한 공정에 의해 형성되는 배선의 폭은, 현재 사용되는 노광장비의 해상도에 의하여 배선 마스크간의 최소 선폭이 한정되어 있다. 따라서 미세한 사이즈의 금속 배선 콘택홀을 형성하는 데에 어려움이 있다.As for the width of the wiring formed by such a process, the minimum line width between wiring masks is limited by the resolution of the exposure equipment currently used. Therefore, it is difficult to form a fine sized metal wiring contact hole.

또한 이러한 상기한 콘택홀 및 배선 홈의 형성에 있어서, 제1b도에 도시된 배선 마스크(16)와 제1c도에 도시된 콘택홀 마스크(17)의 미스얼라인(misalign)에 의해 배선 홈(BH) 또는 콘택홀(CH)이 게이트 전극(12)에 접촉하게 되는 경우가 발생하게 된다. 이에 따라 후속 공정의 전도물질(18)이 게이트 전극과 접촉하게 되는 문제점이 발생하게 된다.Further, in the formation of the above-described contact hole and wiring groove, the wiring groove 16 is misaligned by the misalignment of the wiring mask 16 shown in FIG. 1B and the contact hole mask 17 shown in FIG. 1C. The case where the BH or the contact hole CH comes into contact with the gate electrode 12 may occur. This causes a problem that the conductive material 18 of the subsequent process comes into contact with the gate electrode.

이러한 문제점의 발생을 방지하기 위하여 배선 마스크(16)와 콘택홀 마스크(17) 상에서 콘택홀 위치와 게이트 전극 사이에 필요 이상의 간격을 요구하게 된다. 이것은 반도체 소자의 고밀도화의 장애 요인이 되고 있다.In order to prevent the occurrence of such a problem, more than necessary spacing between the contact hole position and the gate electrode on the wiring mask 16 and the contact hole mask 17 is required. This is a barrier to higher density of semiconductor devices.

따라서, 본 발명은, 배선 형성 영역의 절연막을 부분 식각한 후, 콘택홀 형성 공정 이전에 제2절연막을 일정 두께로 침착하여 콘택홀 내부의 측벽에 스페이서를 형성하도록 하므로써, 콘택홀과 게이트 전극과의 절연을 보장하도록 하는 것을 목적으로 한다.Therefore, according to the present invention, after the partial etching of the insulating film in the wiring formation region and before the contact hole forming process, the second insulating film is deposited to a predetermined thickness to form a spacer on the sidewall inside the contact hole. Its purpose is to ensure insulation.

제1도 내지 1e도는 종래의 방법에 따라 금속 배선 및 콘택홀을 형성하는 과정을 도시한 단면도.1 through 1e are cross-sectional views illustrating a process of forming metal wirings and contact holes according to a conventional method.

제2a도 내지 2f도는 본 발명에 따라 금속 배선 및 콘택트 홀을 형성하는 과정을 도시한 단면도.2A to 2F are cross-sectional views illustrating a process of forming metal wirings and contact holes according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10, 20 : 기판 11, 21 : 게이트 산화막10, 20: substrate 11, 21: gate oxide film

12, 22 : 게이트 전극 13, 23 : 게이트 측벽 스페이서12, 22: gate electrode 13, 23: gate sidewall spacer

14, 24 : 소오스/드레인 영역 15, 25 : 제1절연막14, 24: source / drain regions 15, 25: first insulating film

16, 26 : 배선 마스크 17, 27 : 콘택홀 마스크16, 26: wiring mask 17, 27: contact hole mask

18, 28 : 전도 물질 29 : 제2절연막18, 28: conductive material 29: second insulating film

29' : 측벽 스페이서 CH : 콘택홀29 ': sidewall spacer CH: contact hole

BH : 배선 홈BH: Wiring Groove

상기한 본 발명의 목적을 달성하기 위하여, 본 발명은 다수개의 도전 영역을 구비한 반도체 기판상에 제1절연막을 형성하는 단계; 상기 다수개의 도전 영역상의 제1절연막을 소정 부분 식각하여 배선홈을 형성하는 단계; 상기 배선홈에서 콘택이 형성될 부분에, 상기 도전 영역이 노출되도록 콘택홀을 형성하는 단계를 포함하며, 상기 콘택홀을 형성하는 단계는 상기 배선홈이 형성된 결과물 상부에 제2절연막을 증착하는 단계와, 상기 콘택홀이 형성될 영역을 정의하는 마스크 패턴을 형성하는 단계와, 상기 마스크 패턴을 이용하여 상기 도전 영역중 콘택이 형성될 부분이 노출되도록 제2절연막 및 제1절연막을 순차적으로 식각하여 콘택홀을 형성하면서, 콘택홀에 스페이서를 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention comprises the steps of forming a first insulating film on a semiconductor substrate having a plurality of conductive regions; Etching a predetermined portion of the first insulating films on the plurality of conductive regions to form wiring grooves; Forming a contact hole in the portion where the contact is to be formed in the interconnection groove so that the conductive region is exposed, and forming the contact hole comprises depositing a second insulating layer on the resultant product in which the interconnection groove is formed And forming a mask pattern defining a region where the contact hole is to be formed, and sequentially etching the second insulating layer and the first insulating layer to expose a portion of the conductive region where the contact is to be formed using the mask pattern. Forming a contact hole, characterized in that it comprises the step of forming a spacer in the contact hole.

본 발명의 반도체 제조 방법에 따라 한 도전영역상에 금속 배선을 형성한 경우, 상기 도전 영역 상부의 배선홈 및 콘택홀내에 제2절연막 측벽 스페이서가 형성되므로 마스크 패턴의 폭보다 좁은 금속배선을 형성할 수 있으며, 금속 배선은 상기 도전 영역과 인접한 다른 도전 영역으로부터 절연시킬 수 있게 된다.According to the semiconductor manufacturing method of the present invention, when the metal wiring is formed on one conductive region, the second insulating film sidewall spacer is formed in the wiring groove and the contact hole above the conductive region, so that the metal wiring narrower than the width of the mask pattern can be formed. The metal wires can be insulated from other conductive areas adjacent to the conductive areas.

[실시예]EXAMPLE

이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제2a 내지 2e도를 참조하여 본 발명에 따른 반도체 소자의 배선 홈 및 콘택홀의 제조 과정을 설명하면 다음과 같다.Referring to Figures 2a to 2e will be described the manufacturing process of the wiring groove and the contact hole of the semiconductor device according to the present invention.

제2a도를 참조하면, 반도체 기판(20)상에 게이트 산화막(21)상부에 형성된 게이트 전극(22)과, 게이트 전극의 측벽에 형성된 게이트 측벽 스페이서(23)와, 게이트 전극(22) 양측 하부의 반도체 기판(20)내에 형성된 소오스/드레인(24)과, 반도체 기판(20)의 상부 전면에 형성된 제1절연막(25)이 차례로 형성된다.Referring to FIG. 2A, the gate electrode 22 formed on the gate oxide film 21 on the semiconductor substrate 20, the gate sidewall spacers 23 formed on the sidewalls of the gate electrode, and lower portions of both sides of the gate electrode 22. The source / drain 24 formed in the semiconductor substrate 20 and the first insulating film 25 formed on the entire upper surface of the semiconductor substrate 20 are sequentially formed.

이어 제1절연막(25)의 상부면에 공지의 포토리소 그래피 방식에 의하여 감광 물질로 된 배선 마스크(26)를 형성하고, 이의 형태로 절연막을 식각하여 배선홈(BH)을 형성한 후, 상기 마스크(26)을 공지의 방식을 제거한다.Subsequently, a wiring mask 26 made of a photosensitive material is formed on the upper surface of the first insulating layer 25 by a known photolithography method, and the insulating layer is etched to form the wiring groove BH. Mask 26 removes the known manner.

다음으로, 기판 상부 전면에 걸쳐 제2절연막을 일정 두께로 침착한 후, 제2절연막상부에 콘택홀 마스크(27)를 사용하여, 포토리소그래피법으로 콘택홀(CH)이 형성될 영역의 제2절연막 및 제1절연막을 순차적으로 식각한 후, 콘택홀 마스크(27)을 제거한다.Next, after the second insulating film is deposited to a predetermined thickness over the entire upper surface of the substrate, the contact hole mask 27 is used on the second insulating film, and the second area of the region where the contact hole CH is to be formed by photolithography. After sequentially etching the insulating film and the first insulating film, the contact hole mask 27 is removed.

이때, 콘택홀 마스크(27)에 의하여 배선 홈(BH)내의 제2절연막(29)은 제거되지 않으며, 콘택홀(CH)의 내부에 있어서의 식각은 소스/드레인 영역(24)이 노출되도록 제2 및 제1절연막(25)에 이르도록 제2절연막의 식각이 순차적으로 이루어지며, 콘택홀(CH)의 측벽에 제2절연막(29)의 스페이서(29')가 형성된다. 따라서 배선 홈(BH)과 콘택홀(CH)의 크기는 배선 마스크(26)와 콘택홀 마스크(27)의 폭보다 작게 형성된다. 이어 기판 상부 전면에 전도물질(28)을 침착한후, 배선 홈(BH)과 콘택홀(CH)의 내부에만 상기 전도 물질(28)이 존재하도록 에치백 또는 CMP법으로 다른 부위의 전도 물질을 제거한다.In this case, the second insulating layer 29 in the wiring groove BH is not removed by the contact hole mask 27, and etching in the contact hole CH is performed so that the source / drain region 24 is exposed. The second insulating layer is sequentially etched to reach the second and first insulating layers 25, and the spacers 29 ′ of the second insulating layers 29 are formed on the sidewalls of the contact holes CH. Therefore, the sizes of the wiring grooves BH and the contact holes CH are smaller than the widths of the wiring mask 26 and the contact hole mask 27. Subsequently, after the conductive material 28 is deposited on the entire upper surface of the substrate, the conductive material 28 is etched back or CMP so that the conductive material 28 exists only inside the wiring grooves BH and the contact holes CH. Remove

상기한 바와 같이 콘택홀과 배선이 동시에 형성됨과 동시에 제2절연막 스페이서는 배선 및 콘택홀 마스크의 미스얼라인에 의하여 배선 홈 또는 콘택홀이 게이트 전극에 접촉되는 것을 방지한다.As described above, the contact hole and the wiring are simultaneously formed, and the second insulating layer spacer prevents the wiring groove or the contact hole from contacting the gate electrode by the misalignment of the wiring and the contact hole mask.

이상에서와 같이, 콘택홀 형성 영역과 게이트 전극 사이의 거리가 짧아도 제2절연막 스페이서에 의해 절연이 이루어지도록 하므로써, 제2절연막 스페이서에 의하여 콘택트 홀과 게이트 전극사이가 절연된다.As described above, even if the distance between the contact hole forming region and the gate electrode is short, insulation is performed by the second insulating film spacer, so that the contact hole and the gate electrode are insulated by the second insulating film spacer.

따라서, 배선 마스크나 콘택홀 마스크의 미스얼라인에 의해 콘택홀 가까이에 위치한 게이트 전극과 콘택 전도 물질의 접촉이 이루어지면 절연이 되지 않는 경우를 고려하여, 콘택홀 형성 영역과 게이트 전극 사이의 간격을 필요 이상으로 크게 하던 종래의 문제점을 해결할 수 있다. 즉, 반도체 소자의 고밀도화가 가능해진다.Therefore, the gap between the contact hole forming region and the gate electrode is considered in consideration of the case where the contact between the gate electrode located near the contact hole and the contact conductive material is not caused by the misalignment of the wiring mask or the contact hole mask. It is possible to solve the conventional problem of making it larger than necessary. In other words, the semiconductor element can be densified.

또한 배선홈 측벽에 제2절연막 스페이서가 형성되므로 배선폭이 배선 마스크의 허용 최소 선폭 보다 작아지므로 배선 전도 물질의 폭이 줄어들게 된다. 따라서, 배선과 배선 간의 거리가 멀어지므로, 소자의 고밀도화는 물론, 배선간의 상호 작용과, 커플링 캐패시턴스 등과 같은 기생 효과를 줄일 수 있다.In addition, since the second insulating film spacer is formed on the sidewall of the wiring groove, the width of the wiring is smaller than the minimum allowable line width of the wiring mask, thereby reducing the width of the wiring conductive material. Therefore, since the distance between the wiring and the wiring is increased, not only the density of the device can be increased, but also the parasitic effects such as the interaction between the wiring and the coupling capacitance and the like can be reduced.

Claims (7)

다수개의 도전 영역을 구비한 반도체 기판상에 제1절연막을 형성하는 단계; 상기 다수개의 도전 영역상의 제1절연막을 소정 부분 식각하여 배선홈을 형성하는 단계; 상기 배선홈에서 콘택이 형성될 부분에, 상기 도전 영역이 노출되도록 콘택홀을 형성하는 단계를 포함하며, 상기 콘택홀을 형성하는 단계는 상기 배선홈이 형성된 결과를 상부에 제2절연막을 증착하는 단계와, 상기 콘택홀이 형성될 영역을 정의하는 마스크 패턴을 형성하는 단계와, 상기 마스크 패턴을 이용하여 상기 도전 영역중 콘택이 형성될 부분이 노출되도록 제2절연막 및 제1절연막을 순차적으로 식각하여 콘택홀을 형성하면서, 콘택홀에 스페이서를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Forming a first insulating film on a semiconductor substrate having a plurality of conductive regions; Etching a predetermined portion of the first insulating films on the plurality of conductive regions to form wiring grooves; And forming a contact hole in the portion where the contact is to be formed in the wiring groove so that the conductive region is exposed, wherein forming the contact hole comprises depositing a second insulating layer on the result of the formation of the wiring groove. Forming a mask pattern defining a region in which the contact hole is to be formed, and sequentially etching the second insulating layer and the first insulating layer to expose a portion of the conductive region where the contact is to be formed using the mask pattern. Forming a spacer in the contact hole while forming the contact hole. 제1항에 있어서, 제1절연막이 산화막, 질화막, 산화 질화막, 실리케니트 유리질 또는 반도체 제조 공정에서 절연을 목적으로 사용되는 절연물질인 것을 특징으로 하는 반도체 소자의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is an insulating material used for insulating purposes in an oxide film, a nitride film, an oxynitride film, a silicate glass, or a semiconductor manufacturing process. 제1항에 있어서, 제2절연막이 산화막, 질화막, 산화 질화막, 실리케이트 유리질 또는 반도체 제조 공정에서 절연을 목적으로 사용되는 절연물질인 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the second insulating film is an oxide material, a nitride film, an oxynitride film, a silicate glass, or an insulating material used for insulating purposes in a semiconductor manufacturing process. 제1항에 있어서, 상기 콘택홀을 형성한 후, 배선홈 및 콘택홀내에 전도 물질을 매립하여, 배선홈의 배선과, 콘택홀의 콘택을 동시에 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.The semiconductor device of claim 1, further comprising, after forming the contact hole, embedding a conductive material in the wiring groove and the contact hole to simultaneously form the wiring of the wiring groove and the contact of the contact hole. Manufacturing method. 다수개의 도전 영역을 구비한 반도체 기판상에 제1절연막을 형성하는 단계; 상기 다수개의 도전 영역상의 제1절연막을 소정 부분 식각하여 배선홈을 형성하는 단계; 상기 배선홈에서 콘택이 형성될 부분에 상기 도전 영역이 노출되도록 콘택홀을 형성하는 단계; 배선홈 및 콘택홀내에 전도 물질을 매립하여, 배선홈의 배선과 콘택홀의 콘택을 동시에 형성하는 단계를 포함하며, 상기 콘택홀을 형성하는 단계는, 상기 배선홈이 형성된 결과물 상부에 콘택홀이 형성될 영역을 정의하는 마스크 패턴을 형성하는 단계와; 상기 마스크 패턴을 이용하여 제1절연막 저면의 상기 도전 영역중 콘택 형성 영역이 노출되도록 제1절연막을 식각하는 단계와; 상기 제1절연막이 식각된 결과물 상부 저면에 제2절연막을 증착한 후, 다시 동일 두께만큼 식각하여, 도전 영역중 콘택 형성 영역이 노출되면서 배선 홈과 콘택홀 측벽에는 제2절연막으로 된 스페이서를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Forming a first insulating film on a semiconductor substrate having a plurality of conductive regions; Etching a predetermined portion of the first insulating films on the plurality of conductive regions to form wiring grooves; Forming a contact hole in the wiring groove so that the conductive region is exposed in a portion where a contact is to be formed; Embedding a conductive material in the wiring groove and the contact hole, and simultaneously forming the wiring of the wiring groove and the contact of the contact hole, wherein the forming the contact hole includes forming a contact hole on an upper portion of the resultant product in which the wiring groove is formed. Forming a mask pattern defining a region to be; Etching the first insulating layer using the mask pattern to expose the contact forming region of the conductive region on the bottom surface of the first insulating layer; After depositing the second insulating film on the bottom surface of the resultant, the first insulating film is etched, the second insulating film is etched to the same thickness again, the contact forming region of the conductive region is exposed to form a spacer of the second insulating layer on the wiring groove and the contact hole sidewalls Method of manufacturing a semiconductor device comprising the step of. 제5항에 있어서, 제1절연막이 산화막, 질화막, 산화 질화막, 실리케이트 유리질 또는 반도체 제조 공정에서 절연을 목적으로 사용되는 절연물질인 것을 특징으로 하는 반도체 소자의 제조 방법.The method of manufacturing a semiconductor device according to claim 5, wherein the first insulating film is an oxide material, an nitride film, an oxynitride film, silicate glass, or an insulating material used for insulating purposes in a semiconductor manufacturing process. 제6항에 있어서, 제2절연막이 산화막, 질화막, 산화 질화막, 실리케이트 유리질 또는 반도체 제조 공정에서 절연을 목적으로 사용되는 절연물질인 것을 특징으로 하는 반도체 소자의 제조 방법.The method of manufacturing a semiconductor device according to claim 6, wherein the second insulating film is an insulating material used for insulating purposes in an oxide film, a nitride film, an oxynitride film, a silicate glass, or a semiconductor manufacturing process.
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