KR0126647B1 - Connection device & manufacturing method of semiconductor - Google Patents
Connection device & manufacturing method of semiconductorInfo
- Publication number
- KR0126647B1 KR0126647B1 KR1019940005251A KR19940005251A KR0126647B1 KR 0126647 B1 KR0126647 B1 KR 0126647B1 KR 1019940005251 A KR1019940005251 A KR 1019940005251A KR 19940005251 A KR19940005251 A KR 19940005251A KR 0126647 B1 KR0126647 B1 KR 0126647B1
- Authority
- KR
- South Korea
- Prior art keywords
- contact
- gate electrode
- forming
- insulating layer
- etching
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 41
- 239000011229 interlayer Substances 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000779 smoke Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1도 내지 제5도는 본 발명에 의한 실시예로 반도체소자의 접속장치 및 제조공정 단면도.1 to 5 are cross-sectional views of a semiconductor device connecting device and a fabrication process in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
l : 반도체기판 2 : 소자분리 절연막l: semiconductor substrate 2: device isolation insulating film
3 : 게이트 산화막 4 : 게이트 전극3: gate oxide film 4: gate electrode
5 : 제 1 절연막 6 : 소오스/드레인전극5: first insulating film 6: source / drain electrode
7 : 제 2 절연막 8 : 식각장벽층7: second insulating film 8: etching barrier layer
9 : 제 3 절연막 9' : 제 3 절연막패턴9: third insulating film 9 ': third insulating film pattern
l0 : 제 4 절연막 스페이서 11 : 전극선 연결선l0: fourth insulating film spacer 11: electrode wire connecting line
17 : 콘택홀 30 : 필드오픈 마스크17: contact hole 30: field open mask
31 : 콘택마스크31: contact mask
본 발명은 반도체소자의 접속장치 및 제조방법에 관한 것으로, 반도체기판 상부에 필드산화막, 게이트전극 및 소오스/드레인 전극을 형성한 후, 상부에 제1절연막, 제2절면막 및 식각장벽증을 형성하고 제3절연막을 사용하여 평탄화층을 형성한 다음, 그 상부에 상기 게이트전극에 이웃하는 콘택홀을 형성하기 위한 콘택마스크와 상기 게이트전극 상부에 콘택홀을 형성하기 위한 콘택마스크를 형성하고 상기 콘택마스크를 사용하여 하부의 제3절연막을 식각하고 계속하여 하부의 식각장벽막과 제2절연막을 일정두께 식각하여 자기정렬적인 콘택홀을 각각 하나씩 형성하는 동시에 상기 게이트전극의 측벽에 층간절연막 역할의 제2절연막 스페이서를 형성하고 상기 두 콘택홈을 매립하는 전극선연결선을 각각 형성함으로써 반도체소자에 자기정렬적인 콘택홀을 형성하여 콘택홀 형성시 식각손상에 의한 접합 누설전류의 발생가능성을 최소화하며, 상기 소오스/드레인 전극과 게이트전극의 상부에 자기정렬적으로 콘택홀을 형성함으로써 소자의 면적을 감소시켜 과집적화를 가능하게하며 소자의 생산성을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection device and a manufacturing method of a semiconductor device, wherein a field oxide film, a gate electrode, and a source / drain electrode are formed on a semiconductor substrate, and a first insulating film, a second section film, and an etch barrier are formed thereon. And forming a planarization layer using a third insulating layer, and forming a contact mask for forming a contact hole adjacent to the gate electrode on the top and a contact mask for forming a contact hole on the gate electrode. The lower third insulating layer is etched using a mask, and the lower etch barrier layer and the second insulating layer are etched to a predetermined thickness to form a self-aligning contact hole, one at a time, and at the same time, the second insulating layer acts as an interlayer insulating layer on the sidewall of the gate electrode. 2 Self-aligning the semiconductor device by forming insulating film spacers and forming electrode line connecting lines filling the two contact grooves, respectively. Minimizes the possibility of junction leakage current due to etch damage when forming contact holes, and forms contact holes on top of the source / drain electrodes and the gate electrodes to reduce the area of the device, thereby over-integrating It is a technology that enables and improves the productivity of the device.
특히 식각장벽층을 이용하여 소오스/드레인 전극 및 게이트전극에 대한 자기정렬형 접속장치를 제공하여 반도체장치의 고집적화를 달성하는 것을 특정으로 한다.In particular, it is specified that a high integration of the semiconductor device is achieved by providing a self-aligned connection device to the source / drain electrodes and the gate electrode using the etching barrier layer.
일반적으로 반도체소자를 제조하는데 있어서 상호연결용 전도선을 게이트에 이웃한 소오스/드레인 전극에 접속시키기 위한 콘택을 형성하기 위해서 게이트 전극과는 절연되어야 하므로 게이트전극 마스크와 콘택마스크를 설계하는데 있어서 일정한 설계규칙이 필요하다. 또한 전극선 연결선을 게이트에 접속시키기 위한 콘택홀 형성하기 위해서도 게이트전극 마스크와 콘택마스크를 설계하는데 있어서 일정한 설계규칙이 필요하다. 즉, 게이트전극 마스크와 콘택마스크 사이는 마스크제작 밋 웨이퍼상에서의 사진식각 공정중에 발생될수 있는 씨.디(CD. Critical Dimension, 이하에서 CD라 함) 변화 및 마스크 정렬시 발생될 수 있는 미스얼라인 톨러런스(misalignment tolerance)등을 고려해야 하므로 소자의 면적이 그만큼 커지게 된다.In general, in manufacturing a semiconductor device, a constant design is required in designing a gate electrode mask and a contact mask because the gate electrode must be insulated from the gate electrode in order to form a contact for connecting the interconnection conductor to a source / drain electrode adjacent to the gate. I need a rule. In addition, in order to form a contact hole for connecting the electrode line connecting line to the gate, a certain design rule is required in designing the gate electrode mask and the contact mask. In other words, the gap between the gate electrode mask and the contact mask can be generated during the photolithography process on the mask fabrication wafer, and the misalignment that can occur during the mask alignment. Consideration of misalignment tolerance, etc., makes the area of the device that much larger.
상기한 단점은 특히 고집적화 공정시 많은 문제점을 유발시킨다. 그래서 상기 문제점을 해결하기 위하여반도체소자에 콘택홀을 자기정결적으로 형성하지만 상기 콘택홀 형성방법은 소오스/드레인 전극에만 적용되고, 게이트전극에 형성되는 콘택은 별도로 일반적인 콘택형성을 사용함으로써 접속장치의 면적장소에 제한이 되어왔다.The above disadvantages cause many problems, especially in the high integration process. Therefore, in order to solve the above problems, contact holes are formed in the semiconductor device in a self-cleaning manner. However, the contact hole forming method is applied only to the source / drain electrodes, and the contacts formed on the gate electrodes are separately formed by using general contact formation. The area has been limited.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 반도체기판 상부에 형성된 소오스/드레인 전극에 자기정렬형 콘택홀을 형성하면서 동시에 게이트전극에도 자기정렬형 콘택홀을 형성함으로써 면적을 감소시켜 반도체소자의 고집적화를 이룰 수 있는 반도체소자의 접속장치 및 제조에 그 목적이 있다.Therefore, in order to solve the above problem, the present invention forms a self-aligned contact hole in the source / drain electrode formed on the semiconductor substrate and at the same time forms a self-aligned contact hole in the gate electrode to reduce the area, thereby increasing the integration of the semiconductor device. Its purpose is to provide a device and a connection device for a semiconductor device.
이상의 목적을 달성하기 위한 본 발명의 특정은, 소오스/드레인 전극에 형성된 콘택 측벽에는 게이트전극에 대하여 자기정렬되었고, 상기 소오스/드레인 전극에 형성된 콘택 측벽에는 게이트전극과 제1절연막과 제2절연막과 식각장벽층 그리고 제3절연막이 접하여 절연되어 형성되었고, 게이트전극 상부에 형성되는 콘택은 하부의 전도선, 즉 기판에 대하여 자기정렬되었고, 상기 게이트전극에 형성된 콘택 측벽에는 제2절연막과 식각장벽층 그리고 제3절연막이 접하여 절연된 것이다.A specific aspect of the present invention for achieving the above object is that the contact sidewalls formed on the source / drain electrodes are self-aligned with respect to the gate electrodes, and the contact sidewalls formed on the source / drain electrodes include the gate electrode, the first insulating film and the second insulating film; The etch barrier layer and the third insulating layer are in contact with each other, and are formed in contact with each other. The contact formed on the gate electrode is self-aligned with respect to the lower conductive line, that is, the substrate, and the second insulating layer and the etch barrier layer are formed on the contact sidewall formed on the gate electrode. The third insulating film is in contact with and insulated.
이상의 다른 목적을 달성하기 위한 본 발명의 특징은, 반도체기판 상부에 소자분리 절연막을 형성하고 게이트산화막과 게이트전극용 전도층을 형성한 다음, 그 상부에 제1절연막을 증착하고 필드오픈 마스크를 형성하는 공정과, 상기 필드오픈 마스크를 이용하여 게이트전극 상부에 자기정렬적으로 콘택홀을 형성할 부위의 게이트전극 상부에 제1절연막을 식각하는 공정과, 게이트전극과 소오스/드레인 전극을 형성하고 전체구조상부에 제2절연막과 식각장벽층을 일정두께 증착하고 제3절연막을 형성하는 공정과, 상기 제3절연막상부에 콘텍홀을 형성하기 위한 콘택마스크를 감광막을 이용하여 형성하는 공정과, 상기 콘택마스크를 이용하고 상기 식각장벽층을 식각장벽으로 한여 상기 제3질연막을 식각하고 계속하여 식각장벽층 및 일정두께의 제2절연막을 순차적으로 식각함으로써 반도체기판 상부와 게이트전극의 상부에 콘택홀을 형성하는 공정을 포함하는데 있다.A feature of the present invention for achieving the above another object is to form a device isolation insulating film on the semiconductor substrate, and to form a gate oxide film and a conductive layer for the gate electrode, and then to deposit a first insulating film thereon and to form a field-open mask And etching the first insulating layer on the gate electrode at the portion where the contact hole is to be self-aligned on the gate electrode by using the field-open mask, forming a gate electrode and a source / drain electrode Depositing a second insulating film and an etch barrier layer on the structure to form a third insulating film, and forming a contact mask for forming a contact hole on the third insulating film by using a photosensitive film; Using a mask and using the etch barrier layer as an etch barrier, the third vaginal layer is etched, and then the etch barrier layer and the predetermined thickness of the second section The method includes forming a contact hole on the semiconductor substrate and the gate electrode by sequentially etching the smoke film.
이하 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1도 내지 제5도는 본 발명의 실시예로 반도체소자의 접속장치 및 제조공정을 도시한 단면도이다.1 to 5 are cross-sectional views showing the connection device and manufacturing process of a semiconductor device in an embodiment of the present invention.
제1도는 반도체기판(l) 상부에 소자분리 산화막(2), 게이트산화막(3), 게이트전극용 전도층(4) 및 제1절연막(5)을 형성하고 필드오픈 마스크(30)을 형성한 것을 도시한 단면도로서, 상기 필드오픈 마스크(30)는 게이트전극(4) 상부에 자기정렬형 콘택홀이 형성될 부분이 노출되도록 형성한 것이다·1 shows a device isolation oxide film 2, a gate oxide film 3, a gate electrode conductive layer 4 and a first insulating film 5 formed on the semiconductor substrate 1 and a field-open mask 30 formed thereon. The field-open mask 30 is formed to expose a portion where a self-aligned contact hole is to be formed on the gate electrode 4.
제2도는 상기 필드오픈 마스크(30)를 이용하여 게이트전극 상부에 자기정렬형 콘택홀이 형성될 부분의 게이트전극(4) 상부의 제1절연막(5)을 선택적으로 식각하고, 게이트전극(4)과 소오스/드레인 전극(6)을 형성한 다음, 제2절연막(7)과 식각장벽층(8)을 형성하고 그 상부에 제3절연막(9)으로 평탄화증을 형성한 다음, 상기 반도체기판(1)의 상부에 콘택홀을 형성하기 위한 감광막패턴, 즉 콘택마스크(31)를 형성한 것을 도시한 단면도이다. 여기서, 상기 제1절연막(5)은 습식식각을 이용하여 형성함으로써 상기 소오스/드레인 전극(6)의 손상을 최소화하머, 상기 식각장벽층(8)은 전도물질 또는 절연막을 사용하여 형성하고 상기 제3절연막(9)은 비 피 에스 지(Boro-Phospho-Siligate-Glass, 이하에서 BPSG라 함) 사용하여 형성한다. 그리고, 상기 소오스/드레인 전극(6) 상부에 콘택마스크(31)는 이웃한 게이트전극(4)과 겹쳐 있고, 게이트전극(4) 상부의 콘택마스크(31)는 상기 게이트전극(4) 상부에 형성된 각각의 층(7,8,9)이 일정두께 식각되어도 상기 반도체기판(l)이 노출되지 않도륵 형성한다.FIG. 2 selectively etches the first insulating layer 5 on the gate electrode 4 in the portion where the self-aligned contact hole is to be formed on the gate electrode by using the field open mask 30. ) And a source / drain electrode 6, then a second insulating film 7 and an etch barrier layer 8 are formed, and a planarization film is formed on the upper portion of the semiconductor substrate by using a third insulating film 9 thereon. It is sectional drawing which shows the formation of the photosensitive film pattern, ie, the contact mask 31 for forming a contact hole in the upper part of (1). Here, the first insulating layer 5 is formed by using wet etching to minimize damage to the source / drain electrodes 6, and the etch barrier layer 8 is formed using a conductive material or an insulating layer, and 3 insulating film 9 is formed by using BOSG (Boro-Phospho-Siligate-Glass, hereinafter referred to as BPSG). The contact mask 31 overlaps the neighboring gate electrode 4 on the source / drain electrode 6, and the contact mask 31 on the gate electrode 4 is disposed on the gate electrode 4. Even if each of the layers 7, 8, and 9 formed is etched to a certain thickness, the semiconductor substrate 1 is formed without being exposed.
제3도는 상기 콘택마스크(3l)를 이용하고 상기 식각장벽층(8)을 식각장벽으로 하여 평탄화된 제3절연막(9)을 식각한 것을 도시한 단면도이다.FIG. 3 is a cross-sectional view illustrating the etching of the planarized third insulating layer 9 using the contact mask 3l and the etching barrier layer 8 as an etching barrier.
제4도는 상기 제3도의 공정후에 계속하여 상기 식각상벽층(8)과 제2절연막(7)을 일정두께 식각함으로써 상기 게이트전극(4)의 측벽에 제2절연막 스페이서(15)를 형성함과 동시에 상기 반도체기판(1)과 게이트전극(4)의 상부에 콘택헐(l7,19)을 형성한 것을 도시한 단면도이다 여기서, 상기 게이트전극(4)의 상부에 콘택홀을 형성하는 부위에는 콘택이 게이트전극에서 벗어나 있어도 일정두께의 제2절연막(7)을 식각함으로써 하부의 반도체기판(l)이 노출되지 않는다 상기 제2절연막 스페이서(15)는 층간절연막의 역할을 한다.FIG. 4 shows that the second insulating film spacers 15 are formed on the sidewalls of the gate electrode 4 by etching the etched wall layer 8 and the second insulating film 7 to a predetermined thickness after the process of FIG. At the same time, it is a cross-sectional view illustrating the formation of contact hulls 1, 7 and 19 on the semiconductor substrate 1 and the gate electrode 4. Here, the contact is formed on a portion where the contact hole is formed on the gate electrode 4. Even if the gate electrode is separated from the gate electrode, the lower semiconductor substrate 1 is not exposed by etching the second insulating film 7 having a predetermined thickness. The second insulating film spacer 15 serves as an interlayer insulating film.
제5도는 상기 식각장벽층(8)이 실리콘과 같은 전도물질인 경우 콘택측벽에 노출된 실리콘막 측벽에 절연막을 형성하기 위한 공정으로서, 상부구조전체에 제4절연막을 일정두께 중착하고 이방성식각하여 제4절연막 스페이서(10)를 형성한 다음, 상기 두 콘택홀(l7,19)에 접속되는 전극선 연결선(1l)을 형성함으로써 반도체소자의 콘택홀 형성한 것을 도시한 단면도이다.FIG. 5 is a process for forming an insulating film on the sidewall of the silicon film exposed to the contact side wall when the etch barrier layer 8 is a conductive material such as silicon. After forming the fourth insulating film spacer 10 and forming the electrode hole connecting line 11 connected to the two contact holes 1, 19, a cross-sectional view showing the formation of the contact hole of the semiconductor device.
상기한 본 발명에 의하면, 반도체상부에 형성된 소오스/드례인 전극이 식각시 손상되는 것을 방지하며 상기 손상에 의한 접합 누설전류의 밭생가능성을 최소화할 수 있고, 동시에 게이트전극에 자기정렬형 콘텍을 형성함으로써 접속장치의 면적을 감소시겨 반도체장치의 고집적화를 달성할 수 있어 반도체소자의 생산성을향상시키는 기술이다.According to the present invention, it is possible to prevent the source / excitation electrode formed on the semiconductor from being damaged during etching and to minimize the possibility of field leakage of the junction leakage current due to the damage, and at the same time to form a self-aligned contact on the gate electrode. By reducing the area of the connection device, high integration of the semiconductor device can be achieved, thereby improving the productivity of the semiconductor device.
Claims (6)
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| KR102690660B1 (en) | 2024-02-16 | 2024-08-05 | 주식회사 다현산업 | method for repairing concrete and asphalt road using composition FOR REPAIRING ROAD and composition for Acrylic Film Sealer |
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| KR102690660B1 (en) | 2024-02-16 | 2024-08-05 | 주식회사 다현산업 | method for repairing concrete and asphalt road using composition FOR REPAIRING ROAD and composition for Acrylic Film Sealer |
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