KR0131738B1 - Manufacturing method of semiconductor - Google Patents

Abstract

The method is for enhancing the integration and the reliability of a semiconductor device by preventing the short of the conduction line. The method comprises the processes of: forming an isolation film, a gate electrode, a source and a drain electrode, and forming a first insulating film on top of the gate; forming a planarization layer and a bit line contact mask on top of the drain electrode after forming a second insulating film and a conduction film; forming an insulating spacer on the side wall of the gate electrode and forming a bit line contact hole; forming an insulating spacer on the side wall where the conduction film is formed; forming an etch-barrier layer after forming a bit line and a planarization layer; forming a charge-storage electrode contact mask; etching the bit line; etching the third insulating film and the conduction film; and forming a charge storage electrode contact hole connected to the contact hole.

Description

Manufacturing method of semiconductor device

1A to 1G are sectional views showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

* Explanation of the code for the main parts in the drawing

1 semiconductor substrate 2 device isolation insulating film

3: gate oxide film 4: gate electrode

5: first insulating film 6: drain electrode

6 ': source electrode 7: second insulating film

8: Coupling prevention conductive film 9: Third insulating film

10 bit line contact mask 11 first insulating film spacer

12 bit line 13 fourth insulating film

14 etch barrier layer 15 charge preservation electrode contact mask

16 oxide film 17 second insulating film spacer

18: charge preservation electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a highly integrated semiconductor device, comprising: a capacitor couple having a predetermined potential between an insulating film between a word line gate electrode and a bit line in a memory cell region except a bit line contact and a charge storage electrode contact portion on a semiconductor substrate. Capacitive coupling problem can be completely solved by forming a ring preventing conductive film, and the bit line contact is self-aligned to the gate electrode by using the capacitor coupling preventing conductive film as an etch barrier layer when forming the bit line contact. By using the capacitor coupling preventing conductive layer and the barrier layer as an etch barrier layer when forming the charge preservation electrode contact, the charge storage electrode is formed in a self-aligned manner with respect to the gate electrode and the bit line, and the bit line and the charge preservation. By forming the first and second conductive lines in the portion where the electrode is present, It is a technology that improves the reliability of semiconductor devices by improving the degree of integration of conductor devices and preventing short circuits of conductive lines due to high steps.

The bit line shielded capacitor cell structure in which a conventional bit line is formed before the formation of a capacitor has a voltage of the bit line during cell operation by placing a plate electrode between the bit line and a metal line strapping the word line. When the voltage of the and word lines is changed, the plate electrode having the constant potential is used to reduce the capacitor coupling problem between the bit lines and the metal lines. However, the above structure still does not solve the capacitor coupling problem between the bit line and the word line because the capacitor coupling problem between the bit line and the word line gate electrode is still present.

In general, in the manufacture of semiconductor devices, the first and second conductive lines at the top of the source and drain lines are formed to form a contact for connecting the first or second conductive lines to the source / drain electrodes adjacent to the gate electrode. Since the gate electrode must be insulated from the electrode when it is connected to the electrode, certain design rules are followed in designing the gate electrode mask and the contact mask. In other words, the gap between the gate electrode mask and the contact mask may be generated during the mask fabrication and the photolithography process on the wafer. There must be a distance between misalignment tolerance and the thickness of the insulating material. Therefore, the area of the part to be connected becomes large by that amount.

Conventional self-aligned contact structure used to solve this problem is a sharp step in the vertical direction is formed is a possibility that a defect occurs during the photosensitive film development in the process of forming a conductive film, patterning after contact formation. In addition, when the conductive film is etched to form the conductive line, some of the conductive film formed on the sidewall portion of the step may be left without being etched to cause short circuit of the conductive line.

Therefore, the present invention provides a capacitor coupling by forming a capacitor coupling prevention film having a constant potential between the word line gate electrode and the insulating film between the bit line in the memory cell region except the bit line contact and the charge storage electrode contact portion on the semiconductor substrate. The ring problem can be completely solved, and the capacitor coupling prevention conductive film is used as an etch barrier layer when forming the bit line contact to form a bit line contact in a self-aligned form with respect to the gate electrode, and the capacitor coupling prevention conductive film and By using the etch barrier layer as an etch barrier layer when forming the charge storage electrode contact, the charge storage electrode is formed in a self-aligned manner with respect to the gate electrode and the bit line, and the first conductive line contact and the second conductivity on the semiconductor substrate. The gate electrode for the word line and the first electrode in the memory cell region except for the line contact portion By forming a first etch barrier layer between the insulating film between the conductive wires and using the first etch barrier layer as an etch barrier layer during the first conductive line contact, the first conductive line contact is formed in a self-aligned form with respect to the gate electrode, The second conductive line is formed by using the second etching barrier layer and the first etching barrier layer formed between the planarization layer stacked on the first conductive line and the second conductive line contact mask as the etching barrier layer. The purpose is to improve the degree of integration of the device by forming a contact in a self-aligned form with respect to the gate electrode and the first conductive line.

In order to achieve the above object, the present invention provides a device isolation insulating film on a semiconductor substrate, a gate electrode, a source and a drain electrode, and a process of forming a first insulating film for interlayer insulation purposes on the gate electrode; Forming a second insulating film on the entire upper structure, a conductive film for preventing coupling, and forming a planarization layer using a third insulating film, and forming a bit line contact mask by using a photosensitive film on the drain electrode; Using the bit line contact mask to etch the third insulating film and the anti-coupling conductive film, and anisotropically etch the lower second insulating film to form an insulating spacer on the sidewall of the gate electrode and to form a bit line contact hole; Forming an insulating film spacer on a sidewall on which the anti-coupling conductive film is formed, and being connected to the drain electrode. Forming a bit line, forming a planarization layer with a fourth insulating layer on the entire upper structure, and then forming an etch barrier layer having a predetermined thickness thereon; and using a photosensitive film on the etch barrier layer, using a charge storage electrode contact. Forming a mask, etching the etch barrier layer and the fourth insulating layer using the charge storage electrode contact mask to expose the bit lines, and etching the bit lines of the exposed portions; Growing an oxide film on the sidewalls of the bit line, etching the third insulating film using the etch barrier layer and the anti-coupling conductive film as an etch barrier layer, and the exposed couple using the second insulating film as an etch barrier layer. Etching the ring preventing conductive film, and anisotropically etching the second insulating film to form an insulating spacer on the sidewall of the gate electrode, and to maintain the charge storage electrode contact hole. And forming an insulating film spacer on the sidewall of the contact, and then forming a charge storage electrode connected to the contact hole.

A feature of the present invention for achieving the above object is to form a device isolation insulating film on the semiconductor substrate, and to form a gate electrode and a source and drain electrodes, but to form a first insulating film for interlayer insulation on the gate electrode And forming a second insulating film on the entire upper structure, forming a first etching barrier layer thereon, forming a planarization layer using a third insulating film, and using a photosensitive film on the drain electrode, using a first conductive line contact mask. Forming an insulating spacer on the sidewall of the gate electrode by etching the third insulating layer and the anti-coupling conductive layer using the first conductive line contact mask, and anisotropically etching the lower second insulating layer. Forming a conductive line contact hole, forming an insulating film spacer on a sidewall on which the coupling preventing conductive film is formed, and connecting to the drain electrode Forming a first conductive line, forming a planarization layer with a fourth insulating layer on the entire upper structure, and then forming a second etching barrier layer having a predetermined thickness thereon; and using a photoresist on the etch barrier layer. Forming a second conductive line contact mask, and etching the etch barrier layer and the fourth insulating layer using the second conductive line contact mask to expose the first conductive line, and to expose the first conductive line. Etching the conductive line, and growing an oxide film on the exposed sidewalls of the first conductive line and etching the second insulating layer using the second etching barrier layer and the first etching barrier layer as an etching barrier layer. And etching the exposed first etching barrier layer using the third insulating layer as an etch barrier layer, and anisotropically etching the second insulating layer to form insulating spacers on sidewalls of the gate electrode. Hall That generated, and then, forming an insulating spacer on a side wall of the contact is to include, a step of forming a second conductive line connected to the contact holes.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to 1G are sectional views showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 1A shows the device isolation insulating film 2 formed on the semiconductor substrate 1, the gate electrode 4, the source and the drain electrodes 6 ′ and 6 are formed, and the first insulating film formed on the gate electrode 4. It is sectional drawing which showed (5).

In FIG. 1B, the second insulating film 7 is deposited on the entire structure, and the anti-coupling conductive film 8 is formed thereon, and then the planarization layer is formed using the third insulating film 9 on the entire structure. A cross-sectional view showing the formation of the bit line contact mask 10 on the drain electrode 6 using the photoresist film, wherein the third insulating film 9 is sufficiently planarized to form a photolithography pattern for patterning the subsequently formed bit line. To facilitate the process, the bit line contact mask 10 formed on the drain electrode 3 extends to a predetermined portion of the gate electrode 4 adjacent to the drain electrode 6.

FIG. 1C is a cross-sectional view of the third insulating layer 9 completely etched using the bit line contact mask 10 as the etching preventing barrier layer 8 as an etch barrier layer.

In FIG. 1D, after the process of FIG. 1C, the anti-coupling conductive film 8 is etched using the second insulating film 7 as an etch barrier layer, and the lower second insulating film 7 is etched to etch the bit line contact hole 20. ), An insulating spacer is formed on the top and sidewalls of the gate electrode 4 for interlayer insulation, and a first insulating layer spacer 11 is formed on the sidewall of the bit line contact hole 20. 6) forming a bit line 12 connected to the upper layer and forming a planarization layer using the fourth insulating film 13 in the entire upper structure, and then, a photoresist film is formed on the etch barrier layer 14 having a predetermined thickness thereon. A cross-sectional view showing the formation of the charge storage electrode contact mask 15 by using a relatively isotropic etching characteristic in consideration of the step difference in the vertical direction formed by the gate electrode 4 when the coupling preventing conductive film 8 is etched. Wet etchant may be used, in which case contact Of the etching surface of the coupling preventing conductive film 8 it is formed by etching than cotton inside of the insulating layer 3, 2 (9,7). Alternatively, the anti-coupling conductive film 8 exposed to the insulating film spacer 11 instead of the first insulating film spacer 11 formed for the purpose of insulating the anti-coupling conductive film 8 and the bit line 12 may be oxidized. The fourth insulating layer 13 is sufficiently flattened to facilitate a photolithography process for patterning a later formed charge storage electrode, and the etch barrier layer 14 is subsequently processed using silicon not doped with impurities. When the oxide film is grown on the bit line side wall, less oxide film is grown on the etch barrier layer 14. In addition, the charge storage electrode contact mask 15 formed on the source electrode 6 'is extended to a predetermined portion of the gate electrode 4 and the bit line 12 adjacent to the source electrode 6'. do.

In FIG. 1E, the etch barrier layer 14 is etched using the charge storage electrode contact mask 15, and the fourth insulating layer 13 is etched to expose the bit line 12. After the bit line is etched, the cross-section of the charge preservation electrode contact mask 15 is removed.

FIG. 1F is a planarized third layer wherein an oxide film 16 is grown on the sidewalls of the bit line 12 of the exposed portion, and the etch barrier layer 14 and the coupling preventing conductive film 8 are used as an etch barrier layer. It is sectional drawing which shows the etching of the insulating film 9. As shown in FIG.

FIG. 1g illustrates that the anti-coupling conductive film 8 and the etching barrier layer 14 in the exposed portion are etched using the second insulating layer 7 as an etch barrier layer, and the lower second insulating layer 7 is etched. To form a charge preservation electrode contact hole 30, wherein an insulating film having a predetermined thickness for interlayer insulation remains on the gate electrode 4 and the sidewalls of the gate electrode 4, and then a second insulating film is formed on the side wall of the charge preservation electrode contact hole 30. A spacer 17 is formed to form a second insulating layer spacer 17 for interlayer insulation on the exposed sidewall of the anti-coupling conductive film 8, and a charge storage electrode 18 is formed on the charge storage electrode contact hole 30. It is sectional drawing which shows what was formed so that it might be connected. In this case, a wet etching solution having a relatively isotropic etching characteristic may be used in consideration of the step in the vertical direction formed by the gate electrode 4 when the coupling preventing conductive film 8 is etched. The etching surface of the anti-coupling conductive film 8 is formed inward of the etching surfaces of the third and second insulating films 9 and 7, and the bit line is damaged by the oxide film 16 formed on the sidewall of the bit line 12 in the contact. Can be prevented. In addition, the anti-coupling conductive film 8 exposed to the insulating film spacer 17 instead of the second insulating film spacer 17 formed for the purpose of insulating the anti-coupling conductive film 8 and the charge storage electrode 18 may be oxidized. In the case of forming the second insulating layer spacer 17, the source layer is etched together when the second insulating layer spacer 17 is formed without etching the lower second insulating layer 7 in the process of etching the etch barrier layer 8. The possibility of generation of a junction leakage current due to damage during etching in the electrode 6 'can be minimized.

A second embodiment of the present invention will be described in detail.

The present invention provides a method of forming a semiconductor device in which a gate electrode, a source and a drain electrode are formed on a semiconductor substrate, and a first conductive line is connected to the drain electrode and a second conductive line is connected to the source electrode. The first conductive line instead of the bit line, the second conductive line instead of the charge preservation electrode, the first etching barrier layer instead of the anti-coupling conductive film, and the second etching barrier layer instead of the etching barrier layer are formed. By forming the first conductive line and the second conductive line in the self-aligned type to solve the problems caused by the high step in the prior art to prevent the short circuit of the conductive line.

According to the present invention described above, the capacitor coupling problem can be solved, and the bit line contacts are formed in a self-aligned form with respect to the gate electrode, and the charge storage electrode contacts are formed in a self-aligned form with respect to the gate electrode and the bit line. By preventing the short circuit of the conductive line caused by the high step, the degree of integration of the semiconductor device is increased to improve the reliability of the device.

Claims (7)

Forming a device isolation insulating film over the semiconductor substrate, forming a gate electrode, a source and a drain electrode, forming a first insulating film for interlayer insulation on the gate, and forming a second insulating film over the entire upper structure; Forming a planarization layer using a third insulating layer and forming a bit line contact mask on the drain electrode by using a photoresist layer on the drain electrode, and forming the bit line contact mask on the drain electrode by using the bit line contact mask. Etching the insulating film and the anti-coupling conductive film and anisotropically etching the lower second insulating film to form an insulating spacer on the sidewall of the gate electrode and forming a bit line contact hole, and an insulating film spacer on the sidewall on which the anti-coupling conductive film is formed. Forming a bit line connected to the drain electrode and flattening the fourth insulating film over the entire upper structure. Forming a layer, and then forming an etch barrier layer having a predetermined thickness thereon; forming a charge storage electrode contact mask using a photosensitive film on the etch barrier layer; and forming the charge storage electrode contact mask. Etching the etch barrier layer and the fourth insulating layer to expose the bit lines, etching the bit lines of the exposed portions, growing an oxide film on sidewalls of the exposed bit lines, and etching the etch barriers. Etching the third insulating film using a layer and an anti-coupling conductive film as an etch barrier layer, etching the exposed anti-coupling conductive film using the second insulating film as an etch barrier layer, and the second insulating film. Anisotropic etching is performed to form insulating spacers on sidewalls of the gate electrode and to form charge storage electrode contact holes, and then to form insulating spacers on sidewalls of the contacts. That generated the following method for manufacturing a semiconductor device including a step of forming a charge preservation electrode connected to the contact holes. The method of claim 1, wherein the bit line contact mask is formed by overlapping a predetermined portion of the gate electrode. The method of claim 1, wherein the insulating film for preventing coupling is formed using silicon. The semiconductor device of claim 1, wherein when the anti-coupling conductive film is exposed to a sidewall, the insulating film is formed by oxidizing the anti-coupling conductive film instead of forming an insulating film spacer on the sidewall of the anti-coupling conductive film. Manufacturing method. The method of claim 1, wherein when forming the bit line contact hole and the charge storage electrode contact hole, the second insulating layer is etched without forming an insulating layer spacer on sidewalls of the two contact holes. Forming a device isolation insulating film over the semiconductor substrate, forming a gate electrode, a source and a drain electrode, forming a first insulating film for interlayer insulation on the gate electrode, forming a second insulating film over the entire upper structure, Forming a planarization layer using a third insulating layer and forming a first conductive line contact mask on the drain electrode by using a photoresist on the drain electrode, and forming the first conductive barrier layer on the first conductive line contact mask. Etching the third insulating film and the anti-coupling conductive film by using anisotropic method, and anisotropically etching the lower second insulating film to form insulating spacers on the sidewalls of the gate electrode and to form a first conductive line contact hole; Forming an insulating film spacer on the sidewall on which the prevention conductive film is formed, and forming a first conductive line connected to the drain electrode, and forming a fourth insulating film on the entire upper structure. Forming a planarization layer, and forming a second etch barrier layer having a predetermined thickness thereon; forming a second conductive line contact mask using a photosensitive film on the etch barrier layer; Exposing the first conductive line by etching the etch barrier layer and the fourth insulating layer using a second conductive line contact mask, and etching the first conductive line of the exposed portion; and a first of the exposed portion. Growing an oxide layer on a sidewall of the conductive line, etching the third insulating layer using the second etching barrier layer and the first etching barrier layer as an etching barrier layer, and exposing the exposed third layer using the second insulating layer as an etching barrier layer. Etching the first etching barrier layer, anisotropically etching the second insulating layer, forming an insulating spacer on the sidewall of the gate electrode, forming a second conductive line contact hole, and then forming an insulating layer spacer on the sidewall of the contact. That generated the following method for manufacturing a semiconductor device including a step of forming a second conductive line connected to the contact holes. The semiconductor device of claim 6, wherein when forming the first conductive line contact hole and the second conductive line contact hole, the insulating layer spacer is formed on the sidewalls of the two contact holes without etching the second insulating layer. Manufacturing method.