KR100228344B1 - Method of forming storage electrode of semiconductor device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Semiconductor device manufacturing method.

2. The technical problem to be solved by the invention

It is intended to provide a method of forming a charge storage electrode for maximizing the effective surface area of a capacitor in a limited area while eliminating the stepped fail.

3. Summary of Solution to Invention

A device isolation film is formed on the upper substrate having a predetermined thickness of the lower substrate, the buried insulating film, and the upper substrate, a source electrode and a drain region of the gate electrode and the first conductivity type are formed, and then an interlayer insulating film is formed over the entire structure. A trench is formed by selectively etching the interlayer insulating film, the upper substrate, and the buried insulating film having a predetermined thickness using a charge storage electrode mask, and a portion of the source / drain regions of the adjacent portions are etched together. To provide a method for forming a charge storage electrode, characterized in that the remaining in the form of a spacer on the trench sidewalls by the deposition and surface etching process.

4. Important uses of the invention

Used in the process of forming the charge storage electrode in the semiconductor device manufacturing process.

Description

Method for forming charge storage electrode of semiconductor device

The present invention relates to a method of forming a charge storage electrode for securing the capacity of a capacitor during a semiconductor device manufacturing process.

In general, the area in which charge storage electrodes are formed per unit cell is decreasing as general-purpose semiconductor devices such as DRAMs are highly integrated, thereby maximizing the surface area by forming the charge storage electrodes in a three-dimensional shape. Technology to secure the required charge storage capacity per cell is currently under a lot of research and development.

1A to 1C are cross-sectional views of a charge storage electrode forming process of a semiconductor device according to the prior art.

First, FIG. 1A shows the upper substrate 3 having a predetermined thickness of a silicon on insulator (SOI) substrate formed of a stacked structure of a lower substrate 1, an buried oxide film 2, and an upper substrate 3. Thermal oxidation by a silicon) process to form an isolation film 4 as an inter-element insulating film, and form a gate oxide film 5 and a gate electrode 6, and then source / drain regions 7 are formed. After the formation, the interlayer insulating film 8 is formed on the entire structure.

In this case, the device isolation film 4 for inter-element insulation is formed by oxidizing the upper substrate 3 having a predetermined thickness, so as not to reach the interface of the buried oxide film 2 under the upper substrate 3.

This is because the device isolation film 4 does not reach the interface of the buried oxide film 2 at the bottom, thereby securing the substrate voltage as in the conventional bulk silicon substrate, thereby ensuring stability of the device.

On the other hand, the device isolation film 4 is formed by forming a trench by etching the upper substrate 3 of a predetermined thickness by an etching process using a device separation mask, and then depositing an oxide film for device isolation on the entire structure, the front The device isolation layer 4 may be formed by etching back and leaving the oxide layer for device isolation inside the trench.

Subsequently, in FIG. 1B, the interlayer insulating layer 8 is selectively etched using a mask for forming a charge storage electrode contact hole to form a charge storage electrode contact hole through which the upper substrate 3 of a predetermined portion is exposed. After the first polysilicon film 9 for charge storage electrodes and the sacrificial oxide film 10 are formed, the sacrificial oxide film 10 and the first polysilicon for charge storage electrodes are formed by an etching process using a mask for forming an electron storage electrode. After the etching of the film 9, a second polysilicon film for the charge storage electrode is formed on the entire structure, and the entire surface is etched without a mask to form the first polysilicon film 9 and the sacrificial oxide film 10 for the charge storage electrode. The second polysilicon layer spacer 11 for charge storage electrodes is formed on the sidewalls to form cylindrical charge storage electrodes 9 and 11.

Finally, FIG. 1C shows that the dielectric film 12 and the polysilicon film 13 for the plate electrode are formed on the entire structure after the sacrificial oxide film 10 is wet removed.

By forming the cylindrical charge storage electrode according to the prior art as described above, by increasing the height of the cylinder in a limited area to increase the effective surface area of the charge storage electrode, the capacity of the charge storage electrode can be increased, but the cylindrical charge storage electrode Since the conductive film forming process has to be performed twice in order to form, the overall device fabrication process is complicated, and by manufacturing the cylinder to increase the effective surface area, there is a problem such that the step height becomes larger than other regions by the height of the cylinder. .

In order to solve the above problems, the present invention removes the fail due to the step and at the same time, the charge storage electrode of the semiconductor device for increasing the capacity of the charge storage electrode by maximizing the effective surface area of the capacitor in a limited area in a relatively simple process. The purpose is to provide a formation method.

1A to 1C are cross-sectional views of a charge storage electrode forming process of a semiconductor device according to the prior art;

2A and 2B are cross-sectional views of a process of forming a charge storage electrode of a semiconductor device according to an embodiment of the present invention;

3A to 3D are cross-sectional views of a charge storage electrode forming process of a semiconductor device according to another embodiment of the present invention;

4A to 4D are cross-sectional views of a charge storage electrode forming process of a semiconductor device according to still another embodiment of the present invention;

5A and 5B are cross-sectional views showing variations in the shape of charge storage electrodes due to misalignment occurring during the photolithography process of FIGS. 3C and 4C.

* Explanation of symbols for main parts of the drawings

21, 41, 61: lower substrate 22, 42, 62: buried oxide film

23, 43, 63: upper substrate 24, 44, 64: antioxidant film

25, 45, 65: gate oxide films 26, 46, 66: gate electrode

27, 47, 67: source / drain regions 28, 48, 68: interlayer insulating film

29, 49, 69: polysilicon film for charge storage electrode

30, 50, 70: dielectric film

31, 51, 71: polysilicon film for plate electrodes

60, 80: photoresist pattern

In order to achieve the above object, the present invention comprises the steps of forming an isolation layer on the upper substrate of a predetermined thickness of the semiconductor substrate formed of the lower substrate, the buried insulating film, the upper substrate; Sequentially forming a source / drain region having a gate electrode and a first conductivity type impurity on a semiconductor substrate at a predetermined portion; Forming an interlayer insulating film over the entire structure; Forming a trench by selectively etching the interlayer insulating film, the upper substrate, and the buried insulating film having a predetermined thickness using a mask for forming a charge storage electrode, and etching a portion of the source / drain region in an adjacent region together; And forming a conductive film for the charge storage electrode on the entire structure, and etching the entire surface without a mask to remain on the trench sidewalls in the form of a spacer.

In addition, the present invention includes forming an isolation layer on the upper substrate of a predetermined thickness of the semiconductor substrate formed of the lower substrate, the buried insulating film, the upper substrate; Sequentially forming a source / drain region having a gate electrode and a first conductivity type impurity on a semiconductor substrate at a predetermined portion; Forming an interlayer insulating film on the entire structure; Forming a trench by selectively etching the interlayer insulating film, the upper substrate, and the buried insulating film having a predetermined thickness using a mask for forming a charge storage electrode, and etching a portion of the source / drain region in an adjacent region together; And forming a conductive film for the charge storage electrode on the entire structure, and patterning the conductive film for the charge storage electrode by an etching process using a mask for forming the charge storage electrode.

In addition, the present invention includes forming an isolation layer on the upper substrate of a predetermined thickness of the semiconductor substrate formed of the lower substrate, the buried insulating film, the upper substrate; Sequentially forming a source / drain region having a gate electrode and a first conductivity type impurity on a semiconductor substrate at a predetermined portion; Forming an interlayer insulating film on the entire structure; Forming a trench by selectively etching the interlayer insulating film, the upper substrate, and the buried insulating film having a predetermined thickness using a mask for forming a charge storage electrode, and etching a portion of the source / drain region in an adjacent region together; And forming a conductive film for the charge storage electrode on the entire structure, and patterning the conductive film for the charge storage electrode by an etching process using a mask larger than a mask for forming the charge storage electrode.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A and 2B are cross-sectional views of a charge storage electrode forming process of a semiconductor device according to an embodiment of the present invention.

First, FIG. 2A illustrates thermal oxidation of the upper substrate 23 having a predetermined thickness of a silicon on insulator (SOI) substrate formed of a stacked structure of a lower substrate 21, an buried oxide film 22, and an upper substrate 23. After forming the isolation film 4 as an insulating film, forming the gate oxide film 25 and the gate electrode 26, source / drain regions 27 are formed, and then an interlayer insulating film over the entire structure. (28) is shown.

In this case, the device isolation layer 24 for inter-element insulation is formed by oxidizing the upper substrate 23 having a predetermined thickness, so as not to reach the interface of the buried oxide film 22 under the upper substrate 23.

This is because the device isolation film 24 does not reach the interface of the buried oxide film 22 at the bottom, thereby securing the substrate voltage as in the conventional bulk silicon substrate, thereby ensuring stability of the device.

In the meantime, the device isolation layer 24 forms a trench by etching the upper substrate 23 having a predetermined thickness by an etching process using a device isolation mask, and then deposits an oxide film for device isolation on the entire structure. The device isolation layer 24 may be formed by etching back to leave the oxide layer for device isolation in the trench.

Next, in FIG. 2B, a trench is formed by selectively etching the interlayer insulating layer 28, the upper substrate 23, and the buried oxide layer 22 having a predetermined thickness using a mask for forming a charge storage electrode, wherein the source / drain regions of a predetermined portion are formed. (27) to be etched together so as to be electrically connected to the polysilicon film 29 for the charge storage electrode to be formed later, and then the polysilicon film 29 for the charge storage electrode having a thickness of about 30 mW to 1000 m over the entire structure. ), And then etched the entire surface without a mask to remain on the sidewalls of the upper substrate 23, the buried oxide film 22, and the interlayer insulating film 28 in the form of a spacer, and then the dielectric film 30 and the plate electrode on the entire structure. The thing which formed the polysilicon film 31 for is shown.

In this case, an amorphous silicon film and a metal film may be used instead of the polysilicon film 29 for the charge storage electrode, and a film in which at least two or more films of the polysilicon film, the amorphous silicon film, and the metal film are stacked may be used.

In addition, any one of the polysilicon film 29, the amorphous silicon film and the metal film for the charge storage electrode, or at least two or more films of the polysilicon film, the amorphous silicon film and the metal film is laminated on the hemispherical polysilicon A film can be formed to maximize the effective surface area.

In the etching process for forming the trench, the buried oxide film 22 having a thickness of about 20 kV to 3000 kV or more is left to insulate the polysilicon layer 29 for the charge storage electrode and the lower substrate 21 to be formed later. .

In addition, the mask used as an etch barrier during the etching process for forming the trench is advantageously manufactured and used as large as possible without causing deterioration of the device instead of the mask for forming the charge storage electrode. When the etching process for forming the trench is performed using the mask fabricated as large as described above, not only the source / drain region 27 of the predetermined portion but also the device isolation layer 24 of the predetermined portion is etched together.

In addition, a predetermined portion of the polysilicon layer 29 for charge storage electrode 29 and the source / drain region 27 and the upper substrate 23 may not be shorted before the process of forming the polysilicon layer 29 for charge storage electrode. An impurity doping process may be performed on the upper substrate 23 of the upper substrate 23 or dopants may be diffused from the polysilicon film for the charge storage electrode so as to be in an ohmic contact with the source / drain region. Rectifying contact with the upper substrate.

The present invention made as described above can shorten the process by using a single conductive film to form the charge storage electrode of the cylindrical structure and can eliminate the generation of steps by the height of the cylinder according to the prior art, so that subsequent processes are easy. .

In addition, when the sacrificial oxide film used in the cylindrical charge storage electrode forming process according to the prior art is removed, it is possible to prevent the interlayer insulating layer under the charge storage electrode from being removed together, and when forming the second polysilicon film for the charge storage electrode for spacer formation. It may be prevented from being connected to the first polysilicon film for the charge storage electrode or peeling off during the process.

3A to 3D are cross-sectional views of a charge storage electrode forming process of a semiconductor device according to another embodiment of the present invention.

First, FIG. 3A thermally oxidizes the upper substrate 43 having a predetermined thickness of a silicon on insulator (SOI) substrate formed in a stacked structure of a lower substrate 41 / buried oxide film 42 / upper substrate 43. After forming the device isolation film 44 as an insulating film, forming the gate oxide film 45 and the gate electrode 46, forming a source / drain region 47, and then forming an interlayer insulating film over the entire structure. (48) is shown.

In this case, the device isolation layer 44 for inter-element insulation is formed by oxidizing the upper substrate 43 having a predetermined thickness, so as not to reach the interface of the buried oxide film 42 under the upper substrate 43.

This is because the device isolation film 44 does not reach the interface of the buried oxide film 42 at the bottom, thereby securing the substrate voltage as in the conventional bulk silicon substrate, thereby ensuring stability of the device.

In the meantime, the device isolation layer 44 forms a trench by etching the upper substrate 43 having a predetermined thickness by an etching process using a device isolation mask, and then deposits an oxide layer for device isolation on the entire structure. The device isolation layer 44 may be formed by etching back to leave the oxide layer for device isolation in the trench.

3B, a trench is formed by selectively etching the interlayer insulating film 48, the upper substrate 43, and the buried oxide film 42 having a predetermined thickness using a mask for forming a charge storage electrode. After the drain region 47 is etched together to be electrically connected to the polysilicon film 49 for charge storage electrodes to be formed later, the polysilicon film for charge storage electrodes having a thickness of about 30 kV to 1000 kW over the entire structure is formed. (49) is shown.

In this case, an amorphous silicon film and a metal film may be used instead of the polysilicon film 49 for the charge storage electrode, and a film in which at least two or more films of the polysilicon film, the amorphous silicon film, and the metal film are stacked may be used.

The polysilicon film 49, the amorphous silicon film, and the metal film for the charge storage electrode, or at least two or more films of the polysilicon film, the amorphous silicon film, and the metal film are stacked on the hemispherical polysilicon. A film can be formed to maximize the effective surface area.

Meanwhile, in the etching process for forming the trench, the buried oxide film 42 having a thickness of about 20 GPa to 3000 GPa is left to insulate the polysilicon layer 49 for the charge storage electrode to be formed later from the lower substrate 41. .

In addition, the mask used as an etch barrier during the etching process for forming the trench is advantageously manufactured and used as large as possible without causing deterioration of the device instead of the mask for forming the charge storage electrode. When the etching process for forming the trench is performed by using the mask fabricated as large as described above, not only the source / drain region 47 of the predetermined portion but also the device isolation layer 44 of the predetermined portion is etched together.

In addition, a predetermined portion of the polysilicon film 49 for charge storage electrode 49 and the source / drain region 47 and the upper substrate 43 may not be shorted before the process of forming the polysilicon film 449 for charge storage electrode. An impurity doping process may be performed on the upper substrate 43 of the upper substrate 43 or dopants may be diffused from the polysilicon film for the charge storage electrode so as to be doped, thereby making ohmic contact with the source / drain region. Rectifying contact with the upper substrate.

Subsequently, in FIG. 3C, a photoresist is applied over the entire structure, a photoresist pattern 60 is formed by a photolithography process using a mask for forming a charge storage electrode, and then the photoresist pattern 60 is etched. The polysilicon film 49 for the charge storage electrode is etched with a mask to form a charge storage electrode pattern.

Finally, FIG. 3D shows that the dielectric film 50 and the polysilicon film 51 for the plate electrode are formed on the entire structure after the photoresist pattern 60 is removed.

The present invention as described above can achieve the same effect in the above embodiment, it is possible to enlarge the effective surface area of the charge storage electrode as much as the area of the trench bottom surface than in the above embodiment.

4A to 4D are cross-sectional views of a charge storage electrode forming process of a semiconductor device according to another embodiment of the present invention.

First, FIG. 4A illustrates thermally oxidizing the upper substrate 63 of a predetermined thickness of a silicon on insulator (SOI) substrate formed of a stacked structure of a lower substrate 61 / buried oxide film 62 / upper substrate 63. After forming an isolation layer 64 as an insulating film, forming a gate oxide film 65 and a gate electrode 66, forming a source / drain region 67, and then forming an interlayer insulating film over the entire structure. (68) is shown.

At this time, the device isolation layer 64 for inter-element insulation is formed by oxidizing the upper substrate 63 of a predetermined thickness, so as not to reach the interface of the buried oxide film 62 under the upper substrate 63.

Since the device isolation layer 64 does not reach the interface of the buried oxide layer 62 at the bottom, the device isolation layer 64 can secure the substrate voltage as in the conventional bulk silicon substrate, thereby ensuring stability of the device.

In the meantime, the device isolation layer 64 forms a trench by etching the upper substrate 63 having a predetermined thickness by an etching process using a device isolation mask, and then deposits an oxide layer for device isolation on the entire structure. The device isolation layer 64 may be formed by etching back and leaving the oxide layer for device isolation inside the trench.

Subsequently, in FIG. 4B, a trench is formed by selectively etching the interlayer insulating film 68, the upper substrate 63, and the buried oxide film 62 having a predetermined thickness using a mask for forming a charge storage electrode. After the drain region 67 is etched together to be electrically connected to the polysilicon film 69 for the charge storage electrode to be formed later, the polysilicon film for the charge storage electrode having a thickness of about 30 mW to 1000 mW over the entire structure. (69) is shown.

In this case, an amorphous silicon film and a metal film may be used instead of the polysilicon film 69 for the charge storage electrode, and a film in which at least two or more films of the polysilicon film, the amorphous silicon film, and the metal film are stacked may be used.

In addition, any one of the polysilicon film 69, the amorphous silicon film and the metal film for the charge storage electrode, or at least two or more films of the polysilicon film, the amorphous silicon film and the metal film is laminated on the hemispherical polysilicon A film can be formed to maximize the effective surface area.

Meanwhile, in the etching process for forming the trench, the buried oxide film 62 having a thickness of about 20 GPa to 3000 GPa is left to insulate the polysilicon film 69 for the charge storage electrode to be formed later from the lower substrate 61. .

In addition, the mask used as an etch barrier during the etching process for forming the trench is advantageously manufactured and used as large as possible without causing deterioration of the device instead of the mask for forming the charge storage electrode. When the etching process for forming the trench is performed using the mask fabricated as large as described above, not only the source / drain region 67 of the predetermined portion but also the device isolation layer 64 of the predetermined portion is etched together.

In addition, a predetermined portion of the polysilicon film 69 for the charge storage electrode 69 and the source / drain region 67 and the upper substrate 63 may not be shorted before the process of forming the polysilicon film 69 for the charge storage electrode. An impurity doping process is performed on the upper substrate 63 of the upper substrate 63, or impurities are diffused from the polysilicon film for charge storage electrode so as to be doped, thereby making ohmic contact with the source / drain region. Rectifying contact with the upper substrate.

Subsequently, FIG. 4C shows a photoresist by applying a photoresist over the entire structure and using a photolithography process using a mask fabricated by a predetermined size larger than a mask for forming a charge storage electrode within a range that does not affect adjacent devices. After the pattern 80 is formed, the polysilicon film 69 for the charge storage electrode is etched using the photoresist pattern 80 as an etch mask to form a charge storage electrode pattern.

Finally, FIG. 4D shows that the dielectric layer 70 and the polysilicon film 71 for the plate electrode are formed on the entire structure after the photoresist pattern 80 is removed.

The present invention made as described above can achieve the same effect as in the embodiment and the other embodiment, the charge of the process margin of the mask fabricated by a predetermined size larger than the charge storage electrode mask for forming the charge storage electrode pattern The effective surface area of the storage electrode can be enlarged.

5A and 5B are cross-sectional views showing variations of the shape of the charge storage electrode according to misalignment occurring during the photolithography process of FIGS. 3C and 4C of another embodiment and another embodiment of the present invention. The polysilicon layers 49 and 69 for the charge storage electrodes are formed by using the photoresist patterns 60a and 80a deformed due to the misalignment generated during the photolithography process using the respective masks for forming the charge storage electrode patterns as etch masks. In the case of etching, a phenomenon in which the polysilicon layers 49 and 69 for charge storage electrodes 49 and 69 at the bottom of the charge storage electrode contact hole are disconnected is shown.

At this time, even if a short circuit between the charge storage electrode patterns occurs due to the photoresist patterns 60a and 80a deformed as described above, each charge storage electrode pattern is formed through the source / drain regions 47 and 67 along the trenched side. Are interconnected.

In addition, when the degree of misalignment is not larger than the distance between the charge storage electrode patterns, a short circuit phenomenon between adjacent charge storage electrode patterns does not occur.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

According to the present invention formed as described above, by forming a trench by etching a semiconductor substrate having a predetermined depth, and forming a cylindrical charge storage electrode on the sidewalls of the trench, the height difference of the cylinder can be eliminated as compared with the conventional cylindrical charge storage electrode. Subsequent processes can be easily executed, and the process can be simplified by using the conductive film for the charge storage electrode for forming the cylindrical charge storage electrode only once, so that the cost reduction and the yield improvement can be expected.

Claims (27)

Forming an isolation layer on the upper substrate having a predetermined thickness of the semiconductor substrate formed of the lower substrate, the buried insulating film, and the upper substrate; Sequentially forming a source / drain region having a gate electrode and a first conductivity type impurity on a semiconductor substrate at a predetermined portion; Forming an interlayer insulating film on the entire structure; Forming a trench by selectively etching the interlayer insulating film, the upper substrate, and the buried insulating film having a predetermined thickness using a mask for forming a charge storage electrode, and etching a portion of the source / drain region in an adjacent region together; And And forming a conductive film for the charge storage electrode on the entire structure, and etching the entire surface without a mask and remaining on the sidewalls of the trench in the form of a spacer. The method of claim 1, And implanting impurities of a first conductivity type into the upper substrate having a predetermined depth after forming the trench. The method of claim 1, Forming a conductive film for the charge storage electrode on the entire structure, and etching the entire surface without a mask to remain in the form of a spacer on the sidewall of the trench, followed by heat treatment to diffuse impurities of the conductive film for the charge storage electrode to the upper substrate of a predetermined portion And storing the charge storage electrode of the semiconductor device. The method of claim 1, And a buried insulating film having a thickness of about 20 kV to about 3000 kV in the etching process for forming the trench. The method of claim 1, And the conductive film for the charge storage electrode is any one of a polysilicon film, an amorphous silicon film or a metal film. The method of claim 1, And the conductive film for the charge storage electrode is a laminated structure in which at least two or more of a polysilicon film, an amorphous silicon film, or a metal film are sequentially formed. The method of claim 5, The charge storage electrode conductive film is a method for forming a charge storage electrode of a semiconductor device, characterized in that further comprising a hemispherical polysilicon film. The method of claim 6, The charge storage electrode conductive film is a method for forming a charge storage electrode of a semiconductor device, characterized in that further comprising a hemispherical polysilicon film. The method according to any one of claims 1 to 8, And wherein the conductive film for charge storage electrode is formed to a thickness of about 30 mW to about 1000 mW. Forming an isolation layer on the upper substrate having a predetermined thickness of the semiconductor substrate formed of the lower substrate, the buried insulating film, and the upper substrate; Sequentially forming a source / drain region having a gate electrode and a first conductivity type impurity on a semiconductor substrate at a predetermined portion; Forming an interlayer insulating film on the entire structure; Forming a trench by selectively etching the interlayer insulating film, the upper substrate, and the buried insulating film having a predetermined thickness using a mask for forming a charge storage electrode, and etching a portion of the source / drain region in an adjacent region together; And And forming a conductive film for the charge storage electrode on the entire structure, and patterning the conductive film for the charge storage electrode by an etching process using a mask for forming the charge storage electrode. The method of claim 10, And implanting impurities of a first conductivity type into the upper substrate having a predetermined depth after forming the trench. The method of claim 10, Forming a conductive film for the charge storage electrode on the entire structure, and patterning the conductive film for the charge storage electrode by an etching process using a charge storage electrode mask, followed by heat treatment to remove impurities from the conductive film for the charge storage electrode. The method of claim 1, further comprising diffusing the upper substrate. The method of claim 10, And a buried insulating film having a thickness of about 20 kV to about 3000 kV in the etching process for forming the trench. The method of claim 10, And the conductive film for the charge storage electrode is any one of a polysilicon film, an amorphous silicon film or a metal film. The method of claim 10, And the conductive film for the charge storage electrode is a laminated structure in which at least two or more of a polysilicon film, an amorphous silicon film, or a metal film are sequentially formed. The method of claim 14, The charge storage electrode conductive film is a method for forming a charge storage electrode of a semiconductor device, characterized in that further comprising a hemispherical polysilicon film. The method of claim 15, The charge storage electrode conductive film is a method for forming a charge storage electrode of a semiconductor device, characterized in that further comprising a hemispherical polysilicon film. The method according to any one of claims 10 to 17, And wherein the conductive film for charge storage electrode is formed to a thickness of about 30 mW to about 1000 mW. Forming an isolation layer on the upper substrate having a predetermined thickness of the semiconductor substrate formed of the lower substrate, the buried insulating film, and the upper substrate; Sequentially forming a source / drain region having a gate electrode and a first conductivity type impurity on a semiconductor substrate at a predetermined portion; Forming an interlayer insulating film on the entire structure; Forming a trench by selectively etching the interlayer insulating film, the upper substrate, and the buried insulating film having a predetermined thickness using a mask for forming a charge storage electrode, and etching a portion of the source / drain region in an adjacent region together; And Forming a conductive film for the charge storage electrode on the entire structure, and patterning the conductive film for the charge storage electrode by an etching process using a mask larger than a mask for forming the charge storage electrode. Electrode formation method. The method of claim 19, And implanting impurities of a first conductivity type into the upper substrate having a predetermined depth after forming the trench. The method of claim 19, Forming a conductive film for the charge storage electrode on the entire structure, and patterning the conductive film for the charge storage electrode by an etching process using a mask having a predetermined size larger than the charge storage electrode mask, followed by heat treatment to conduct the charge storage electrode. And diffusing an impurity of a film onto the upper substrate at a predetermined portion. The method of claim 19, And a buried insulating film having a thickness of about 20 kV to about 3000 kV in the etching process for forming the trench. The method of claim 19, And the conductive film for the charge storage electrode is any one of a polysilicon film, an amorphous silicon film or a metal film. The method of claim 19, And the conductive film for the charge storage electrode is a laminated structure in which at least two or more of a polysilicon film, an amorphous silicon film, or a metal film are sequentially formed. The method of claim 23, wherein The charge storage electrode conductive film is a method for forming a charge storage electrode of a semiconductor device, characterized in that further comprising a hemispherical polysilicon film. The method of claim 24, The charge storage electrode conductive film is a method for forming a charge storage electrode of a semiconductor device, characterized in that further comprising a hemispherical polysilicon film. The method according to any one of claims 19 to 26, And wherein the conductive film for charge storage electrode is formed to a thickness of about 30 mW to about 1000 mW.

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