KR20080088098A - Method of manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent the collapse of a bit line by etching a part of a bit line material and then gap-filling a gap between the etched bit line materials with a first separation dielectric. A bit line material is formed on a semiconductor substrate(210). A first mask pattern is formed on the bit line material to cover two adjacent bit line forming regions and a region therebetween. The bit line material is etched. The first mask pattern is removed. A first spacer(S1) is formed on both sidewalls of the etched bit line material. A bit line first isolation dielectric(291) is gap-filled between the bit line materials where the first spacer is formed. A second mask pattern is formed on the bit line material where the bit line first isolation dielectric and the first spacer are formed. The first mask pattern covers the two adjacent bit line forming regions and the bit line first separation dielectric. The bit line material is etched to form bit lines having the first spacers at both sides of the bit line first isolation dielectric. The second mask pattern is removed. A second spacer(S2) is formed on both sidewalls of the two adjacent bit lines. A bit line second isolation dielectric(292) is gap-filled between the bit lines where the second spacer is formed.

Description

Method of manufacturing semiconductor device

1 is a cross-sectional view showing the collapse of the bit line according to the prior art.

2A to 2G are cross-sectional views of processes for explaining a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

210: semiconductor substrate 220: device isolation film

230: first insulating film 240: landing plug contact

250: second insulating film 261: Ti film

262: TiN film 269: bit line barrier film

279: bit line conductive film 289: bit line hard mask film

291: bit line first isolation insulating film 292: bit line second isolation insulating film

M1: first mask pattern M2: second mask pattern

S1: first spacer S2: second spacer

B / L: Bitline

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can prevent the collapse of the bit line.

BACKGROUND ART With the high integration of semiconductor devices, a technology for using a low resistance, high melting point metal such as tungsten (W) as a material of a bit line is being provided for a bit line providing an input / output path of data in the device.

Since the high melting point metal, such as tungsten, has a relatively low resistivity compared to the conventional bit line material tungsten silicide (WSix), the bit line of the high melting point metal material may satisfy the operation speed required for the highly integrated device. .

On the other hand, the semiconductor device is to implement a high-performance and high-density device as the technology advances to implement a smooth electrical signal transmission, for this purpose it is inevitable to increase the number of bit lines that serves as an electrical signal transmission.

As such, as the size of the device becomes smaller, the height of the bit lines increases to form a larger number of bit lines, and the gap between the bit lines becomes narrower, as shown in FIG. 1, the aspect ratio of the bit lines. Due to the increase, collapse occurs when the bit line is formed, which causes shorting with neighboring bit lines.

As the size of the semiconductor device gradually decreases, the aspect ratio of the bit line is further increased. Therefore, in order to manufacture a high-performance device, the collapse of the bit line must be suppressed.

In FIG. 1, reference numeral 110 denotes a semiconductor substrate, 120 denotes an isolation layer, 130 denotes a first insulating layer, 140 denotes a landing plug contact, and 150 denotes a second insulating layer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing a short phenomenon between bit lines by suppressing the collapse of bit lines when forming a bit line having a high aspect ratio.

In order to achieve the above object, the present invention, the step of forming a bit line material on a semiconductor substrate on which the base layer is formed; Forming two adjacent bit line forming regions on the bit line material and a first mask pattern covering an area therebetween; Etching the bitline material; Removing the first mask pattern; Forming first spacers on both sidewalls of the etched bitline material; Filling a bit line first isolation insulating layer between the bit line materials having the first spacer formed thereon; Forming a second mask pattern on the bit line material on which the bit line first isolation insulating layer and the first spacer are formed and covering the two bit line forming regions adjacent to each other and the bit line first isolation insulating layer formed therebetween; Etching the bit line material to form bit lines having first spacers facing each other on both sides of the bit line first isolation insulating layer; Removing the second mask pattern; Forming a second spacer on opposite sides of the two adjacent bit lines; And embedding a bit line second isolation insulating layer between the bit lines on which the second spacers are formed.

Here, the bit line material may be formed of a stacked layer of a bit line barrier layer, a bit line conductive layer, and a bit line hard mask layer.

The bit line barrier film includes a stacked film of a Ti film and a TiN film.

The bit line conductive film includes a tungsten film.

The bit line hard mask layer may include a nitride layer-based layer.

The first spacer and the second spacer includes a nitride film-based film.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be described by etching a bit line material formed in two adjacent bit line forming regions and an area outside the region between them by a first mask process, and then forming a first bit line between the etched bit line materials. A separation insulating film is buried.

Then, the bit line material etched by the second mask process is etched to form two bit lines adjacent to both sides of the bit line first isolation insulating film, and then between the bit lines where the bit line first isolation insulating film is not buried. The bit line second isolation insulating layer is buried.

As described above, a portion of the bit line material is primarily etched, and then the bit line first isolation insulating layer is buried therebetween, thereby biting the bit line material during the bit line material etching. It is possible to prevent the line from falling down.

Therefore, the present invention can suppress the phenomenon that the short occurs due to the electrical short caused by falling to the neighboring bit line when forming the bit line having a large aspect ratio, and as a result, it becomes possible to form a reliable bit line.

2A to 2G are cross-sectional views taken along the line AA ′ of FIG. 3, and a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to this.

Referring to FIG. 2A, a transistor including a gate insulating layer, a gate conductive layer, and a gate hard mask layer in a gate formation region on a semiconductor substrate 210 having an isolation layer 220 defining an active region is formed of a transistor and a junction region. (Not shown) is formed.

2A is a cross-sectional view taken along the line AA ′ of FIG. 3, and thus the gate is not shown.

Thereafter, a first insulating layer 230 including a contact hole exposing a landing plug contact formation region is formed on the entire surface of the substrate including the transistor, and then a landing plug contact (LPC) is formed in the contact hole. 240).

Next, a second insulating layer 250 is formed on the entire surface of the substrate including the landing plug contact 240.

Subsequently, a bit line barrier layer 269, a bit line conductive layer 279, and a bit line hard mask layer 289 are formed on the second insulating layer 250 using a bit line material.

In this case, the bit line barrier film 269 is formed of a stacked film of a Ti film 261 and a TiN film 262, and the bit line conductive film 279 is formed of a tungsten-based film, and the bit line hard The mask film 289 is formed of a nitride film-based film.

Referring to FIG. 2B, two bit line forming regions adjacent to the bit line hard mask layer 289 and a first mask pattern M1 covering an area therebetween are formed.

Next, the bit line materials 269, 279, and 289 that are not covered by the first mask pattern are etched using the first mask pattern M1 as an etching mask until the second insulating layer 250 is exposed.

Referring to FIG. 2C, after the nitride layer for the spacer is deposited on the entire surface of the substrate including the etched bit line materials 269, 279, and 289 while the first mask pattern is removed, the nitride layer for the spacer is etched back. The first spacer S1 is formed on both sidewalls of the bit line materials 269, 279 and 289.

Referring to FIG. 2D, after the bit line first isolation insulating layer 291 is deposited to fill the bit line materials 269, 279 and 289 on which the first spacer S1 is formed, the bit line hard mask layer 250 may be formed. The bit line first isolation insulating layer 291 is etched until the bit line is exposed.

Referring to FIG. 2E, two bit line forming regions adjacent to the bit line hard mask layer 289 on which the bit line first isolation insulating layer 291 and the first spacer S1 are formed and the bit lines formed therebetween are shown. A second mask pattern M2 covering the first isolation insulating layer 291 is formed.

Then, using the second mask pattern M2 as an etching mask, the bit line materials 269, 279, and 289 not covered by the second mask pattern are etched to face both sides of the bit line first isolation insulating layer 291. Bit lines B / L having the first spacer S1 having the shape are formed.

As such, when the bit line materials 269, 279, and 289 are primarily etched using the first mask pattern M1, the bit line first isolation insulating layer 291 is formed between the etched bit line materials. The bit line first isolation insulating layer 291 may prevent the bit line B / L from falling down during the etching process for forming the complete bit line.

In detail, since the bit line first isolation insulating film 291 buried between two adjacent bit line forming regions serves as a support for the bit line material, the bit line falls to a neighboring bit line when forming a bit line having a high aspect ratio. It is possible to prevent the phenomenon that occurs.

Referring to FIG. 2F, after the spacer nitride film is deposited on the entire surface of the substrate including the bit line B / L in a state where the second mask pattern is removed, the spacer nitride film is etched back. Accordingly, a second spacer S2 is formed on both sidewalls of two bit lines B / L adjacent to both sides of the bit line first isolation insulating layer 291.

Referring to FIG. 2G, after the bit line second isolation insulating layer 292 is deposited on the entire surface of the substrate to fill the gap between the bit lines B / L on which the second spacer S2 is formed, the bit line hard mask. The bit line second isolation insulating film bit line second isolation insulation film bit line second isolation insulation films B / L are completely separated until the film 289 is exposed.

Thereafter, although not shown, a semiconductor device according to an embodiment of the present invention is manufactured by sequentially performing a series of well-known subsequent steps.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, according to the present invention, a portion of a bit line material is primarily etched, and then a bit line first isolation insulating layer is buried therebetween, thereby forming a bit line due to the bit line first isolation insulating layer. It is possible to prevent the bit line from falling down when etching the material.

Accordingly, the present invention prevents bit line collapse when forming a bit line with a high aspect ratio, thereby suppressing a short phenomenon between bit lines, and as a result, it is possible to form a reliable bit line. .

Claims (6)

Forming a bit line material on the semiconductor substrate on which the underlayer is formed; Forming two adjacent bit line forming regions on the bit line material and a first mask pattern covering an area therebetween; Etching the bitline material; Removing the first mask pattern; Forming first spacers on both sidewalls of the etched bitline material; Embedding a bit line first isolation insulating layer between the bit line materials on which the first spacer is formed; Forming a second mask pattern on the bit line material on which the bit line first isolation insulating layer and the first spacer are formed and covering the two bit line forming regions adjacent to each other and the bit line first isolation insulating layer formed therebetween; Etching the bit line material to form bit lines having a first spacer of a bit line, a first isolation insulating film bit line, and a first spacer of a second isolation insulating film bit line; Removing the second mask pattern; Forming a second spacer on opposite sides of the two adjacent bit lines; And A bit line second isolation insulating layer between the bit lines on which the second spacer is formed; Method of manufacturing a semiconductor device comprising a. The method of claim 1, And the bit line material is formed of a stacked layer of a bit line barrier film, a bit line conductive film, and a bit line hard mask film. The method of claim 2, The bit line barrier film is formed of a stacked film of a Ti film and a TiN film. The method of claim 2, And the bit line conductive film is formed of a tungsten film. The method of claim 2, The bit line hard mask film is a semiconductor device manufacturing method, characterized in that formed of a nitride film-based film. The method of claim 1, The first spacer and the second spacer is a semiconductor device manufacturing method, characterized in that formed by a nitride film-based film.

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