JPH03268332A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce gate length and gate resistance by a method wherein, while the patterning size of a first resist layer is kept, an insulating layer and a second resist layer on the first resist layer are constituted so as to have a stretched shape. CONSTITUTION:A second resist layer 9 is subjected to gate patterning; an insulating layer 8 and a first resist layer 5 are anisotropically etched by using the second resist layer 9 as a mask; only the insulating layer 8 is selectively etched, and the second resist layer 9 is formed in an overhang type; and by oblique beam incidence, the overhang part of the second resist layer 9 is made to retreat by an arbitrary amount. Hence the sectional shape of the obtained gate electrode constitutes a mushroom shape. Thereby the gate length is shortened, and the gate resistance can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a gate electrode of a field effect transistor or the like.

[Prior art 3] Figure 2 (-~(el is a cross-sectional view showing the manufacturing process of a conventional semiconductor device. In the figure, 1 is a semiconductor substrate made of gallium arsenide, etc., and 2 is a semiconductor substrate formed on a semiconductor board 1. Semiconductor active layer, 3 and 4 are drain'#71 electrodes and source electrodes formed on semiconductor active layer 2, 5 is a resist layer, 6 is a recess region formed on semiconductor active layer 2, 7 is a gate electrode, 70 is the gate electrode metal.

Next, a method for manufacturing a semiconductor device will be explained with reference to FIGS. 2(a-1). First, as shown in FIG. An electrode 4 is formed, and a resist layer 5 is laminated on the entire surface by a spin code method or the like.
Gate patterning is performed on the cyst layer 5 as shown in FIG. 2 (bl), and in FIG. next,
As shown in FIG. 2 (dl), the gate electrode metal 70 is deposited on the entire surface by vacuum evaporation or the like. Next, the resist [i5 and the gate electrode metal 70 on the resist layer 5 are removed by a lift-off method, and the recessed area 6 A gate electrode 7 is formed therein, and a semiconductor device as shown in FIG. 2 (el) is formed.

[Problem to be solved by the invention]

Since the conventional semiconductor device manufacturing method was configured as described above, the cross-sectional structure of the gate electrode was trapezoidal, and the gate length was an important point in improving the performance of field effect transistors. (Lg) shortening, gate folding,
In the conventional case, gate length (Lg
), there is a problem in that the gate resistance increases because the cross-sectional structure is trapezoidal. In addition, since the area where gate patterning is performed is a concave portion, the flatness is not good and the thickness of the resist becomes thick. there were.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method for manufacturing a semiconductor device that can shorten the gate length and reduce the gate resistance.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes sequentially stacking a first resist e, a flattened insulating layer, and a second resist layer, and patterning the second resist layer. The insulating layer and the first resist layer are anisotropically etched using the second resist layer as a mask. Next, after selectively etching only the insulating layer to form the second resist layer into an overhanging shape, the overhanging portion of the second resist layer is retreated by an arbitrary amount by irradiating an oblique beam such as RrBE. This is what I did.

[For production]

In the method of manufacturing a semiconductor device according to the present invention, the first resist layer maintains the date patterning dimension, and
The insulating layer on the resist layer and the second resist layer can have a shape larger than the gate patterning dimension, so the cross-sectional shape of the formed gate electrode has a short length (gate length) of the part that contacts the semiconductor active layer. Since the upper part of the gate is large (so-called pine mushroom gate), gate resistance can also be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 (al to (41) is a cross-sectional view showing an embodiment of the manufacturing process of a semiconductor device of the present invention. In the figure, 1 to 7 and 70 are the same as the conventional one, but here 5 is It is called a first resist layer. 8 is an insulating layer laminated on the first resist layer 5, and 9 is a second resist layer laminated on the insulating layer 8.

Next, a method for manufacturing a GaAs MES FET will be described with reference to FIGS. 1(al) to (1).

In FIG. 1 (at), a drain electrode 3 and a source electrode 4 are formed on a semiconductor active layer 2 such as n-type GaAs formed on a semi-e-type GaAs substrate 1, and a first resist layer is formed. 5 is coated on the entire surface by a spin code method or the like.At this time, it is desirable to make the film thickness of the first resist layer 5 as thin as possible within a range that can cover the stepped portion.Next, as shown in FIG. Like bl, the first resist ff!
An insulating layer 8 (for example, 5iCh・5iON-8iN
(insulating films such as ) are stacked and planarized. Plasma CVD or ECR (Electron Cyclotron Co-CVD) CVD is suitable for forming this insulation @8 at low temperatures.
A second resist (Iiii9) is laminated on the insulating layer 8 like cl, and gate patterning is performed. At this time, the second resist layer 9 and the first resist layer 5 are made of different materials. Since the underlying layer is flattened, the second resist Ili! 9 allows fine gate patterning,
This allows the gate length to be shortened. Also, Figure 1fd
In step 1, the second resist rt49 is used as a mask, and the insulating layer 8 and first resist layer 5 are anisotropically etched by RIE (reactive ion etching) or the like. Next, as shown in FIG. As shown in Figure 1 (fl), the overhang part of the second resist layer 9 is retreated.As a method for retreating the second resist layer 9, RIBE (reactive ion beam etching) or the like is used. The overhang part is made to recede by giving it shading.

Here, since the materials of the second resist #9 and the first resist layer 5 are different, conditions are adopted that allow for a large degree of selectivity between the two, and at the same time, the selection of the second resist layer 9 and the insulating layer 8 is also achieved. By increasing the size, even if the dimensions of the gate patterned portion of the second resist layer 9 expand and the incident beam enters the underlying side, the first resist layer 5 and the insulating layer 8 will not be etched, and the second resist layer 9 will not be etched. Only the etching of the resist layer 9 proceeds. Therefore, the fine patterning dimensions of the first resist layer 5 can be maintained as they were initially. Although the amount of retreat of the overhang portion of the second resist layer 9 is arbitrary, it is set so that it has an overhang shape with respect to the e-line layer 8.

This is to facilitate lift-off performed in a small number of steps.

Furthermore, in FIG. 1(g), the semiconductor active layer 2 is etched using the first resist layer 5 as a mask to form a recessed area 6. Subsequently, as shown in FIG. 1 fh), after a gate electrode metal 70 is deposited on the entire surface by vacuum deposition or the like, a first resist layer 5. is deposited by a lift-off method. Insulation #8. Second
The resist layer 9 and the unstable gate electrode metal 70 on the second resist layer 9 are removed, and the gate electrode 7 is formed in the recessed region 6. Finally, a semiconductor device as shown in FIG. 1 is obtained. .

〔Effect of the invention〕

As described above, according to the present invention, the second resist layer for gate patterning is flattened, so that fine gate patterning is possible, the gate length can be shortened, and the cross section of the gate electrode obtained by the present invention is The shape is
Because it has a pine mushroom shape, the gate length can be shortened.
Furthermore, since gate resistance can be reduced, device performance can be improved.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG.
FIG. 1 is a cross-sectional view showing the manufacturing process of a conventional semiconductor device. In the figure, the mountain is the semiconductor substrate, (2) is the semiconductor active layer,
(31 is the drain electrode, (4) is the source electrode, (5) is the first resist layer, (61 is the recess chain ring, (7) is the gate electrode, (8) is the insulating layer, (9) is the second resist layer,
(70) indicates gate electrode metal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 1 (1)

Claims (1)

[Claims] a step of forming a source electrode and a drain electrode on a semiconductor active layer formed on a semiconductor substrate; a first resist layer;
a step of sequentially laminating an insulating layer and a second resist layer;
A step of applying gate patterning to the resist layer of
A process of anisotropically etching the insulating layer and the first resist layer using the resist layer as a mask, and selectively etching the insulating layer to side-etch the desired amount to form the second resist layer into an overhang shape. a step of selectively etching the second resist layer with an obliquely incident ion beam to retreat the overhang portion by a desired amount; and a step of etching the semiconductor active layer using the first resist layer as a mask to form a recessed region. a step of forming a gate electrode metal; a step of laminating gate electrode metal; and a step of removing unnecessary gate electrode metal on the first resist layer, the insulating layer, the second resist layer, and the second resist layer. A method for manufacturing a semiconductor device, characterized by: