JPH03239325A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a yield without causing the mutual dislocation between a first recess and a second recess by a method wherein, when a two-stage recess structure is formed, the second recess is formed at the inside of the first recess in a self-aligned manner. CONSTITUTION:A first insulating film 9 is formed on the surface of an active layer 2; an opening part is formed selectively in the insulating film 9; a first recess 11 is formed by a wet-etching method. A second insulating film 10 is formed on the first insulating film 9 and the first recess 11. The second insulating film 10 is removed by an anisotropic etching method until the bottom of the first recess appears in a prescribed width. A second recess 12 is formed by a wet-etching method by using the second insulating film 10 as a mask. In this manner, a self-alignment process in which the active layer 2 is etched by using the second insulating film 10 as the mask and the second recess 12 is formed is adopted. As a result, the dislocation between the first recess and the second recess 11, 12 is not caused, and a yield can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device having a two-stage recess structure.

[Conventional technology]

In the field of semiconductor devices, high integration and miniaturization are rapidly progressing, and as a result, the range of applications of semiconductor devices is expanding, and higher reliability and improved performance are required.

This is true not only for silicon devices but also for compound semiconductor devices. In the latter case, especially in field effect transistors, the structure of the gate electrode and its formation method are extremely important, and there are many development examples. Introduced.

FIG. 3 is a sectional view of a compound semiconductor device having a conventional two-stage recess structure.

In the figure, (1) is a compound semiconductor substrate (2) is an active layer, +31 is an ohmic electrode, (4) is a gate electrode, and (6) is an ohmic electrode.
; is the first recess, and (8) is the second recess.

Next, a method for manufacturing the semiconductor device constructed as described above will be explained in sequence with reference to FIGS.

First, an active layer (2) is formed on the surface of a compound semiconductor substrate (1) by, for example, ion implantation and annealing, and then an ohmic electrode (3) is formed on the active layer (2). (Figure 4(a)) Next, after forming a photoresist pattern (5), the active layer (2) is etched by RIE (reactive ion etching) using the photoresist pattern (5) as a mask. Etching to form a first recess (6). (Figure 4(b)) Next, after removing the resist pattern (5), a photoresist pattern (7) is formed so as to selectively have openings in the first recess, and Similar to the time of formation, the V-shaped viscous layer (2) is etched by RIE or the like to form a second recess (8). (Fig. 4 (C)) Next, a metal (4) that will become the gate electrode material, for example A/, is formed all over the wafer by a steaming method (Fig. 4 (d)).
)) Furthermore, the resist pattern (7
) and the metal (4) above it, a semiconductor device having the two-stage recess structure shown in FIG. 3 is obtained.

[Problem to be solved by the invention]

A conventional compound semiconductor substrate having a two-stage recess structure has the above-described structure and manufacturing method, and is shown in Fig. 4(c).
When forming the second recess (8) inside the first recess (6), the exact alignment is very difficult and often the second recess (8) or the 1 recess (
6) Defects such as protrusion may occur, resulting in a problem of significantly lowering yield.

This invention was made in order to eliminate the above-mentioned problems, and provides a semiconductor device that can be easily manufactured without misalignment in the process of aligning the first recess and the second recess. The purpose is to sound the manufacturing method.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes forming an active layer on the surface of a substrate, and forming a first recess in the layer and a second recess in the center of the first recess. In a method for manufacturing a semiconductor device including a recess and a gate electrode made of a high melting point metal and a low resistance metal on the second recess, a first insulating film is formed on the surface of the active cylinder, and the insulating film a first recess is formed by a wet etching method by selectively forming an opening in the first insulating film and a second insulating film in the first recess; The second insulating film is removed by an anisotropic etching method until a predetermined width of the bottom surface of the recess appears, and the second recess is formed by a wet etching method using the second ELL film as a mask. It is.

[For production]

In this invention, the second fermentation membrane provided in the first recess is etched by %-oriented etching until a predetermined width of the bottom surface of the first recess is exposed;
Since a self-alignment process is adopted in which the active layer is etched using the edge film as a mask to form the second recess, no aft deviation occurs between the first and second recesses.

[Embodiment 1 A] An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a sectional view showing a two-stage recess structure of a semiconductor device according to an embodiment of the present invention. In the figure, (1) is a compound semiconductor substrate, (2) is an active layer, and (3) is an ohmic electrode. , (9) is the first insulating film, +101 is the second insulating film, (111 is the first recess, [2+ is the second recess,
(13) is a high melting point metal part of the gate electrode, and 04) is a low resistance gold island part of the gate electrode.

FIG. 2 is a cross-sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention.

First, an active layer (2) is formed on a compound semiconductor substrate (1), for example, a GaAs substrate, by ion implantation and annealing, or epitaxial growth, and then an ohmic chamber frame (3), for example, AuGe/Ni is formed. (
Figure 2 (a)) Next, Prada? SiN, Sin by CVD method etc.

After forming the first @ edge film (91) made of a 5iON film or the like, a resist pattern is formed so as to have an opening between the ohmic electrodes 131 (FIG. 2(b)). 15) as a mask, the first insulating film (9) is etched using RIE method etc. to expose the surface of the active layer (2) (Fig. 2(C)). Using the film (9) and the resist q51 as a mask, the active layer (2) is etched by wet etching to form a first recess (11).Then, the resist u5+ is removed (FIG. 2(d)). ) Again, the second insulating film made of SiN, 5iON, 8i0, etc.
10) is formed on the entire surface using a plasma CVD method or the like. (FIG. 2(e)) Next, the second insulating film (10) is etched over the entire surface of the first recess opening 1 until a predetermined width of the active layer (21) is removed using RIE or the like. At this time, the first recess 01
The second insulating film (10) remains within the substrate 1 as a sidewall assist. (FIG. 2(f)) Next, using the side wall assist as a mask, a second recess FI is formed in the first recess 01 by wet etching.
21 is formed. (Fig. 2 fg+) At this time, the second
The recess 1121 is self-aligned with the first recess (11)
Since it is formed within, it does not protrude from the second recess (121) or the first recess (11j) as in the prior art.

Next, a high melting point metal f131, such as WSi, TiN, W
N or the like is formed on the entire surface by sputtering or the like. Historically, low resistance metals (14) such as Au, Cu, Ag, A
/ etc. are formed by sputtering or vapor deposition to form a resist pattern for gate wiring. (Figure 2 (h
)) Next, using the resist (1e) as a mask, the high-melting point metal +131 and the low-resistance metal (14), which will become the gate electrode, are continuously removed by etching.At this time, the etching method includes ion milling, RIE, Or wet etching method etc. can be used.After this, resist 0
61 is removed. (Fig. 2 (1)) Finally, the first insulating film (9) on the ohmic electrode (31) is etched by RIE method or the like to expose the ohmic electrode (3), thereby forming the semiconductor shown in Fig. 1. The equipment is damaged.

In addition, in the above embodiment, G was used as the compound semiconductor substrate (1).
Although we have explained the case of aAs, in addition to GaAs, 8i
, Ga1nAs, GaP, Ga1nAs, etc. may be used. In addition, high melting point metal (13) and low resistance metal (
14) has been described as a two-chest metal structure, but a multilayer metal structure having three or more layers may be used. In any of the above cases, the same effect can be achieved.

[Effects of the Invention] As described above, according to the present invention, when forming a two-stage recess structure, the second recess is formed in a self-aligned manner inside the first recess. Also, there is an effect that semiconductor devices can be manufactured with high yield without causing any positional deviation between the second recesses.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a sectional view showing the manufacturing process of the semiconductor device of FIG. cross section,
FIG. 4 (at to fdl are cross-sectional views showing the manufacturing process of the semiconductor device in FIG. 3. In the figure, (1) is a compound semiconductor substrate, (2) is an active layer, and (9) is a first insulating layer. The film and grip are the second insulating film, (11
) is the first recess, t12) is the second recess, +13
1 is a high melting point gate metal, and (14) is a low resistance gate metal. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) having an active layer on the surface of the substrate, a first recess in the layer and a second recess formed in the center of the first recess, and a high melting point metal on the second recess; A method for manufacturing a semiconductor device having a gate electrode made of a low-resistance metal, the method comprising: (a) providing a first insulating film on the surface of the active layer, selectively forming an opening in the film, and then wet etching. Step (a) of forming a first recess by a method, a second insulating film is provided on the first insulating film and the first recess, and an anisotropic etching is performed until the bottom surface of the first recess appears with a predetermined width. , a step of removing the second insulating film; and a step of forming the second recess by a wet etching method using the second insulating film as a mask. .