JPH0195564A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To position a gate electrode highly accurately by a method wherein, after a first ion implantation layer of a first conductivity has been formed on a semiconductor substrate and a second ion implantation layer of a second conductivity has been formed on it, the first and the second ion implantation layers are activated. CONSTITUTION:Ions of an impurity are implanted into a compound semiconductor substrate 10; first ion implantation layers 11, 12 of a first conductivity type are formed on its surface; a first insulating film 14 is formed on a whole face of the substrate 10. Then, a second insulating film 16 having an opening 15 is formed on the first insulating film 14; ions of an impurity are implanted into the first ion implantation layers 11, 12 through the opening 15 in the second insulating film 16; a second ion implantation layer 13 of a second conductivity type is formed on the surface. Then, the second insulating film 16 is removed; while only a conductor layer 19 on an exposed face of the substrate 10 is left, a surface electrode 20 is formed; after that, an annealing operation is executed; the first and the second ion implantation layers 11-13 are activated. By this setup, a gate electrode can be positioned highly accurately with reference to a gate region of a fine size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a junction field effect semiconductor device using a ■-v group compound semiconductor substrate.

(Prior art) Among field-effect semiconductor devices, so-called FETs, ■-v
Although GaASF uses a group of compound semiconductors as a substrate,
There are ET etc. A so-called MES type GaASFET using a Jittky barrier gate is widely used because of its simple process. On the other hand, junction type FET
(hereinafter referred to as J-FET), the barrier hide φB of the junction can be set as large as 1V or more, and the normally
It is possible to obtain sufficient operating margin even as an off-type device, and it is possible to manufacture both N-channel and P-channel structures by ion implantation, and a complementary circuit configuration can be realized.
There are advantages such as However, the fine processing of the gate part is
It is more difficult than conventional methods, and its development is still lagging behind.

By the way, there are various types of J-FETs depending on the method of forming the gate region, such as diffusion bonding type, ion implantation bonding type, epitaxial growth bonding type, etc., but in all of them, the problem is that the gate electrode can be taken out. . That is,
Conventionally, after forming a gate region, a gate electrode is aligned by mask alignment on top of the gate electrode, and then formed using a lift-off method or an etching method, or the gate electrode is not directly provided on the gate region, and conduction with the gate region is formed. There is a method of making contact with the gate electrode through a part of the region.

By the way, the gate region is a minute region. The reason is,
The mutual conductance gm as a performance factor of the element is W(
Q
In order to reduce the value of lll, W must be thin (and L must be long).The problem is that in order to position the gate electrode on this micro region of about 1 μm to 2 μm, it is necessary to estimate the accuracy of mask alignment. However, implementation is impossible from the viewpoint of mass production such as yield.

In addition, the method using a partial region that is electrically connected to the gate region is
Since the gate is routed through the semiconductor layer, the gate resistance increases by about one to two orders of magnitude compared to metal wiring.

Therefore, although such a method has a small effect on low-frequency FETs, it is not preferable mainly for high-frequency applications because the noise figure (NF) and gain, which are the performance of the device, decrease as the frequency increases.

(Problems to be Solved by the Invention) As described above, in the conventional manufacturing method, the method of positioning the gate electrode with respect to the gate region is impossible to implement from the viewpoint of mass production such as yield.

Other methods using a partial region electrically connected to the gate region degrade the performance and cannot be used for high frequency applications (there is a problem called X).

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide a gate electrode that can be positioned with high precision in a gate region of minute dimensions and that is suitable for high frequency applications. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be manufactured.

[Structure of the Invention] (Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes implanting impurity ions into a compound semiconductor substrate to form a first conductivity type first impurity ion on the surface of the compound semiconductor substrate.
A step of forming an ion implantation layer and a step of forming a first layer on the entire surface of the substrate.
A step of forming an insulating film, a step of forming a second insulating film having a first opening in a part on the first insulating film, and a selective etching method using the second insulating film as a mask. forming a second opening in the first insulating film;
Impurity ions are introduced into the first opening through the first opening of the insulating film.
A step of implanting ions into the ion-implanted layer and forming a second ion-implanted layer of a second conductivity type on the surface of the ion-implanted layer; and a step of implanting at least a refractory metal layer or a refractory metal layer in the lowermost layer with the first insulating film remaining. a step of depositing a conductive layer comprising a layer containing the second insulating film, and removing the conductive layer on the surface thereof by removing the second insulating film, and depositing the conductive layer on the exposed surface of the substrate through the first opening of the second insulating film. A step of forming a surface electrode while leaving only the deposited conductor layer, and an annealing treatment are performed to
The method consists of a step of activating the ion implantation layer.

Further, the method for manufacturing a semiconductor device includes a step of forming a first conductivity type semiconductor region on a compound semiconductor substrate, a step of forming an insulating film having an opening in a part on the semiconductor region, and a step of forming the insulating film on the semiconductor region. forming a groove in the surface of the semiconductor region by selective etching using a mask as a mask, and implanting impurity ions into the groove through the opening of the insulating film to implant ions of a second conductivity type into the surface of the semiconductor region. a step of forming a conductive layer, a step of depositing a conductor layer whose bottom layer is at least a refractory metal layer or a layer containing a refractory metal while leaving the insulating film; A process of removing the conductive layer on the surface and forming a surface electrode by leaving only the conductive layer deposited on the surface of the semiconductor region through the opening of the insulating film, and performing an annealing treatment to remove the ion-implanted layer. The process consists of a step of activating the .

(Function) In the method of the present invention, the insulating film used as a mask for ion implantation to form a gate region is also used as a mask for depositing gate electrode material, so that the gate electrode is self-aligned with respect to the gate region. is formed.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views sequentially showing each step when the present invention is applied to a method of manufacturing an ion implantation junction type J-FET.

First, ions of Sl are selectively implanted into the GaAS substrate 10. At this time, an ion acceleration voltage Vac of 180 KeV is applied to the regions where the source and drain are to be formed.

Ion implantation is performed at a dose of ff1Qd of 5×10 13 /cm 2 to form ion implanted layers 11 and 12. In addition, in the region where the channel is to be formed, the ion acceleration voltage Vac is set to 100 KeV, and the dose amount Qd is set to 3×10' 2
The ion implantation layer 1 was formed by performing ion implantation under the condition of /cm2.
3 (Fig. 1(a)).

Next, the entire surface is coated with 5 layers by CVD (chemical vapor deposition method).
10211g14 is formed to a thickness of 5000 mm, and a photoresist film 16 having an opening 15 at a location corresponding to the gate region is formed thereon. Subsequently, using this photoresist vA16 as a mask, the 5iO21114 is etched by an isotropic etching technique using an NH4F solution to form an opening 17 in the Si021114. After that, zn is applied to the surface of the ion implantation layer 13 through the openings 15 and 17 at an acceleration voltage yac of 80 KeV.
, ion implantation is performed under the condition that the dose amount Qd is lX101'/cm'' to form ion-implanted Wi1B (see Fig. 1).
b)).

Next, as the metal for forming the gate electrode, a TiW layer with a thickness of 1,000 wafers is used as the first layer, and a TiW layer with a thickness of 5,000 wafers is used as the second layer.
A conductor layer 19 is formed by depositing each U layer by sputtering in an Ar gas atmosphere. At this time, Si
A conductive layer 19A is also formed on the surface of the ion implantation layer 11i13 through the opening 17 formed in the O2 film 14 (FIG. 1(C)).

The conductor M19 may be made of any material that does not deteriorate the ohmic contact with the gate region even after subsequent annealing, and may be made of a TiW layer, a WN layer, a WSi layer, etc.
A structure in which the layer in contact with the GaAS substrate 10 is made of a high melting point metal, such as a layer containing a high melting point metal such as L or a two-layer structure of WNii and an Au layer, can be used.

Next, by removing the photoresist film 16, the conductor layer 19 formed on the surface thereof is also removed at the same time. That is, by removing the conductor layer 19 by so-called lift-off, only the conductor WJ19A formed on the surface of the ion implantation layer 13 is left, and the gate electrode 20 is formed. (Figure 1(d)).

Next, after removing the above 5i0211114, PSGg! is applied to the entire surface by CVD. 21 with a thickness of 5000 people,
Thereafter, an annealing process is performed at 800° C. for 15 minutes in an Ar gas atmosphere to activate the impurities that have been ion-implanted and form the N+ type source and drain regions 22 and 23, the N type channel region 24, and the P type gate. Regions 25 are respectively formed (FIG. 1(e)).

At the same time, the gate electrode 20 comes into ohmic contact with the surface of the gate region 25, completing the gate structure.

Finally, the first layer contains 5% Ge and has a thickness of 2000 people.
Source electrode 2 with uGe film and second layer 1000 μm thick
6 and drain electrode 27 are formed by, for example, a lift-off method, and then alloying is performed at 400° C. for 3 minutes to establish ohmic contact, thereby completing the desired J-FET structure (FIG. 1(f)).

In the FET manufactured by this method, the gate electrode 20 is in direct contact with the gate region 25, so the gate resistance can be sufficiently reduced, and the noise figure and gain at high frequencies are not impaired. do not have. Furthermore, the P-type gate region 25 and the gate electrode 20 are made of photoresist g! They are formed by performing ion implantation or sputtering through the same openings 15 of 16, and the two are aligned in a self-aligned manner. Therefore, even if the gate region 25 is formed with minute dimensions, the gate electrode 20 can be arranged without reducing the yield.

By the way, in the method of the above embodiment, after forming the gate electrode 20, an annealing treatment is performed to form the N+ type source and drain regions t4t22.23, the N type channel region 24, and the P type gate region 25. Since the gate region 25 extends laterally during the activation of the ion implantation 11118, there is almost no possibility that the gate electrode 20 will come into contact with the channel region 24. However, although the impurities to be ion-implanted are incident almost perpendicularly to the substrate 10, the gate electrode material by sputtering is distributed at a planetary setting angle. Contact is also possible.

- FIGS. 2A to 2C are cross-sectional views sequentially showing the steps of a method according to another embodiment of the present invention, which is capable of preventing contact between the gate electrode 20 and the channel region 24 as described above. be. In the method of this embodiment, the steps from FIG. 1(a) to FIG. 1(C) are the same. After that, the conductor layer 19 is removed by lift-off, and the conductor layer 19 is removed.
A gate electrode 20 is formed leaving only A. Subsequently, using the Si 02 film 14 and the gate electrode 20 as a mask, Zn is again accelerated at an acceleration voltage Vac of 80 KeV and a dose lQ.
d is 1X101! By performing ion implantation under the condition of I/cm2, an ion implanted FIJ 18 with enlarged dimensions is formed (FIG. 2(a)).

After this, as in the case of Fig. 1, PSGg121 is first formed to a thickness of 5,000 yen on the entire surface by CVD, and then annealing treatment is performed at 800°C for 15 minutes in an Ar gas atmosphere, and ions have already been implanted. Activate the impurities
+-type source and drain regions 22 and 23, an N-type channel region 24, and a P-type gate region 25 are formed (FIG. 2(b)).

Next, a source electrode 26 and a drain electrode 27 are formed, and then alloying is performed to achieve ohmic contact.
The desired J-FET structure is completed (FIG. 2(C)).

According to such a method, since the gate region 25 is formed to extend laterally with respect to the gate electrode 20, contact between the gate electrode 20 and the channel region 24 can be prevented.

FIGS. 3(a) to 3(e) are cross-sectional views sequentially showing each step when the present invention is applied to a method for manufacturing an epitaxially grown junction type J-FET.

First, an N-type GaAS semiconductor region 31 is formed on a GaAS substrate 30 by epitaxial growth. next,
A photoresist WA33 having an opening 32 at a location corresponding to the gate region is formed thereon, and then, using this photoresist [133 as a mask, the N-type GaAS
The semiconductor region 31 is etched to form a trench 34 having a depth corresponding to the desired equivalent value.

Etching at this time is carried out using an etching solution having a volume ratio of, for example, 3 parts of phosphoric acid, 1 part of aqueous peroxide solution, and 50 parts of pure water (FIG. 3(a)).

After that, the N-type GaAs semiconductor region 3 corresponding to the bottom of the groove 34 is passed through the opening 32 of the photoresist ll33.
1, acceleration voltage VaC is 80 KeV, dose amount Qd
Ion implantation is performed under the condition of 1.times.101'/Cm2 to form ion implantation 11135 (FIG. 3(b)).

1000 in the first layer as a metal for forming the gate electrode,
A TiW layer with a thickness of 5000 people was added to the 21st TiW layer with a thickness of 5000 people.
A conductor H36 is formed by depositing u1m by sputtering in an Ar gas atmosphere. At this time, a conductive layer 36A is also formed on the surface of the ion implantation layer 35 through the opening 32 formed in the photoresist film 33 (FIG. 3(C)). As in the case of the embodiment shown in FIG. 1, the conductor layer 36 may be made of any material that does not deteriorate the ohmic contact with the gate region even after subsequent annealing, and other materials include TiW layer and WNil.

A layer containing a high melting point metal such as WSili or a WN layer and A
A structure in which the layer in contact with the N-type GaAs semiconductor region 31 is made of a high melting point metal, such as a two-layer structure of a u layer, can be used.

Next, by removing the photoresist Wi33, the conductor layer 36 formed on its surface is also removed at the same time. That is, the conductor layer 36 is removed by so-called lift-off.
is removed, thereby leaving only the conductor layer 36A formed on the surface of the N-type GaAs semiconductor region 31, thereby forming the gate electrode 37.

After that, apply 5000 coats of PSGli38 to the entire surface by CVD.
Formed to a thickness of about 100 yen, and then heated to 80° C. in an Ar gas atmosphere.
Annealing treatment is performed at 0° C. for 15 minutes to activate the impurities already ion-implanted and form a P-type gate region 39 (FIG. 3(d)).

At the same time, the gate electrode 37 comes into ohmic contact with the surface of the gate region 39, completing the gate structure.

Finally, the first WJ is an AuGe film with a thickness of 2000 μm containing 5% Ge, and the second layer is a source electrode 40 and a drain electrode 41 with a thickness of 1000 μm, for example, formed by a lift-off method, and then at 400° C. Alloying is performed for 3 minutes to achieve ohmic contact, and the desired J-FET structure is completed (FIG. 3(e)).

Even in the FET manufactured by this method, the gate electrode 31 is in direct contact with the gate region 39, so the gate resistance can be sufficiently reduced, and the noise figure and gain at high frequencies will not be impaired. do not have. Further, the P-type gate region 39 and the gate electrode 37 are formed by ion implantation or sputtering through the same opening 32 of the photoresist 11133,
Both are aligned in a self-aligning manner. For this reason,
Even if the gate region 39 is formed with minute dimensions, the upper gate electrode 37 can be placed without reducing the yield.

[Effects of the Invention] As explained above, according to the method of the present invention, it is possible to position the gate electrode with high precision in a gate region of minute dimensions, and to manufacture a device suitable for high frequency applications. can.

[Brief explanation of the drawing]

FIGS. 1(a) to 1f) are cross-sectional views sequentially showing steps according to a method according to an embodiment of the present invention, and FIGS. 2(a) to C
) are cross-sectional views sequentially showing steps according to a method according to another embodiment of the present invention, and FIGS. 3(a) to 3e) are cross-sectional views sequentially showing steps according to a method according to still another embodiment of the present invention. 10, 30・G a A S I board, 11.12.13
．． 18.35--Ion implantation layer, 14-SiO2
Membrane, 15.17.32... Opening, 16.33...
Photoresist film, 11...opening, 19, 36...
・Conductor layer, 20.37... Gate electrode, 21.38
...PSG film, 22...source region, 23...drain region. 24... Channel region, 25.39... Gate region, 26.40... Source electrode, 27.41... Train electrode, 31... GaAs semiconductor region, 34...
groove. Applicant's agent Patent attorney Takehiko Suzue J111 Figure 1 Figure 2 A

Claims (11)

[Claims] (1) A step of implanting impurity ions into a compound semiconductor substrate to form a first ion-implanted layer of a first conductivity type on the surface thereof, a step of forming a first insulating film on the entire surface of the substrate, and a step of forming a first insulating film on the entire surface of the substrate; forming a second insulating film having a first opening on the first insulating film; and forming a second opening in the first insulating film by selective etching using the second insulating film as a mask. a step of injecting impurity ions into the first ion implantation layer through the first opening of the second insulating film to form a second ion implantation layer of a second conductivity type on the surface thereof; 2. A step of depositing a conductor layer whose bottom layer is at least a high melting point metal layer or a layer containing a high melting point metal while leaving the second insulating film, and removing the second insulating film to remove the conductor layer on the surface. forming a surface electrode by removing the layer and leaving only the conductor layer deposited on the exposed surface of the substrate through the first opening of the second insulating film, and performing an annealing treatment to remove the first and second layers. 1. A method for manufacturing a semiconductor device, comprising the step of activating an ion implantation layer. (2) The step of implanting impurity ions into the substrate to form a first ion implantation layer of the first conductivity type on the surface thereof is performed by two ion implantation steps with different impurity ion acceleration energies and doses. A method for manufacturing a semiconductor device according to claim 1. (3) The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the second opening in the first insulating film is performed by an isotropic etching method. (4) The method of manufacturing a semiconductor device according to claim 1, wherein the step of depositing the conductor layer is performed by a sputtering method. (5) The method for manufacturing a semiconductor device according to claim 1, wherein the compound semiconductor substrate is a III-V group compound semiconductor substrate. (6) The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film is a photosensitive resin film. (7) After forming the surface electrode, impurity ions of a second conductivity type are implanted into the first ion implantation layer using the surface electrode and the first insulating film as a mask. A method for manufacturing a semiconductor device according to. (8) A step of forming a semiconductor region of a first conductivity type on a compound semiconductor substrate, a step of forming an insulating film having an opening in a part on the semiconductor region, and a selection using the insulating film as a mask. forming a groove on the surface of the semiconductor region by etching; and implanting impurity ions into the groove through the opening of the insulating film to form an ion-implanted layer of a second conductivity type on the surface of the semiconductor region. , a step of depositing a conductor layer whose bottom layer is at least a refractory metal layer or a layer containing a refractory metal while leaving the insulating film; and removing the insulating film to form a conductor layer on the surface. a step of removing the insulating film and leaving only the conductor layer deposited on the surface of the semiconductor region through the opening of the insulating film to form a surface electrode; and a step of activating the ion implantation layer by performing an annealing treatment. A method for manufacturing a semiconductor device, comprising: (9) The method of manufacturing a semiconductor device according to claim 8, wherein the step of depositing the conductor layer is performed by a sputtering method. (10) The method for manufacturing a semiconductor device according to claim 8, wherein the compound semiconductor substrate is a III-V group compound semiconductor substrate. (11) The method for manufacturing a semiconductor device according to claim 8, wherein the insulating film is a photosensitive resin film.