JPH0555266A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To form the fine gate electrode of a field-effect transistor of a structure, wherein a backward breakdown strength is high and the capacity between a gate and a source is small. CONSTITUTION:A non-doped GaAs layer 3 is formed on an N-type GaAs layer 2, a gate electrode 6a is formed in a recess in the layer 3, an ion implantation is performed using this electrode 6a as mask and the layer 3 is made to remain on the side surfaces of the electrode 6a to form an N-type high-concentration layer 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly to a field effect transistor using a compound semiconductor.
The present invention relates to a field effect transistor having a recess type gate electrode which requires a gate length of 5 μm or less, and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional main manufacturing process of a field effect transistor having a recess type gate electrode.
aAs substrate, 2 is n-type G formed on GaAs substrate 1
a is an As layer, 9 is a recess formed in a predetermined portion of the n-type GaAs layer 2 by using a photoresist 5, 10 is a metal for forming a gate electrode, and 10a is a gate formed in the recess 9. It is an electrode.

The manufacturing method will be described below. First,
As shown in FIG. 4A, a resist pattern 5 having a desired opening size is formed on the n-type GaAs 2, and wet etching is performed using the resist 5 as a mask to form a recess 9.

Next, in this state, the gate metal 10 is vapor-deposited on the entire surface (see FIG. 4 (b)) and the resist 5 is removed. As shown in FIG. 10a is formed.

When the gate electrode is formed by the above method, as shown in FIG. 5, the gate metal itself deposited on the resist 5 at the time of vapor deposition of the gate metal 10 also serves as a mask to form the gate electrode in the recess. 10b becomes thin, especially when forming a fine gate electrode of 0.5 μm or less, the opening of the resist is blocked, the cross section of the electrode becomes triangular, the resistance of the gate electrode becomes high, and the device characteristics deteriorate. Cause of.

Therefore, as shown in FIG. 6, n-type GaAs
An insulating film 4 having a desired opening is formed on the layer 2 and a recess is formed by performing anisotropic dry etching using the insulating film 4 as a mask, and then a T-type gate electrode is formed by a sputtering method or an RIE method. 10c or, as shown in FIG. 7, after forming the recess in the same manner as in FIG. 6, the side wall 11 of the insulating film is formed on the side surface of the recess to form the T-type gate electrode 10d.
Is used.

[0007]

The conventional field effect transistor is manufactured and constructed as described above, and in the method of FIG. 6, the side surface of the gate 10c is the n-type GaAs layer 2.
Therefore, there is a problem that the reverse breakdown voltage becomes low,
Further, the method of FIG. 7 has a problem that the gate-source capacitance increases due to the presence of the insulating film 11 on the side wall of the recess, device characteristics deteriorate, and the process becomes complicated.

The present invention has been made to solve the above problems, and a field effect transistor having a fine T-type gate electrode without causing deterioration of reverse breakdown voltage and increase of gate-source capacitance, and It is intended to provide a manufacturing method thereof.

[0009]

In the field effect transistor and the method of manufacturing the same according to the present invention, a non-doped semiconductor layer having a recess is formed on a semiconductor layer in which impurities are implanted, and a gate electrode is formed in the recess. After that, impurity implantation is performed using the gate electrode as a mask to form a second impurity implanted semiconductor layer while leaving the non-doped semiconductor layer on the side surface of the gate electrode.

Further, at the time of impurity implantation, oblique implantation centering on the gate electrode is performed to reduce the non-doped semiconductor layer region on the side surface of the gate electrode.

[0011]

According to the present invention, the side surface of the gate electrode is in contact with the non-doped semiconductor layer having a low dielectric constant and is not in contact with the semiconductor layer into which impurities are implanted, so that the reverse breakdown voltage is not deteriorated and the gate-source capacitance is reduced. Can be reduced.

Further, since the region of the non-doped semiconductor layer on the side surface of the gate electrode is reduced by the oblique ion implantation, the resistance between the gate and the source (drain) can be reduced.

[0013]

1 is a sectional view of a field effect transistor according to a first embodiment of the present invention, in which the same reference numerals as those in FIGS. 4 to 7 designate the same or corresponding parts, and 7 designates a gate electrode 6a as a mask, The high-concentration n layer is obtained by selectively ion-implanting the non-doped GaAs layer 3, and 31 is the non-doped GaAs layer remaining during the selective ion implantation.
Further, 4 is an insulating film formed between the gate 6a and the non-doped GaAs layer 3, and 8a and 8b are source and drain electrodes formed on the high concentration n layer 7.

Next, the manufacturing method will be described with reference to FIG. First, as shown in FIG. 2 (a), n-type Ga
After forming a non-doped GaAs layer 3 on the As layer 2 and further depositing an insulating film 4 by a CVD method or the like, a resist pattern 5 having a desired opening size is formed by a transfer technique, and the resist 5 is used as a mask for insulation. RIE the membrane 4
Etching by a method or the like.

Next, as shown in FIG. 2 (b), after removing the resist 5, the non-doped GaAs layer 3 is anisotropically etched by the RIE method or the like using the insulating film 4 as a mask to form a recess, and the entire surface is sputtered. The refractory metal 6 such as WSi is deposited by, for example,

Next, as shown in FIG. 2 (c), a resist residual pattern having a size larger than the opening size of the recess is formed by the transfer technique, and the refractory metal 6 and the insulating film 4 are etched by the RIE method or the like. After forming the gate electrode 6a and removing the resist, the non-doped GaAs layer 3 is made into the high-concentration n layer 7 by selectively implanting high-concentration ions by using the gate electrode 6a as a mask by an ion implantation method. At this time,
The non-doped GaAs layer 31 remains on the side surface of the gate electrode 6a due to the expanded portion above the gate electrode 6a.

Next, as shown in FIG. 2D, source and drain electrodes 8a and 8b are formed by vapor deposition and lift-off method.

As described above, according to this embodiment, nGaAs
A non-doped GaAs layer 3 is provided on the layer 2, a recess is formed in the non-doped GaAs layer 3, a metal 6 is deposited, and patterning is performed using a resist having an opening larger than the width of the recess to form a gate electrode 6a. Since the high-concentration n layer 7 is obtained by performing high-concentration ion implantation into the non-doped GaAs layer 3 using the gate electrode 6a as a mask, the side surface of the gate electrode 6a should be in contact with the non-doped GaAs layer 31 having a low dielectric constant. Therefore, the reverse breakdown voltage is not deteriorated, and the gate-source capacitance can be reduced. The non-doped GaAs layer 31 is the gate electrode 6a.
Since it is formed in a self-aligned manner using as a mask, the manufacturing process does not become complicated.

Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, the source resistance is reduced by narrowing the non-doped layer region on the source electrode 8a side as shown in FIG.

Next, a method of manufacturing the above structure will be described. After forming the gate electrode 6a in the same manner as in the first embodiment, when ion implantation is performed using the gate 6a as a mask, high-concentration ions are obliquely implanted only on the source electrode 8a side, and then from the vertical direction to the entire surface. By implanting high-concentration ions, a high-concentration n layer on the source electrode 8a side is formed up to near the gate 6a, and a narrow non-doped layer region 3a is formed.

In the second embodiment, the source electrode 8
Although the non-doped layer region is narrowed by obliquely implanting only the a side, the drain side may be obliquely implanted in a device that does not require a high reverse breakdown voltage.

Although WSi is used as the refractory metal to form the gate metal 6, another refractory metal or a two-layer structure such as WSi / Au may be used to reduce the gate resistance.

[0023]

As described above, according to the present invention, a non-doped semiconductor layer having a recess is formed on a semiconductor layer into which impurities are implanted, a gate electrode is formed in the recess, and then the gate electrode is formed. Impurity implantation is performed as a mask, and the second non-doped semiconductor layer is left on the side surface of the gate electrode.
Since the impurity-injected semiconductor layer of is formed, the side surface of the gate electrode is in contact with the non-doped semiconductor layer having a low dielectric constant,
Since it is not in contact with the semiconductor layer in which the impurities are implanted, there is an effect that the reverse breakdown voltage does not deteriorate and the gate-source capacitance can be reduced.

Since the region of the non-doped semiconductor layer is made smaller by the oblique ion implantation, there is an effect that the resistance between the gate and the source (or the drain) can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a field effect transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of a field effect transistor according to an embodiment of the present invention.

FIG. 3 is a sectional view showing the structure of a field effect transistor according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a conventional field effect transistor.

FIG. 5 is a process cross-sectional view for explaining a problem caused by a conventional method for manufacturing a field effect transistor.

FIG. 6 is a sectional view showing another example of a field effect transistor manufactured by a conventional manufacturing method.

FIG. 7 is a sectional view showing still another example of a field effect transistor manufactured by a conventional manufacturing method.

[Explanation of symbols]

 1 GaAs substrate 2 n-type GaAs layer 3 non-doped GaAs layer 4 insulating film 5 photoresist 6 refractory metal 6a gate electrode 7 high-concentration n layer 8a source electrode 8b drain electrode 31 remaining non-doped GaAs layer

Claims (4)

[Claims] 1. A field effect transistor having a gate electrode in Schottky contact and source and drain electrodes in ohmic contact on a semiconductor layer into which impurities are implanted, the recess being formed on the semiconductor layer. A second impurity-implanted semiconductor layer, a non-doped semiconductor layer formed on a recess sidewall of the second impurity-implanted semiconductor layer, a gate electrode contacting the non-doped semiconductor layer and contacting the semiconductor layer on the bottom surface of the recess A field effect transistor comprising: 2. The field effect transistor according to claim 1, wherein at least one of the source electrode side and the drain electrode side of the non-doped semiconductor layer in contact with the gate electrode is
A field effect transistor characterized by being smaller than a non-doped semiconductor layer formed on the other electrode side. 3. A method for manufacturing a field effect transistor, comprising forming a recess on a semiconductor layer in which impurities are implanted and forming a gate electrode in the recess, wherein a non-doped semiconductor layer is formed on the semiconductor layer in which impurities are implanted. And a step of forming a recess having a predetermined opening width in the non-doped semiconductor layer, and after forming a metal layer on the entire surface, using a resist having an opening larger than the predetermined opening width, the metal A field effect transistor comprising: a step of patterning a layer to form a gate electrode; and a step of selectively implanting an impurity using the gate electrode as a mask to form a second impurity-implanted semiconductor layer. Production method. 4. The method of manufacturing a field effect transistor according to claim 3, wherein in the step of forming the second impurity-implanted semiconductor layer, impurities are obliquely implanted at an angle with the gate electrode as a center. A method for manufacturing a field effect transistor, characterized in that