JPH03156933A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To execute a fine patterning operation in order to form a recess region by a method wherein, when the recess region is formed by laminating a resist layer between a first electrode and a second electrode, a spacer layer is laid between the electrodes. CONSTITUTION:A spacer layer 5 is laminated on a semiconductor active layer 2 on a semiconductor substrate; a resist layer 6 is laminated on the spacer layer 5 and its width is formed to be a desired size. The spacer layer 5 is removed by making use of the resist layer 6 as a mask in such a way that its width is by an arbitrary amount narrower than the width of the resist layer. An interval between a first electrode and a second electrode 3, 4 which are formed on the semiconductor active layer 2 is decided by the width of the resist layer 6; a width of a recess region is decided by the width of the spacer layer 5. Thereby, a fine gate can be patterned even at an arbitrary interval between a source and a drain, and a shape of a recess can be formed uniformly.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a method for manufacturing a semiconductor device.

(Prior Art) FIGS. 2(a) to 2(g) are cross-sectional views showing the main steps of a conventional method for manufacturing a semiconductor device having a multi-stage recess structure. In these figures, (1) is gallium arsenide (Ga
(2) is a semiconductor substrate (1
), (3) and (4) are train electrodes and source electrodes formed on the semiconductor active layer (2), and (5) is an insulating film such as a silicon nitride (SiN) film. Spacer layer, (12) is a resist layer laminated on spacer layer (5), (7) is a groove region formed in semiconductor active layer (2), (8) is a gate electrode, (81) is a gate electrode It is metal.

Next, a method for manufacturing a semiconductor device having a multi-stage recess structure will be described with reference to FIGS. 2(a) to 2(g).

First, as shown in FIG. 2(a), a train electrode (3) is placed on a semiconductor active layer (2) formed on a semiconductor substrate (1).
, after forming the source electrode (4), a spacer layer (
5) Sequentially stack resist layers (12). Next, as shown in FIG. 2(b), an opening is formed in the resist layer (12) by gate patterning, and an opening is formed in the spacer layer (5).
) is selectively removed by dry etching such as RIE. Next, as shown in FIG. 2(c), the semiconductor active layer (2) is etched using the spacer layer (5) as a mask to form a recess region (7). Next, the second
After side-etching the spacer layer (5) by a desired amount as shown in FIG. 2(d), the semiconductor active layer (2) is etched again to form a recessed area as shown in FIG. 2(e). The recessed area (7) is completed by widening and forming a stepped portion. Next, as shown in FIG. 2(f), a gate electrode metal (81) is laminated on the entire surface by vapor deposition or the like. Thereafter, as shown in FIG. 2(g), the unnecessary gate electrode metal (81) on the resist layer (12) is removed by a lift-off method.
is removed, and the resist layer (12) is further removed to form a gate electrode (8) made of a gate electrode metal (81) in the recess region (7).

(Problems to be Solved by the Invention) A conventional semiconductor device having a multi-stage recess structure is manufactured as described below, but it has the following problems.

Since the resist layer (12) between the source trains becomes thick, it is difficult to perform fine gate patterning. Also, if you try to narrow the source-train spacing, -layer patterning becomes difficult, and the gate length (Ng) increases.
cannot be shortened. Furthermore, since side etching of the spacer layer (5) is performed by wet etching, it is difficult to control the amount of etching. Therefore, the recess shape cannot be made uniform, causing variations in device performance.

This invention was made to solve the above problems, and even at any source train interval,
The object of the present invention is to provide a method for manufacturing a semiconductor device that allows fine gate patterning and uniform recess shape.

(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes stacking a spacer layer on a semiconductor active layer on a semiconductor substrate, stacking a resist layer on the spacer layer, and adjusting the width to a desired size. formed into;
Using the resist layer as a mask, the spacer layer is removed so that the spacer layer has a width narrower by an arbitrary amount than the width of the spacer layer, and first and second electrodes are formed on the semiconductor active layer according to the width of the resist layer. The width of the recessed region is determined by the width of the spacer layer.

[For production]

In the method for manufacturing a semiconductor device of the present invention, since the spacer layer is interposed between the first and second electrodes formed on the semiconductor active layer, a resist layer is laminated between the first and second electrodes and the recess is formed. When forming the region, the thickness of the resist layer on the spacer layer is reduced by the thickness of the spacer layer, so fine patterning for forming the recess region is performed in the first and second steps.
This is easily possible even if the spacing between the electrodes is narrowed. Furthermore, since the width of the spacer layer can be controlled accurately regardless of the width of the resist layer using the resist layer as a mask, the recess shape can be made uniform at any given first and second electrode spacing. can be achieved.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(k) are cross-sectional views showing the main steps of a method for manufacturing a semiconductor device having a multi-stage recess structure according to an embodiment of the present invention. In the figure, (6) is the first resist layer, (9) is the source/train electrode metal, (lO
) is the second resist layer, and the rest is the same as in FIG.

First, as shown in FIG. 1(a), a semiconductor (e.g. Ga
As) A semiconductor active layer (for example, n-GaAs with a thickness of 0.41 Lm) (2) formed on a substrate (1), a train electrode (3) and a source electrode (
4) Spacer layer (e.g. SiN, 5iON, 5iOz, etc.) with the same thickness as (e.g. o, sg■)
A first resist layer (for example, a positive resist layer having a thickness of 0.4 ru) (6) is formed on the first resist layer (6), which is patterned to form a source/train electrode. Here, the width of the first resist layer (6) (for example 4μ) determines the source-train spacing (Lso). Next, as shown in FIG. 1(b), the spacer layer (5) is etched using the resist layer (6) as a mask. At this time,
For etching, a dry etching method such as old E or RIBE is used, and the resist layer (6) is over-etched beyond the radius (L=o). Over-etched spacer layer (5
) width (for example, 2 p-m) (W) determines the recess width in forming a glue recess in a subsequent process. The width of this spacer layer (5) can be sufficiently controlled by using the tri-etching method.

Next, as shown in FIG. 1(C), a source/train electrode metal (9) is deposited over the entire surface by vapor deposition or the like to a thickness of, for example, 0.
Unnecessary source/train electrode metal (9) on the first resist layer (6) is stacked to a thickness of 51 Lm and removed by lift-off method.
As shown in FIG. 1(d), a train electrode (3) and a source electrode (4) made of the source/train electrode metal (9) are formed on the semiconductor active layer (2), as well as a source electrode (4) as shown in FIG. - Leave a spacer layer (5) between the trains. Next, as shown in FIG. 1(e), a second resist layer (for example, a positive resist layer with a thickness of 0.4 mm) (10) is laminated. Here, the second resist layer (10) is planarized by the presence of the spacer layer (5), and the thickness of the second resist layer (1o) is reduced in the region where gate patterning is to be performed. Next, as shown in FIG. 1(f), gate patterning is performed, but the second resist layer (10)
Since it is flattened and thinned, fine patterning becomes possible. After gate patterning, the spacer layer (5) is selectively etched away by dry etching such as (2)E. Next, as shown in FIG. 1(g), the semiconductor active layer (2) is etched to form a recess region (7) as in the conventional method. Thereafter, the entire spacer layer (5) is removed by etching as shown in FIG. 1(h). Next, as shown in FIG. 1(i), the semiconductor active layer (2) is etched again using the second resist layer (lO) after the removal of the spacer layer (5) as a mask to widen the recess area and , forming a step to complete the recess area (7). Subsequently, as shown in FIG. 1(j), a gate electrode metal layer (81) is formed by a vapor deposition method or the like, and then an unnecessary gate electrode metal layer on the second resist layer (10) is removed by a lift-off method. (81) and the second resist layer (10) are removed to form a gate electrode (81) consisting of the gate electrode metal layer (81) in the recess region (7) as shown in FIG. 1(k). ) to form.

〔Effect of the invention〕

As described above, according to the present invention, when forming a recess region by laminating a resist layer between the first and second electrodes, the spacer layer is interposed between the first and second electrodes. Since the thickness of the resist layer is reduced by the thickness of the spacer layer, fine patterning for forming recessed regions is possible. Furthermore, since the width of the spacer layer that determines the width of the recess region can be accurately controlled, the recess shape can be made uniform. Furthermore, the uniformity of these fine patterning and groove shapes is an arbitrary first step.
and a second electrode spacing.

[Brief explanation of the drawing]

1(a) to 1(k) are cross-sectional views showing the main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG.
1A to 1G are cross-sectional views showing main steps of a conventional method for manufacturing a semiconductor device. In each country, (1) is a semiconductor substrate, (2) is a semiconductor active layer, (3) and (4) are first and second electrodes, and (5) is a semiconductor active layer.
) is a spacer layer, (6) is a first resist layer, (7) a beam recess region, (8) is a third electrode, (9) is a first electrode metal layer, and (10) is a second resist layer. (8) is the second electrode metal layer. The same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (v
) gu”＋ ■ ■ ＼j く

Claims (1)

[Claims] (1) A first step of laminating a spacer layer on a semiconductor active layer formed on a semiconductor substrate; laminating a first resist layer on the spacer layer and patterning it to have a width of a desired size; a second step of forming the spacer layer using the first resist layer as a mask;
a third step of etching to make the width narrower by an arbitrary amount than the width of the resist layer; forming a first electrode metal layer on the first resist layer and the semiconductor active layer; a fourth step of removing the first electrode metal layer and the first resist layer on the first resist layer to form first and second electrodes facing each other with the spacer layer interposed; a fifth step of laminating a second resist layer between the first electrode and the second electrode and patterning the layer; selectively applying the spacer layer using the second resist layer as a mask; a sixth step of etching the semiconductor active layer to expose the semiconductor active layer, and then etching the semiconductor active layer using the spacer layer as a mask; removing all the spacer layer and masking the second resist layer; a seventh step of etching the semiconductor active layer again to form a recessed region; depositing a second electrode metal on the second resist layer and the recessed region; A method for manufacturing a semiconductor device, comprising: removing the second electrode metal and the second resist layer deposited on the resist layer to form a third electrode in the recess region.