JPH05299440A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05299440A
JPH05299440A JP7076391A JP7076391A JPH05299440A JP H05299440 A JPH05299440 A JP H05299440A JP 7076391 A JP7076391 A JP 7076391A JP 7076391 A JP7076391 A JP 7076391A JP H05299440 A JPH05299440 A JP H05299440A
Authority
JP
Japan
Prior art keywords
photoresist
insulating film
gate electrode
spacer layer
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7076391A
Other languages
Japanese (ja)
Inventor
Nobuyuki Kasai
信之 笠井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7076391A priority Critical patent/JPH05299440A/en
Publication of JPH05299440A publication Critical patent/JPH05299440A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain the manufacturing method of a semiconductor device which does not generate parasitic capacity and has simplified manufacture process. CONSTITUTION:A spacer layer 9 consisting of an insulating film is provided on the semiconductor active layer 2 on a semiconductor substrate 1, and photoresist 10 is applied, and a gate is patterned, and then with this photoresist 10 as a mask, the spacer layer 9 is etched off, and next an insulating film 11 is stacked all over the surface. Furthermore, a T-shaped photoresist 7 is patterned hereon, and the insulating film 11 is etched, and then a recessed region 4 is made by the etching by self alignment using this spacer layer 9 as a mask, and further a T-shaped gate electrode 8 is made and lifted off, whereby it is so arranged that the insulating film, etc., in contact with the recessed region 4 and the gate electrode 8 does not exist.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、特に電界効果トランジスタなどのゲ−ト電極の
形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a gate electrode such as a field effect transistor.

【0002】[0002]

【従来の技術】図3(a)〜(e)および図4(a),
(b)は従来の半導体装置の製造方法をその製造工程順
に示した断面図である。これらの図において、1は半導
体基板、2はこの半導体基板1上に形成された半導体活
性層、3はフォトレジスト、4は前記半導体活性層2に
形成されたリセス領域、5は窒化シリコン等からなる絶
縁膜、6,7はフォトレジスト、8は前記リセス領域4
内に形成されたゲ−ト電極、80はゲ−ト電極金属であ
る。
2. Description of the Related Art FIGS. 3 (a) to 3 (e) and FIG. 4 (a),
(B) is sectional drawing which showed the manufacturing method of the conventional semiconductor device in order of the manufacturing process. In these figures, 1 is a semiconductor substrate, 2 is a semiconductor active layer formed on the semiconductor substrate 1, 3 is a photoresist, 4 is a recess region formed in the semiconductor active layer 2, and 5 is silicon nitride or the like. Insulating film, 6 and 7 are photoresists, 8 is the recessed region 4
The gate electrode 80 is formed inside, and 80 is a gate electrode metal.

【0003】次に、図3および図4によりT型形状のの
ゲ−ト電極を有する半導体装置の製造工程について説明
する。まず、図3(a)に示すように、半導体基板1上
に形成された半導体活性層2上全面にフォトレジスト3
を塗布した後、パタ−ニングが行われる。このフォトレ
ジスト3をマスクに半導体活性層2を所望の量だけエッ
チングし、リセス領域4を形成する。次に、図3(b)
に示すように、フォトレジスト3を除去した後、窒化シ
リコン等からなる絶縁膜5をプラズマCVD等により
0.3μm程度の厚さで形成する。次に、図3(c)に
示すように、絶縁膜5上にフォトレジスト6を塗布し、
ゲ−ト形成のためのパタ−ニングを行う。この時、図示
したように、フォトレジスト6のパタ−ニングによる開
口部はリセス領域4内に入るように形成する。次に、図
3(d)に示すように、フォトレジスト6をマスクにし
て絶縁膜5をエッチングする。エッチングはRIE(反
応性イオンエッチング)などによる異方性エッチングを
行う。この場合、絶縁膜5の開口幅lがゲ−ト長を決め
ることになる。次に、図3(e)に示すように、フォト
レジスト6を除去した後、新たなフォトレジスト7を塗
布し、パタ−ニングを行う。フォトレジスト7のパタ−
ニングはT型形状を得るために絶縁膜5の開口幅lより
広く開口する。ここで、レジストプロファイルはリフト
オフ性向上のため、逆テ−パ−になっている方が望まし
い。次に、図4(a)に示すように、ゲ−ト電極金属8
0を真空蒸着等により被着する。さらに、図4(b)に
示すように、リフトオフによりフォトレジスト7および
フォトレジスト7上の不要のゲ−ト電極金属80を除去
し、T型形状のゲ−ト電極8を有する半導体装置が形成
される。図4(b)では、絶縁膜5を除去していない場
合を示したが、図5に示すように、ゲ−ト電極8に接す
る部分だけ絶縁膜5を残したり、図6に示すように、全
て除去する場合もある。絶縁膜5の除去は、RIEやプ
ラズマエッチング等で行う。
Next, a manufacturing process of a semiconductor device having a T-shaped gate electrode will be described with reference to FIGS. First, as shown in FIG. 3A, a photoresist 3 is formed on the entire surface of the semiconductor active layer 2 formed on the semiconductor substrate 1.
After applying, patterning is performed. Using the photoresist 3 as a mask, the semiconductor active layer 2 is etched by a desired amount to form a recess region 4. Next, FIG. 3 (b)
After removing the photoresist 3, an insulating film 5 made of silicon nitride or the like is formed to a thickness of about 0.3 μm by plasma CVD or the like, as shown in FIG. Next, as shown in FIG. 3C, a photoresist 6 is applied on the insulating film 5,
Patterning for gate formation is performed. At this time, as shown in the figure, the opening of the photoresist 6 by patterning is formed so as to enter the recess region 4. Next, as shown in FIG. 3D, the insulating film 5 is etched using the photoresist 6 as a mask. The etching is anisotropic etching such as RIE (reactive ion etching). In this case, the opening width 1 of the insulating film 5 determines the gate length. Next, as shown in FIG. 3 (e), after removing the photoresist 6, a new photoresist 7 is applied and patterning is performed. Pattern of photoresist 7
The opening is wider than the opening width 1 of the insulating film 5 to obtain the T-shape. Here, it is desirable that the resist profile has a reverse taper in order to improve the lift-off property. Next, as shown in FIG. 4A, the gate electrode metal 8
0 is deposited by vacuum evaporation or the like. Further, as shown in FIG. 4B, the photoresist 7 and the unnecessary gate electrode metal 80 on the photoresist 7 are removed by lift-off to form a semiconductor device having a T-shaped gate electrode 8. To be done. Although FIG. 4B shows the case where the insulating film 5 is not removed, as shown in FIG. 5, the insulating film 5 is left only in the portion in contact with the gate electrode 8, or as shown in FIG. , All may be removed. The insulating film 5 is removed by RIE, plasma etching or the like.

【0004】[0004]

【発明が解決しようとする課題】従来の半導体装置は以
上のように形成されるが、リセス領域4内にゲ−トパタ
−ニングするのが不安定であり、かつT型形状のゲ−ト
電極8と半導体活性層2が絶縁膜5を介して余分な寄生
容量を持つことになる。余分な寄生容量を持たせないよ
うに絶縁膜5を除去してしまう場合、リセス領域4での
ドライエッチングによるダメ−ジがデバイス特性へ影響
を与えることが懸念されるなどの問題点があった。
Although the conventional semiconductor device is formed as described above, the gate pattern in the recess region 4 is unstable and the gate electrode is T-shaped. 8 and the semiconductor active layer 2 have an extra parasitic capacitance via the insulating film 5. When the insulating film 5 is removed so as not to have an extra parasitic capacitance, there is a problem that damage due to dry etching in the recess region 4 may affect device characteristics. ..

【0005】本発明は、上記のような問題点を解消する
ためになされたもので、ゲ−トパタ−ニングに対しセル
フアラインでリセス領域が形成できるとともに、余分な
寄生容量が発生しないうえ、リセス領域にドライエッチ
ングダメ−ジが入る工程がない半導体装置の製造方法を
得ることを目的とする。
The present invention has been made in order to solve the above-mentioned problems, and it is possible to form a recess area by self-alignment with respect to gate patterning and to prevent an extra parasitic capacitance from occurring. It is an object of the present invention to obtain a method for manufacturing a semiconductor device, which does not have a step of entering a dry etching damage into a region.

【0006】[0006]

【課題を解決するための手段】本発明に係る半導体装置
の製造方法は、半導体基板上の半導体活性層上に絶縁膜
からなるスペ−サ層を設け、フォトレジストを塗布して
ゲ−トパタ−ニングした後、このフォトレジストをマス
クにして前記スペ−サ層をエッチング除去し、全面に絶
縁膜を積層した後、レジストを塗布してT型形状に上部
ゲ−トパタ−ニングし、前記スペ−サ層をマスクとした
エッチングによりリセス領域を形成するようにし、さら
に、T型形状のゲ−ト電極の形成に際し、リフトオフ後
にはリセス領域およびゲ−ト電極に接する絶縁膜がない
ようにするものである。
According to the method of manufacturing a semiconductor device of the present invention, a spacer layer made of an insulating film is provided on a semiconductor active layer on a semiconductor substrate, and a photoresist is applied to the gate pattern. After this, the photoresist layer is used as a mask to etch away the spacer layer, an insulating film is laminated on the entire surface, a resist is applied, and an upper gate pattern is formed into a T shape to form the spacer. Recess regions are formed by etching using the mask layer as a mask, and when forming a T-shaped gate electrode, there is no insulating film in contact with the recess region and the gate electrode after lift-off. Is.

【0007】[0007]

【作用】本発明においては、スペ−サ層を介在させ、ス
ペ−サ層をマスクとしてリセス領域を形成するため、ゲ
−トパタ−ニングに対しセルフアラインでリセス領域を
形成できるとともに、ゲ−ト電極形成ではリセス領域お
よびゲ−ト電極に接する絶縁膜がないため、余分な寄生
容量の発生がなく、絶縁膜除去の工程も不要なので、ド
ライエッチングダメ−ジの心配がない。
In the present invention, since the recess region is formed by interposing the spacer layer and using the spacer layer as a mask, the recess region can be formed by self-alignment with respect to the gate patterning and the gate region can be formed. In the electrode formation, since there is no insulating film in contact with the recess region and the gate electrode, no extra parasitic capacitance is generated and the step of removing the insulating film is unnecessary, so that there is no fear of dry etching damage.

【0008】[0008]

【実施例】以下、本発明の一実施例を図について説明す
る。図1(a)〜(d)および図2(a)〜(d)は本
発明の半導体装置の製造方法の一実施例を示す工程断面
図である。図1および図2において、1は半導体基板、
2はこの半導体基板1上に形成された半導体活性層、4
はこの半導体活性層2に形成されたリセス領域、7はフ
ォトレジスト、8はT型形状のゲ−ト電極、9はスペ−
サ層、10はフォトレジスト、11は絶縁膜、80はゲ
−ト電極金属である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1A to 1D and 2A to 2D are process cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device of the present invention. 1 and 2, 1 is a semiconductor substrate,
2 is a semiconductor active layer formed on the semiconductor substrate 1, 4
Is a recess region formed in the semiconductor active layer 2, 7 is a photoresist, 8 is a T-shaped gate electrode, and 9 is a space.
10 is a photoresist, 11 is an insulating film, and 80 is a gate electrode metal.

【0009】次に、本発明による半導体装置の製造工程
について説明する。まず、図1(a)に示すように、半
導体基板1上に半導体活性層2を形成し、この半導体活
性層2上に窒化シリコン等からなるスペ−サ層9を0.
1μm程度積層した後、フォトレジスト10を塗布し、
ゲ−トパタ−ニングを行う。次に、図1(b)に示すよ
うに、フォトレジスト10をマスクにしてスペ−サ層9
をエッチング除去する。この時、エッチングはRIE等
による異方性エッチングを行う。次に、図1(c)に示
すように、スペ−サ層9とは膜質の異なる絶縁膜11を
全面に積層する。絶縁膜11の役割りは次工程において
塗布するフォトレジストがゲ−トパタ−ニングを施した
フォトレジスト10とミキシングするのを抑制すること
である。次に、図1(d)に示すように、絶縁膜11上
にフォトレジスト7を塗布し、T型形状の上部を決める
パタ−ニングを行う。レジストプロファイルは従来と同
様、逆テ−パ−になる方が望ましい。次に、図2(a)
に示すように、フォトレジスト7をマスクにして絶縁膜
11をエッチングする。この時のエッチングはウエッ
ト,ドライどちらの方法でも構わない。次に、図2
(b)に示すように、FET耐圧向上を考慮し、必要な
量だけスペ−サ層9をサイドエッチングした後、スペ−
サ層9をマスクにして半導体活性層2をエッチングし、
リセス領域4を形成する。ここで、リセス領域4はゲ−
トパタ−ニングに対しセルフアラインで形成されるの
で、従来のようなマスク合わせの不安定が解消される。
次に、図2(c)に示すように、ゲ−ト電極金属80を
真空蒸着等により被着した後、リフトオフによりフォト
レジスト7,10および絶縁膜11,フォトレジスト7
上の不要のゲ−ト電極金属80を除去し、図2(d)に
示すようなT型形状のゲ−ト電極8を有する半導体装置
が形成される。
Next, a manufacturing process of the semiconductor device according to the present invention will be described. First, as shown in FIG. 1A, a semiconductor active layer 2 is formed on a semiconductor substrate 1, and a spacer layer 9 made of silicon nitride or the like is formed on the semiconductor active layer 2.
After stacking about 1 μm, a photoresist 10 is applied,
Perform gate patterning. Next, as shown in FIG. 1B, the spacer layer 9 is formed using the photoresist 10 as a mask.
Are removed by etching. At this time, the etching is anisotropic etching such as RIE. Next, as shown in FIG. 1C, an insulating film 11 having a film quality different from that of the spacer layer 9 is laminated on the entire surface. The role of the insulating film 11 is to prevent the photoresist applied in the next step from mixing with the photoresist 10 which has been subjected to the gate patterning. Next, as shown in FIG. 1D, a photoresist 7 is applied on the insulating film 11 and patterned to determine the upper portion of the T-shape. As in the conventional case, the resist profile is preferably reverse taper. Next, FIG. 2 (a)
As shown in, the insulating film 11 is etched using the photoresist 7 as a mask. The etching at this time may be either wet or dry. Next, FIG.
As shown in (b), the spacer layer 9 is side-etched by a necessary amount in consideration of the improvement of the FET breakdown voltage, and then the spacer is removed.
The semiconductor active layer 2 is etched using the mask layer 9 as a mask,
The recess region 4 is formed. Here, the recess area 4 is
Since it is formed by self-alignment with respect to the top patterning, the instability of mask alignment as in the conventional case is eliminated.
Next, as shown in FIG. 2C, a gate electrode metal 80 is deposited by vacuum evaporation or the like, and then lifted off to remove the photoresists 7, 10 and the insulating film 11, the photoresist 7.
By removing the unnecessary unnecessary gate electrode metal 80, a semiconductor device having a T-shaped gate electrode 8 as shown in FIG. 2D is formed.

【0010】[0010]

【発明の効果】以上説明したように、本発明によれば、
ゲ−トパタ−ニングするフォトレジストの下にスペ−サ
層を介在させることで、ゲ−トパタ−ニングに対しセル
フアラインでリセス領域が形成できるようになるうえ、
リセス領域およびゲ−ト電極に接する絶縁膜等がないた
め、余分な寄生容量の発生もなくなり、絶縁膜除去の工
程も不要となり、ドライエッチングダメ−ジもなくなる
等の効果がある。
As described above, according to the present invention,
By interposing a spacer layer under the photoresist for gate patterning, it becomes possible to form a recess region by self-alignment with respect to the gate patterning.
Since there is no insulating film or the like in contact with the recess region and the gate electrode, extra parasitic capacitance is not generated, the step of removing the insulating film is not required, and dry etching damage is also eliminated.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の製造方法の一実施例を示
す工程断面図である。
FIG. 1 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device of the present invention.

【図2】図1に引き続く本発明の半導体装置の製造工程
を示す断面図である。
FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device of the present invention, which is subsequent to FIG.

【図3】従来の半導体装置の製造方法を示す工程断面図
である。
3A to 3D are process cross-sectional views showing a conventional method for manufacturing a semiconductor device.

【図4】図3に引き続く従来の半導体装置の製造方法を
示す工程断面図である。
FIG. 4 is a process cross-sectional view showing the method of manufacturing the conventional semiconductor device, following FIG. 3;

【図5】従来の他の半導体装置を示す断面図である。FIG. 5 is a cross-sectional view showing another conventional semiconductor device.

【図6】従来のさらに他の半導体装置を示す断面図であ
る。
FIG. 6 is a sectional view showing still another conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 半導体活性層 4 リセス領域 7 フォトレジスト 8 ゲ−ト電極 9 スペ−サ層 10 フォトレジスト 11 絶縁膜 80 ゲ−ト電極金属 1 Semiconductor Substrate 2 Semiconductor Active Layer 4 Recess Region 7 Photoresist 8 Gate Electrode 9 Spacer Layer 10 Photoresist 11 Insulating Film 80 Gate Electrode Metal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に形成された半導体活性層上
に絶縁膜からなるスペ−サ層を形成する工程,前記スペ
−サ層上にフォトレジストを塗布した後、ゲ−トパタ−
ニングする工程,ゲ−トパタ−ニングされたフォトレジ
ストをマスクにして前記スペ−サ層をエッチングする工
程,全面に絶縁膜を積層した後、前記フォトレジストと
異なるフォトレジストを塗布しT型形状に上部ゲ−トパ
タ−ニングを行う工程,前記T型形状のフォトレジスト
をマスクにして前記絶縁膜をエッチングする工程,前記
スペ−サ層を所望の量だけサイドエッチングした後、こ
のスペ−サ層をマスクとして前記半導体活性層をエッチ
ングしリセス領域を形成する工程,全面にゲ−ト電極金
属を被着する工程,リフトオフにより前記フォトレジス
ト,絶縁膜およびフォトレジスト上の不要のゲ−ト電極
金属を除去し、T型形状のゲ−ト電極を形成する工程と
を有することを特徴とする半導体装置の製造方法。
1. A step of forming a spacer layer made of an insulating film on a semiconductor active layer formed on a semiconductor substrate, coating a photoresist on the spacer layer, and then forming a gate pattern.
Process, a process of etching the spacer layer using the gate patterned photoresist as a mask, a layer of an insulating film is laminated on the entire surface, and then a photoresist different from the photoresist is applied to form a T-shape. The step of performing the upper gate patterning, the step of etching the insulating film using the T-shaped photoresist as a mask, the side etching of the spacer layer by a desired amount, and then the spacer layer is removed. The step of etching the semiconductor active layer as a mask to form a recess region, the step of depositing a gate electrode metal on the entire surface, and the unnecessary gate electrode metal on the photoresist, insulating film and photoresist by lift-off. A step of removing the gate electrode to form a T-shaped gate electrode.
JP7076391A 1991-04-03 1991-04-03 Manufacture of semiconductor device Pending JPH05299440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7076391A JPH05299440A (en) 1991-04-03 1991-04-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7076391A JPH05299440A (en) 1991-04-03 1991-04-03 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05299440A true JPH05299440A (en) 1993-11-12

Family

ID=13440877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7076391A Pending JPH05299440A (en) 1991-04-03 1991-04-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05299440A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08195404A (en) * 1995-01-13 1996-07-30 Nec Corp Minute t-shaped electrode and its formation method
US5583063A (en) * 1993-11-30 1996-12-10 Nec Corporation Method of forming T-shaped, cross-sectional pattern using two layered masks
JPH0964064A (en) * 1995-08-24 1997-03-07 Nec Corp Manufacture of semiconductor device
CN100446185C (en) * 2005-11-29 2008-12-24 韩国电子通信研究院 Manufacturing method of T or gamma gate electrode

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5583063A (en) * 1993-11-30 1996-12-10 Nec Corporation Method of forming T-shaped, cross-sectional pattern using two layered masks
JPH08195404A (en) * 1995-01-13 1996-07-30 Nec Corp Minute t-shaped electrode and its formation method
JPH0964064A (en) * 1995-08-24 1997-03-07 Nec Corp Manufacture of semiconductor device
CN100446185C (en) * 2005-11-29 2008-12-24 韩国电子通信研究院 Manufacturing method of T or gamma gate electrode

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