JPH0629406A - Contact structure and its manufacture - Google Patents

Abstract

PURPOSE:To enhance breakdown voltage between conductive layers constituting a contact hole and wiring layer formed inside the contact hole. CONSTITUTION:A contact structure consisting of the second conductive layer and an offset insulating film 4, both of which are formed successively above the first conductive layer 1, a contact hole 6 opened through the second conductive layer and the offset insulating film 4, an insulating side wall formed on the side wall of the contact hole, and a wiring layer 10 self-aligned in the contact hole 6, wherein a projected section 9b of said wall is formed in a section of the second conductive layer right under the offset insulating film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact structure and a contact forming method, and more particularly to a contact structure and a contact forming method for forming a contact in a contact hole by self-alignment.

[0002]

2. Description of the Related Art As a method for making electrical contact with a silicon substrate or a lower layer wiring in manufacturing a semiconductor device such as a MOS transistor, a self aligned contact (Self Aligned Contac
t: SAC) formation methods are known. FIG. 3 shows the conventional S
It is process sectional drawing which shows the typical formation method of AC.

A conventional SAC forming method is shown in FIG.
3, a gate oxide film 2, a gate polysilicon (Poly-Si) film 3, and an offset SiO ₂ film 4 are sequentially formed on a silicon (Si) substrate 1, and then a photoresist is formed as shown in FIG. The (PR) film is patterned by a lithography technique to form a resist pattern 5, which is used as a mask for the offset SiO ₂ film 4 and the gate Po.
The ly-Si film 3 is sequentially removed by etching by the RIE (reactive ion etching) method to form the contact hole 6. By this RIE, the thin gate oxide film 2 in the opening is also removed. Therefore, after removing the resist pattern 5 as shown in FIG. 3C, the Si in the opening is thermally oxidized.
The surface of the substrate 1 and the side walls of the gate Poly-Si film 3 are oxidized to form an oxide film 7 in a U shape. Next, SiO ₂ is deposited by a CVD (chemical vapor deposition) method to form SiO ₂
The layer 8 is formed, and the SiO ₂ sidewall (side wall) 8a is formed in the opening by etching back by RIE from above (FIG. 3D).

Next, after a diffusion layer is formed by impurity ion implantation, aluminum (Al) or Poly-S is used.
i is deposited on the entire surface and a wiring layer 10 for self-aligned contact is formed by patterning (FIG. 3E).

In the conventional self-aligned contact forming method described above, since the contact portion is automatically formed at a portion separated from the edge of the gate Poly-Si film 3 by the width of the SiO ₂ side wall 8a, there is a problem such as mask misalignment. In addition, it is a method suitable for miniaturization of contacts.

[0006]

In the conventional contact formation described above, an electric field is likely to be concentrated at the shoulder corner portion A of the gate Poly-Si film 3 shown in FIG. Is not so far away, so the part A
Thus, the breakdown voltage between the gate Poly-Si film 3 and the wiring layer 10 decreases.

Therefore, it is an object of the present invention to provide a contact structure and a contact forming method for improving the breakdown voltage between a conductive layer forming a contact hole and a wiring layer formed in the contact hole.

[0008]

According to the present invention, the above-mentioned problem is solved by providing a second conductive layer and an offset insulating film, which are sequentially formed above the first conductive layer, in the second conductive layer and the offset insulating film. A contact hole formed through the contact hole, an insulating material side wall provided on the side surface of the contact hole, and a wiring layer provided in the contact hole in a self-aligned manner. The contact structure is characterized in that a protrusion of the insulating material side wall is provided at a conductive layer portion.

Further, according to the present invention, there is provided the above-mentioned object, wherein a step of sequentially forming a second conductive layer and an offset insulating film above the first conductive layer, and a step of forming a contact hole upper part in the offset insulating film is performed. Exposing the second conductive layer, forming a hole in the second conductive layer directly under the offset insulating film by isotropically etching the second conductive layer using the offset insulating film as a mask, and the offset By anisotropically etching the insulating film as a mask to form a lower portion of the contact hole, forming an insulating material side wall to fill the hole in the contact hole, and depositing a conductive material on the entire surface and patterning And a contact forming method in which a wiring layer is formed in the contact hole in a self-aligning manner.

[0010]

According to the present invention, since the corner portion of the shoulder of the second conductive layer 3 forming the contact hole 6 (immediately below the offset insulating film 4) is removed to form the insulating material side wall 9b, the electric field is concentrated. Can be relaxed, and the distance between the second conductive layer 3 and the wiring layer 10 can be increased.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of the contact structure of the present invention.

In the contact structure shown in FIG. 1, the wiring layer 10 is formed in self-alignment on the silicon (Si) substrate 1 as the first conductive layer, and the gate polysilicon (Poly-Si) on the Si substrate 1 is formed. They are separated by a SiO ₂ sidewall 9 a formed between the film 3 and the wiring layer 10. The SiO ₂ sidewall 9a forms the electric field concentration relaxation side wall portion 9b as a protruding portion of the side wall at the corner of the shoulder of the gate Poly-Si film 3 to literally relax the concentration of the electric field and improve the breakdown voltage. ing. Offset Si is formed on the gate Poly-Si film 3.
An O ₂ film (insulating film) 4 is provided to serve as an offset material at the time of etch back.

Next, a method of forming the contact structure shown in FIG. 1 will be described.

FIG. 2 is a cross-sectional view showing the process, showing a process following the process of FIG. 3 (a) which is a conventional process.

In this embodiment, first, as in the conventional case, FIG.
A gate oxide film 2 on a Si substrate 1 as a first conductive layer,
A gate Poly-Si film 3 as a second conductive layer and an offset SiO ₂ film (insulating film) 4 are sequentially formed.

In this embodiment, the gate oxide film 2 has a thickness of 20.
nm, the thickness of the gate Poly-Si film 3 is 200 nm,
The thickness of the offset SiO ₂ film 4 was set to 300 nm.

Next, a resist having a thickness of about 1 μm is formed on the offset SiO ₂ film 4, a resist pattern 5 having an opening having a width of about 0.6 μm is formed, and the resist pattern 5 is used as a mask in FIG. As shown in a), the offset SiO ₂ film 4 is removed by anisotropic etching such as RIE (reactive ion etching) using CH ₄ / H ₂ gas to form a contact hole 6.

Next, as shown in FIG. 2B, the gate Pol
1/4 to 1/2 of the thickness of the y-Si film 3 (50 nm to 10 nm
The thickness of 0 nm) is removed by isotropic etching such as plasma etching with CH ₄ + O ₂ . Since this etching is isotropic, it has a boat shape in which the portion directly below the offset SiO ₂ film 4 in which the contact hole is formed is also removed. Reference numeral 11 is an isotropic etching removed portion removed by this etching.

In order to promote the isotropic etching of the gate Poly-Si film 3 in the lateral direction (immediately below the offset SiO ₂ film 4) and enhance the effect of removing the corners of the film, the gate Poly-Si film 3 is formed. After forming by the CVD method, ion implantation of silicon (Si), phosphorus (P) or the like is performed to form a gate P
A damaged layer may be formed on the surface of the poly-Si film 3, or the offset SiO ₂ film 4 may be etched to form the gate P.
After exposing the poly-Si film 3, the gate Poly-Si immediately below the offset SiO ₂ film 4 is formed by oblique ion implantation.
A damaged layer may be formed on the film 3.

Next, as shown in FIG. 2C, RI is used with the resist pattern 5 and the offset SiO ₂ film 4 as a mask.
The remaining gate Poly-Si film 3 and the contaminated gate oxide film 2 are removed by E.

Next, after the resist is peeled and removed, as shown in FIG.
The gate Poly-Si film 3 is thermally oxidized as shown in FIG.
And after forming the oxide film 7 on the Si substrate 1, low pressure CVD
SiO on the whole surface by the method₂Form the layer 9. At this time
SiO2₂Isotropic etching removal of horizontal holes directly under the film 4
SiO in the part 11₂Is accumulated and the electric field concentration side is relaxed
The wall portion 9b is formed. After that, as shown in FIG.
Similarly, by RIE, SiO ₂Layer 9 from above
Etching (etch back), SiO₂Sidewall
(Sidewall) 9a is formed.

Then, a metal such as aluminum (Al) is deposited on the entire surface from above and patterned to form the wiring layer 10 in a self-aligned manner (self-aligned) (FIG. 1). Further, in the above-mentioned embodiment, the target to be contacted is the Si substrate, but it may be a conductive layer such as Poly-Si.

[0024]

As described above, according to the present invention, the concentration of the electric field during operation of the semiconductor device can be alleviated, and the distance between the second conductive layer 3 and the wiring layer 10 can be increased. The withstand voltage in the meantime can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a contact structure of the present invention.

FIG. 2 is a process sectional view for forming the embodiment of the present invention.

FIG. 3 is a process sectional view showing a typical method for forming a conventional self-aligned contact (SAC).

[Explanation of symbols]

1 Silicon (Si) Substrate (First Conductive Layer) 2 Gate Oxide Film 3 Gate Polysilicon (Poly-Si) Film (Second Conductive Layer) 4 Offset SiO ₂ Film (Insulating Film) 5 Resist Pattern 6 Contact Hole 7 Oxide Film 8, 9 SiO ₂ layer 8a, 9a SiO ₂ sidewall (insulating material side wall) 9b electric field concentration relaxing side wall portion (side wall protrusion) 10 wiring layer 11 isotropic etching removal portion (hole)

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] June 2, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art As a method for making electrical contact with a silicon substrate or a lower layer wiring in manufacturing a semiconductor device such as a MOS transistor, a self aligned contact (Self Aligned Contac
t: SAC) formation methods are known. FIG. 4 shows the conventional S
It is process sectional drawing which shows the typical formation method of AC.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

A conventional SAC forming method is as shown in FIG.
, A gate oxide film 2, a gate polysilicon (Poly-Si) film 3, and an offset SiO ₂ film 4 are sequentially formed on a silicon (Si) substrate 1, and then a photoresist is formed as shown in FIG. 4 (b). The (PR) film is patterned by a lithography technique to form a resist pattern 5, which is used as a mask for the offset SiO ₂ film 4 and the gate Po.
The ly-Si film 3 is sequentially removed by etching by the RIE (reactive ion etching) method to form the contact hole 6. Since this RIE also removes the thin gate oxide film 2 in the opening, the resist pattern 5 is removed as shown in FIG.
The surface of the substrate 1 and the side walls of the gate Poly-Si film 3 are oxidized to form an oxide film 7 in a U shape. Next, SiO ₂ is deposited by a CVD (chemical vapor deposition) method to form SiO ₂
The layer 8 is formed, and the SiO ₂ sidewall (side wall) 8a is formed in the opening by etching back by RIE from above (FIG. 5B).

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

Next, after a diffusion layer is formed by impurity ion implantation, aluminum (Al) or Poly-S is used.
i is deposited on the entire surface, and the wiring layer 10 of the self-aligned contact is formed by patterning (FIG. 5C).

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

[0006]

In the conventional contact formation described above, the electric field is likely to concentrate at the shoulder corner portion A of the gate Poly-Si film 3 shown in FIG. Is not so far away, so the part A
Thus, the breakdown voltage between the gate Poly-Si film 3 and the wiring layer 10 decreases.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

2 and 3 are cross-sectional views showing the process, showing a process subsequent to the conventional process of FIG. 4 (a).

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

In this embodiment, first, as in the conventional case, FIG.
A gate oxide film 2 on a Si substrate 1 as a first conductive layer,
A gate Poly-Si film 3 as a second conductive layer and an offset SiO ₂ film (insulating film) 4 are sequentially formed.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

Next, as shown in FIG. 3A, RI is used with the resist pattern 5 and the offset SiO ₂ film 4 as a mask.
The remaining gate Poly-Si film 3 and the contaminated gate oxide film 2 are removed by E.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

Next, after peeling and removing the resist, FIG.
The gate Poly-Si film 3 is thermally oxidized as shown in FIG.
And after forming the oxide film 7 on the Si substrate 1, low pressure CVD
SiO on the whole surface by the method₂Form the layer 9. At this time
SiO2₂Isotropic etching removal of horizontal holes directly under the film 4
SiO in the part 11₂Is accumulated and the electric field concentration side is relaxed
The wall portion 9b is formed. After that, as shown in FIG.
Similarly, by RIE, SiO ₂Layer 9 from above
Etching (etch back), SiO₂Sidewall
(Sidewall) 9a is formed. ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] September 2, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a contact structure of the present invention.

FIG. 2 is a sectional view of a first half process for forming the embodiment of the present invention.

FIG. 3 is a sectional view of a second half process for forming the embodiment of the present invention.

FIG. 4 is a first-half process sectional view showing a typical method for forming a conventional self-aligned contact (SAC).

FIG. 5 is a second-half process sectional view showing a typical method for forming a conventional self-aligned contact (SAC).

[Description of Reference Signs] 1 silicon (Si) substrate (first conductive layer) 2 gate oxide film 3 gate polysilicon (Poly-Si) film (second conductive layer) 4 offset SiO ₂ film (insulating film) 5 resist pattern 6 Contact hole 7 Oxide film 8,9 SiO ₂ layer 8a, 9a SiO ₂ Side wall (side wall of insulating material) 9b Side wall portion for relaxing electric field concentration (side wall protrusion) 10 Wiring layer 11 Isotropic etching removal portion (hole)

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 3]

[Figure 4]

[Figure 5]

Claims (2)

[Claims] 1. A contact hole formed in a second conductive layer and an offset insulating film, which are sequentially formed above the first conductive layer, through the second conductive layer and the offset insulating film,
In a contact structure including an insulating material sidewall provided on the side surface of the contact hole and a wiring layer provided in the contact hole in a self-aligning manner, the insulating material sidewall is provided at a second conductive layer portion immediately below the offset insulating film. The contact structure is characterized in that a protrusion is provided. 2. A step of sequentially forming a second conductive layer and an offset insulating film above the first conductive layer, a step of forming a contact hole upper part in the offset insulating film to expose the second conductive layer, Isotropically etching the second conductive layer using the offset insulating film as a mask to form a hole in the second conductive layer immediately below the offset insulating film; anisotropically using the offset insulating film as a mask Self-aligning in the contact hole by performing a conductive etching to form a lower portion of the contact hole, forming an insulating material sidewall filling the hole in the contact hole, and depositing a conductive material on the entire surface and patterning. A method for forming a contact, which comprises the step of forming a wiring layer selectively.