JPH03278543A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To form a fine gate whose size controllability is excellent and whose gate resistance is low by a method wherein a sidewall film is formed of an insulating film, the upper part of the sidewall film is exposed by a flattening operation and an etchingback operation, a selective etching operation is executed and a substratum gate metal is processed while an Au-plated part grown on an etching region part of the sidewall film is used as a mask. CONSTITUTION:A first metal layer 2 to be used as a gate metal and a second metal layer 3 for Au-diffusion prevention use are applied sequentially on the main surface of a semiconductor substrate 1; a first insulating film 5 is grown on them; the insulating film 5 is anisotropically dry-etched selectively; the vertical difference in level of the insulating film is formed. Then, a second insulating film 7 is grown on the whole surface; the insulating film 7 is anisotropically dry-etched; a second insulating film 7' is left on the side of the difference in level. Then, an organic material 6' having a flattening characteristic is coated and flattened; the organic material 6' and the insulating film 5 are etched by an anisotropic dry-etching operation until the upper part of the insulating film 7' is exposed. Then, the residual part of the insulating film 7' is removed; an Au-plated part 8 is grown in its removed part; the insulating film 5 and the organic material 6' are removed; after that, the metal layers 4, 2 are removed by making use of the Au-plated part 8 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor, and particularly to a method for manufacturing a fine gate having excellent gate length controllability and low gate resistance.

[Conventional technology]

Shortening the gate length is an essential condition for improving device characteristics. The main process that determines this is lithography, and technological developments to improve resolution, such as shortening exposure wavelengths including electron beam exposure, are actively being carried out in various places.

However, the current lithography technology is still unstable when it comes to gate formation at a level of, for example, ~0.3 μm or less, and a fine gate length control technology that does not rely on lithography is expected. Sidewall film formation technology using anisotropic dry etching is a well-known technology, for example, as shown in Fig. 2(a).
As shown in ~(d), a 5in2 film 7 is formed so that its edge is located at the gate formation area of the semiconductor substrate 1, WSi2 is formed covering the edge to become a gate electrode, and then etched by anisotropic dry etching. It is considered that the WSi2 is etched and left only at the ends, and then the 5iOz film 7 is removed to form a gate. Regarding dimensional control at the ~0.3 μm level, with current technology, film thickness control using insulating film or metal growth technology, that is, longitudinal dimensional control, is much more accurate than plane patterning using lithography, that is, lateral dimensional control. Therefore, it is true that the gate formation method shown in Figures 2 (a) to (d) can form fine gates with higher accuracy than the gate formation method using normal lithography because the gate length is almost determined by the thickness of the grown metal film. Can be formed.

[Problem to be solved by the invention]

However, in the conventional technology described above, the film remaining as the side wall,
In other words, it is assumed that the gate metal side is processed almost completely vertically, and heat-resistant metals such as WSi, for example, CF
4. When a gas such as SFs is used, etching is performed mainly by reaction with the F* radical component, and complete anisotropy is achieved without the large need for assistance from ions such as CF3'' as seen in SiO2 etching. Therefore, it is difficult to form a gate with high precision because lateral etching progresses to a considerable extent, and the sidewall length, that is, the gate length, is greatly influenced by this effect. Figure 2 (a) shows that the gate resistance becomes extremely large in this conventional gate formation method.
This is also clear from (d).

[Means to solve the problem]

According to the present invention, there is a step of depositing a gate metal and a barrier metal for preventing Au diffusion on the entire surface, a first insulating film is grown thereon, and anisotropic dry etching is performed to form a vertical layer of the first insulating film. A step is formed in the gate formation region, and after the second insulating film is grown, the first insulating film is formed by anisotropic dry etching.
A step of leaving a second insulating film as a sidewall film on the stepped sidewall of the insulating film, and after coating and planarizing a photoresist, the photoresist and the second insulating film are coated until the upper surface of the second insulating film remaining as a sidewall film is exposed. A process of anisotropic dry etching of the first insulating film, a process of selectively etching the second insulating film with respect to the first insulating film, a process of wet etching with a tinda liquid, and plating the Bali 7 metal. A process of growing Au plating on the gate metal in the sidewall film removed portion as a pass, and a process of anisotropic dry etching the barrier metal and gate metal using the Au plating as a mask after etching and removing the first insulating film and photoresist. A method for manufacturing a field effect transistor is obtained.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(h) are cross-sectional views of one embodiment of the present invention. First, as shown in FIG. 1(a), WSil as a gate metal, Ti3 as a binder, and Pt4 as a barrier metal are successively deposited by sputtering. For example, WSi-Ti-Pt has 2000 people and 1000 people
There are 500 people. Next, 5000 layers of 5ixN, 5 are grown on PtJ by plasma CVD. Next, as shown in FIG. 1(b), one side of the gate formation region is masked with a photoresist 6 and etched using CF 4 or active ion etching (RIE) to form a vertical step. After removing photoresist 6, reduce pressure C
Grow 4,000 5iO27 cells using the VD method (Figure 1 (C)). Next, by RIE using CF, 5iOz7
5iO27 as shown in Figure 1(d).
A side wall film 7' is left. Next, after applying the photoresist 6' again and planarizing it (FIG. 1(e)), for example, CF,
The photoresists 6' and 31 are coated with 10□ of mixed gas.
3N45 is etched until the upper part of the side wall film 7' is exposed (FIG. 1(f)). Next, the SiO2 side wall film 7' is selectively etched with a solution of hydrofluoric acid:water=1=6. Au plating 8 is grown on the etched portion using the Pt layer 4 as a plating pass (FIG. 1(g)).

Next, first, the photoresist 6' is removed by ashing with 02 plasma, and then 5i3 is removed by dry etching with CF.
Remove N45. Thereafter, Pt4 and Ti3 are etched by ion milling using the Au plating 8 as a mask, and then WSi2 is etched using a mixed gas of, for example, CF and /SF to form a gate (FIG. 1(h)).

The present invention is not limited to the above embodiments, and the sidewall film may be formed by a coating method. In this case, 5i027 shown in Fig. 1(c) becomes Sing, so-called SOG, by the coating method, but the advantage of using this is that in Fig. 1('), this sidewall film 7' is removed. When using normal low pressure CVD etc.
It is possible to use an etching solution that has a higher etching selectivity for 5isNn than for Ch, improving gate length controllability. For example, in this case, hydrofluoric acid:water = 1:30
The sidewall film can be easily etched by dipping it in a thin etching solution of 5 niN for a few seconds, and there is almost no gate length expansion due to lateral etching of <5iiN.

〔Effect of the invention〕

As explained above, according to the present invention, a sidewall film is formed from an insulating film, the upper part of this sidewall film is exposed using a flattening etch bar, and then selectively etched to remove the Au grown in the etched region of the sidewall film. By processing the underlying gate metal using plating as a mask, it is possible to form a fine gate with excellent dimensional controllability and low gate resistance.

[Brief explanation of the drawing]

FIGS. 1(a) to (h) are cross-sectional views showing an embodiment of the present invention in the order of steps, and FIGS. 2(a) to (d) are sectional views showing the conventional gate manufacturing method using sidewall technology in the order of steps. FIG. l...Substrate, 2...WSi, 3...
...T X s4...Pt, 5...
5isN 6,6'...Photoresist, 7
......SiO2s 8...Au, 7
′... Side wall membrane.

Claims (1)

[Claims] A step of sequentially depositing a first metal layer serving as a gate metal and a second metal layer for preventing Au diffusion on the main surface of a semiconductor substrate, and growing a first insulating film on the second metal layer. a step of selectively performing anisotropic dry etching on the first insulating film to form an insulating film step perpendicular to the gate formation region; a step of growing a second insulating film over the entire surface; 2
A step of leaving a second insulating film on the side surface of the first insulating film in the step portion by anisotropic dry etching the insulating film of etching the organic material and the first insulating film by directional dry etching until the upper part of the second insulating film is exposed; etching the remaining part of the second insulating film with the first insulating film and the organic material; a step of removing with an etching solution having selectivity, a step of growing Au plating on the removed portion using the second metal layer as a plating pass, and dry etching the first insulating film and the organic material. a step of removing the second metal layer using the Au plating part as a mask;
A method for manufacturing a field effect transistor, comprising the step of removing the first metal layer.