JPH1187322A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable fine processing of a strip shape. SOLUTION: In a process for forming a junction field effect transistor, SiO2 film 2 is first formed on a gallium arsenide substrate 1, a resist film 3 having a space of 0.5 μm is provided on the film 2, and the film 2 is etched by an isotropic dry etcher with an over-etching time and with use of the film 3 as a mask. At this time, the etching is continued until the film 2 under the film 3 has a line width of 0.3 μm. Then a plasma Si3 N4 film is deposited by a CVD process on the film 2 and a GaAs substrate 1 and is subjected on its full surface to an etch-back process by the isotropic dry etcher to be planarized, the SiO2 film 2 is subjected to a web etching process with the use of hydrofluoric acid for forming a gate window opening pattern having a width of 0.3 μm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of performing slit-shaped fine processing.

[0002]

2. Description of the Related Art FIGS. 8A to 8E show a conventional semiconductor device manufacturing method (junction field effect transistor (JFE).
It is sectional drawing which shows (a part of manufacturing process of T).

[0003] First, as shown in FIG. 8 (a), a CVD (Cheine) is formed on the surface of a gallium arsenide substrate (GaAs substrate) 51.
First plasma Si by mical vapor deposition) method
₃ N ₄ film 53 is deposited. Next, the plasma Si ₃
On the N ₄ film 53, a photoresist film 55 having an elongated slit-like gate pattern is provided. The width of this slit is, for example, 0.6 μm.

After that, as shown in FIG. 8B, the Si ₃ N ₄ film 53 is opened to 0.6 μm by etching using the photoresist film 55 as a mask. At this time, a Si ₃ N ₄ film 53 is formed on the GaAs substrate 51 by 50 nm.
Degree is left. This is to suppress damage to the surface of the GaAs substrate 51 due to etching.

Next, as shown in FIG. 8C, the photoresist film 55 is peeled off. Thereafter, as shown in FIG. 8D, a second plasma Si ₃ N ₄ film 57 is further formed on the first Si ₃ N ₄ film 53 by the CVD method.
As a result, the second Si ₃ N ₄ film 57 is also formed on the side wall of the convex portion of the first Si ₃ N ₄ film 53, so that the 0.6 μm wide slit-like pattern is formed to a 0.4 μm width. In a slit pattern.

[0006] Thereafter, as shown in FIG.
The second Si ₃ N ₄ films 53 and 57 are etched by an anisotropic dry etcher over the entire surface. At this time, since the side wall of the fine slit pattern is hard to be etched, the Si ₃ N ₄ film 5 at the bottom of the slit is formed by this etching.
3, 57 will be removed. As a result, 0.6 μ
The gate window of the 0.4 μm Si ₃ N ₄ film 53 can be opened on the GaAs substrate 51 by the m photoresist pattern.

[0007]

In the above-described conventional method for manufacturing a semiconductor device, a gate window of 0.4 .mu.m is opened.
In the step (d), the second Si ₃ N ₄ film 57 must be formed thicker. In this case, S shown in FIG.
The i ₃ N ₄ film becomes thick, and as a result, the gate is buried. Therefore, the conventional method of manufacturing a semiconductor device has been limited to opening a gate window of 0.4 μm.

In the step shown in FIG. 8E, since the gallium arsenide surface is directly opened by the anisotropic etcher, the gallium arsenide surface is unevenly etched on the substrate. As a result, the channel width immediately below the gate varies on the substrate, which causes a reduction in yield. In addition, plasma Si
₃ N ₄ film can have higher etching rate, it is difficult to control the etching amount.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of performing slit-shaped fine processing.

[0010]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises the steps of forming an insulating film on a substrate and providing a mask film on the insulating film. And a step of isotropically overetching the insulating film using the mask film as a mask.

After the step of isotropic over-etching, a step of removing the mask film, a step of forming a film having a different etching rate from the insulating film on the insulating film and the substrate, Etching back the film;
It is preferable that the method further includes a step of removing the insulating film.

In the above method of manufacturing a semiconductor device, the insulating film immediately below the mask film is etched to the side wall by isotropically overetching the insulating film using the mask film as a mask. Therefore, an insulating film having a width smaller than the width of the mask film can be formed. Therefore, the line width can be controlled by the isotropic overetching of the insulating film.

The substrate may be, for example, a gallium arsenide substrate, but other substrates may be used. Further, it is preferable to use a SiO ₂ film as the insulating film. Further, it is preferable to use a resist film as the mask film.
Further, a film having an etching rate different from that of the insulating film is Si
It is preferable to use ₃ N ₄ film.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 to 7 are sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 1, a gallium arsenide substrate (GaAs substrate) 1 has
An O ₂ film 2 is formed. Next, a photoresist film 3 for forming an elongated slit-like gate pattern is provided on the SiO ₂ film 2. The photoresist film 3 is patterned, and the width of the photoresist film 3 is, for example, 0.5 μm.

Thereafter, as shown in FIG. 2, using the photoresist film 3 as a mask, the SiO ₂ film 2 is etched by an isotropic dry etcher with an etching time exceeding the etching time. At this time, etching is performed until the line width of the SiO ₂ film 2 under the photoresist film 3 becomes a line pattern of 0.3 μm.

Next, as shown in FIG. 3, the photoresist film 3 is peeled off, and after etching the Si
An O ₂ film pattern is formed. That is, a SiO ₂ film 2 of a 0.3 μm width convex pattern is formed on a GaAs substrate 1.
Is formed.

Thereafter, as shown in FIG.
A plasma Si ₃ N ₄ film 5 is formed on the iO ₂ film 2 and the GaAs substrate 1 by a CVD method. At this time, a convex portion 5a is formed on the convex SiO ₂ film 2.

Next, as shown in FIG. 5, the Si ₃ N ₄ film 5
Is provided with a resist film 6 for etch back.
This resist film 6 has the same etching rate as the plasma Si ₃ N ₄ film 5 (the selectivity between the Si ₃ N ₄ film 5 and the resist film 6 is 1: 1) with respect to the reactive ion etching used for the etch back. Things.

Thereafter, as shown in FIG.
Then, the entire surface of the Si ₃ N ₄ film 5 is etched to the upper surface of the convex SiO ₂ film 2 by an isotropic dry etcher. As a result, the convex portions 5a of the resist film 6 and the Si ₃ N ₄ film 5 are etched, so that the upper surface of the SiO ₂ film 2 is exposed and the Si ₃ N ₄ film 5 is planarized. Therefore, the flat Si
_The state is such that the SiO ₂ film 2 is embedded in the ₃ N ₄ film 5.

Next, as shown in FIG. 7, by etching the SiO ₂ film 2 with a wet etching solution such as hydrofluoric acid, the Si ₃ N ₄ film 5 has a slit-shaped pattern having a width of 0.3 μm. A gate window opening portion (gate window opening pattern) 8 is formed.

According to the above embodiment, the SiO ₂ film 2 is etched by using the photoresist film 3 as a mask in the process of FIG. The pattern shape can be processed, and a thinner 0.3 μm wide SiO ₂ film 2 can be formed using the 0.5 μm width resist film 3. Since this 0.3 μm-wide SiO ₂ film 2 becomes the gate window opening 8 shown in FIG.
The line width can be controlled by over-etching the O ₂ film 2. Therefore, 0.4 μm, which has been a limit in opening a gate window by a conventional method of manufacturing a semiconductor device, is used.
It is possible to open a gate window with a width of 0.3 μm finer than the width of m.

FIG. 8 shows a conventional method of manufacturing a semiconductor device.
The gallium arsenide surface is not directly etched by the anisotropic dry etcher as in the step shown in FIG. Therefore, the gate can be processed without receiving plasma damage. As a result, the yield of the JFET can be improved, and Vth (threshold), which is a characteristic of the JFET, can be easily controlled. Further, since the gallium arsenide surface of the gate portion is not etched, the uniformity of the channel width in the substrate surface can be improved, and the number of times of gate diffusion can be reduced. This leads to an improvement in the productivity of the semiconductor device.

Further, although etching the SiO ₂ film 2 a photoresist film 3 in the step of FIG. 2 as a mask, SiO ₂
Since the etching rate of the SiO ₂ film 2 is stable,
It is easy to control the amount of etching when over-etching. This leads to an improvement in the productivity of the semiconductor device.

[0025]

As described above, according to the present invention, the insulating film is isotropically over-etched using the mask film as a mask. Therefore, it is possible to provide a method for manufacturing a semiconductor device capable of performing slit-shaped fine processing.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention, showing a step subsequent to FIG. 1;

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention, showing a step subsequent to FIG. 2;

FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention, which shows the step subsequent to FIG. 3;

FIG. 5 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the embodiment of the present invention, which shows the step subsequent to FIG. 4;

FIG. 6 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention, which illustrates the next step of FIG. 5;

FIG. 7 is a cross-sectional view showing a step subsequent to FIG. 6, illustrating the method for manufacturing a semiconductor device according to the embodiment of the present invention;

FIGS. 8A to 8E are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1: Gallium arsenide substrate (GaAs substrate) 2: SiO ₂
Film, 3 ... photoresist film, 5 ... plasma Si ₃ N ₄ film,
5a: convex portion, 6: resist film, 8: gate window opening portion (gate window opening pattern), 51: gallium arsenide substrate (Ga
As substrate), 53... First plasma Si ₃ N ₄ film, 55
... Photoresist film, 57 ... Second plasma Si ₃ N ₄
film.

Claims (2)

[Claims] 1. A step of forming an insulating film on a substrate, a step of providing a mask film on the insulating film, and a step of isotropically overetching the insulating film using the mask film as a mask. A method for manufacturing a semiconductor device, comprising: 2. A step of removing the mask film after the step of isotropic over-etching, a step of forming a film having an etching rate different from that of the insulating film on the insulating film and the substrate, 2. The method according to claim 1, further comprising a step of etching back the film and a step of removing the insulating film.