KR100392362B1 - Selective wet etching method of silicon - Google Patents
Selective wet etching method of silicon Download PDFInfo
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- KR100392362B1 KR100392362B1 KR10-2000-0086556A KR20000086556A KR100392362B1 KR 100392362 B1 KR100392362 B1 KR 100392362B1 KR 20000086556 A KR20000086556 A KR 20000086556A KR 100392362 B1 KR100392362 B1 KR 100392362B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
본 발명은 실리콘 박막의 식각 방법에 관한 것으로서 특히 도핑된 실리콘박막과 비도핑된 실리콘박막 사이에 높은 식각 선택비를 가지는 습식 식각에 대한 것이다. 본 발명을 이용할 경우 6:1 이상의 높은 식각 선택비를 가지게 되기 때문에 반도체 소자의 제조 과정에서 기술자가 원하는 다양한 형태의 소자 구조를 형성하고자할 때 손쉽게 공정의 제어가 가능하다. 또한 종래의 건식 식각 방법에서는 식각 대상의 하층 박막에 미치는 손상 때문에 불가능했던 공정의 진행이 가능하다. 따라서 본 발명을 이용할 경우 기술자가 원하는 소자의 특성에 가장 적합한 소자의 구성이 보다 용이해지며 그 공정의 제어도 손쉬어지기 때문에, 결과적으로 소자의 특성 향상과 생산성의 향상을 꾀할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching method of a silicon thin film, and more particularly, to wet etching having a high etching selectivity between a doped silicon film and an undoped silicon thin film. When using the present invention has a high etching selectivity ratio of 6: 1 or more, it is possible to easily control the process when forming a variety of device structures desired by a technician in the manufacturing process of the semiconductor device. In addition, in the conventional dry etching method, a process that is impossible due to damage to the lower layer thin film to be etched is possible. Therefore, when using the present invention, since the configuration of the device most suitable for the characteristics of the device desired by the technician is easier and the control of the process is easier, the characteristics of the device and the productivity can be improved as a result.
Description
본 발명은 실리콘 박막의 식각 방법에 대한 것으로서, 도핑된 실리콘 박막과 비도핑 실리콘 박막 사이에 높은 식각 선택비를 가지는 습식식각 방법에 관한 것으로, TFT-LCD (Thin-Film Transistor Liquid Crystal Display) 장치 제조에 필수적인 요소인 TFT(Thin-Film Transistor) 제조에 응용 가능한 실리콘 박막 식각 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching method of a silicon thin film, and to a wet etching method having a high etching selectivity between a doped silicon film and an undoped silicon thin film, and manufacturing a TFT-LCD (Thin-Film Transistor Liquid Crystal Display) device. The present invention relates to a silicon thin film etching method applicable to TFT (Thin-Film Transistor) manufacturing, which is an essential element.
도 1a 내지 도 1b는 종래의 방법에 의해 제조된 TFT의 구조를 보여준다.1A to 1B show the structure of a TFT manufactured by a conventional method.
도 1a 및 도 1b를 참조하면, TFT의 구조는 절연성기판(11) 상에 금속 게이트(12)가 위치하고 그 위에 게이트 절연막(13)이 형성되고 그 위로 활성층인 비도핑 실리콘 박막(14)이 존재하고 그 위에 소스/드레인의 접촉 저항을 줄이기 위한 n+ 도핑된 실리콘 박막(15)이 존재하고, 그 상부에 소스/드레인 금속(16)이 형성되는 역스태거드 (inverted-staggerd) 방식이 주로 사용되고 있다.Referring to FIGS. 1A and 1B, the TFT structure includes a metal gate 12 disposed on an insulating substrate 11, a gate insulating layer 13 formed thereon, and an undoped silicon thin film 14 serving as an active layer thereon. And an n + doped silicon thin film 15 to reduce contact resistance of the source / drain thereon, and an inverted-staggerd method in which the source / drain metal 16 is formed thereon. .
이러한 구조로 TFT를 형성하기 위해서는 비도핑 실리콘 박막(14)위에 증착되는 n+ 도핑된 실리콘 박막(15)을 제거하되 하부에 존재하는 비도핑 실리콘 박막(14)에는 영향을 최소화하는 방법이 필수적으로 필요하게 된다.In order to form a TFT with such a structure, a method of removing the n + doped silicon thin film 15 deposited on the undoped silicon thin film 14 and minimizing the influence on the undoped silicon thin film 14 below is essential. Done.
도 1a는 건식 식각 방법을 이용하여 n+ 도핑된 실리콘 박막(15)을 식각했을때로서, n+ 도핑된 실리콘 박막(15)의 식각시 비도핑 실리콘 박막(14)에 대한 손상이 불가피하게 존재했다. 특히 낮은 선택비 ( < 5:1 )때문에 비도핑 실리콘 박막의 불필요한 식각으로 이어졌다.FIG. 1A illustrates that when the n + doped silicon thin film 15 is etched using the dry etching method, damage to the undoped silicon thin film 14 is inevitably present during the etching of the n + doped silicon thin film 15. In particular, the low selectivity (<5: 1) led to unnecessary etching of the undoped silicon thin film.
즉, n+ 도핑된 실리콘 박막(15) 하부에 있는 활성층(비도핑 실리콘 박막)의 두께가 얇아지게 되는데 그 양이 공정에서 쉽게 제어 가능하지 않은 범위에 있기 때문에 공정 진행후 활성층의 균일한 형성이 불가능해지고 결국 소자의 특성이 불균일해지는데 중요한 원인으로 작용하게 된다.That is, the thickness of the active layer (non-doped silicon thin film) under the n + doped silicon thin film 15 becomes thin, and since the amount is in a range that cannot be easily controlled in the process, it is impossible to uniformly form the active layer after the process proceeds. This results in an important cause for the nonuniformity of the device.
종래에는 이와 같은 문제 때문에 n+ 도핑된 실리콘 박막(15)의 식각시 하부 비도핑 실리콘 박막이 영향을 받지 않도록 하기 위해서 도 1b 의 경우처럼 식각방지층(19)을 사용하기도 하였다. 이 경우 n+ 도핑된 실리콘 박막(15)의 식각시 하부에 있는 식각방지층(19)이 비도핑 실리콘 박막(14)을 보호하기 때문에 손상은 피할 수가 있지만 소자(TFT)의 구조에 필수적이지 않은 하나의 층이 삽입되게 되며 공정 수의 증가와 함께 생산성의 저하를 가져오는 원인이 될 수 있다.In the related art, in order to prevent the lower undoped silicon thin film from being affected when the n + doped silicon thin film 15 is etched, an etch stop layer 19 is used as in FIG. 1B. In this case, damage may be avoided because the etch stop layer 19 at the bottom of the n + doped silicon thin film 15 protects the undoped silicon thin film 14, but is not essential to the structure of the TFT. The layers may be inserted and cause a decrease in productivity with an increase in the number of processes.
상술한 바와 같이 반도체소자를 제조하는 경우 도핑된 실리콘 박막과 비도핑된 실리콘 박막을 선택적으로 식각하는 과정이 필요시 되는 경우가 있는데, 종래기술의 식각 방법을 사용하는 경우 하부층인 비도핑된 실리콘 박막이 식각시 손상되거나, 식각방지층 사용에 따른 공정의 추가(박막증착 및 포토리소그라피 공정 및 식각 공정)를 가져오는 문제점이 있다.As described above, when manufacturing a semiconductor device, there is a case where a process of selectively etching a doped silicon thin film and an undoped silicon thin film is required. In the case of using a conventional etching method, an undoped silicon thin film is a lower layer. There is a problem that is damaged during the etching, or the addition of the process (thin film deposition and photolithography process and etching process) according to the use of the etch stop layer.
본 발명은 도핑된 실리콘 박막과 비도핑된 실리콘 박막 간의 식각선택비가 우수한 습식식각 방법을 제공하는데 그 목적이 있다.It is an object of the present invention to provide a wet etching method having an excellent etching selectivity between a doped silicon film and an undoped silicon film.
도 1a 내지 도 1b는 종래의 방법에 의해 제조된 박막트랜지스터의 제조 과정을 설명하기 위한 단면도.1A to 1B are cross-sectional views illustrating a manufacturing process of a thin film transistor manufactured by a conventional method.
도 2a 내지 도 2c는 본 발명에 따른 실리콘 식각 공정을 나타내는 단면도.2A to 2C are cross-sectional views illustrating a silicon etching process according to the present invention.
도 3a 내지 도 3b는 본 발명의 식각 특성중 불화수소의 함량 변화에 따른 식각 선택비의 변화를 설명하기 위한 도면.3a to 3b are views for explaining the change in the etching selectivity according to the change in the content of hydrogen fluoride in the etching characteristics of the present invention.
* 도면의 주요 부분에 대한 설명 *Description of the main parts of the drawing
21 : 소정 공정이 완료된 구조물21: Structure where predetermined process is completed
22 : 비도핑된 실리콘 박막22: undoped silicon thin film
23 : 도핑된 실리콘 박막23: doped silicon thin film
24 : 마스크패턴24: mask pattern
상기 목적을 달성하기 위한 본 발명은 소정 공정이 완료된 구조물 상에 비도핑된 실리콘 박막과 도핑된 실리콘 박막을 적층하는 단계: 상기 도핑된 실리콘 박막 상에 도핑된 실리콘 박막의 식각 영역이 오픈된 마스크패턴을 형성하는 단계; 상기 도핑된 실리콘 박막을 상기 비도핑된 실리콘 박막에 대해 선택적으로 습식 식각하는 단계를 포함하며, 상기 습식 식각 용액은 산화작용이 큰 성분과 상기 산화작용에 의하여 형성된 산화막을 식각하는 성분을 포함하는 것을 특징으로 한다.The present invention for achieving the above object is a step of laminating a undoped silicon thin film and a doped silicon thin film on the structure is completed: a mask pattern in which the etched region of the doped silicon thin film is opened on the doped silicon thin film Forming a; Selectively wet etching the doped silicon thin film with respect to the undoped silicon thin film, wherein the wet etching solution includes a component having a large oxidation effect and a component for etching the oxide film formed by the oxidation process. It features.
본 발명에서, 상기 습식 식각 용액은 실리콘을 산화시키는 질산과 산화막을 식각하는 불화수소를 포함하는 용액인 것을 특징으로 한다.In the present invention, the wet etching solution may be a solution containing nitric acid for oxidizing silicon and hydrogen fluoride for etching an oxide film.
이하 첨부된 도면을 참조하여 본 발명을 보다 상세히 살펴보도록 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 실리콘 식각 공정을 나타내는 단면도이다.2A to 2C are cross-sectional views illustrating a silicon etching process according to the present invention.
도 2a는 소정 공정이 완료된 구조물(21) 상에 비도핑된 실리콘 박막(22)과 도핑된 실리콘 박막(23)이 적층되어 있는 상태이고, 도 2b는 식각영역이 오픈된 마스크패턴(24)을 형성한 상태이다.2A illustrates a state in which a undoped silicon thin film 22 and a doped silicon thin film 23 are stacked on a structure 21 in which a predetermined process is completed, and FIG. 2B illustrates a mask pattern 24 having an etched region open. It is in a formed state.
상기 마스크패턴(24)는 포토리소그라피 공정에 의해 형성된 포토레지스트패턴이 될 수도 있고, 금속과 같이 폴리실리콘과 습식식각 선택비를 갖는 물질이 사용 가능하다.The mask pattern 24 may be a photoresist pattern formed by a photolithography process, and a material having a polysilicon and a wet etching selectivity such as a metal may be used.
아울러, 어떤 소자에 본 발명의 방법이 적용되느냐에 따라서 그 소자의 구성 요소 일부층을 그대로 사용할 수도 있다.In addition, depending on which device the method of the present invention is applied, a partial layer of components of the device may be used as it is.
이어서, 도 2c는 본 발명의 방법에 따라 습식 식각을 수행하여 도핑된 실리콘 박막(23)을 식각한 상태이다.Subsequently, FIG. 2C shows a state in which the doped silicon thin film 23 is etched by performing wet etching according to the method of the present invention.
이와 같이 본 발명은 습식 식각을 사용하여 도핑된 실리콘 박막을 비도핑된 실리콘 박막에 대해 선택적으로 식각하는 바, 이때 불화수소(HF)와 질산 및 초산을 혼합한 용액 또는 불화수소와 질산과 물을 혼합한 용액을 사용한다.As such, the present invention selectively etches the doped silicon thin film with respect to the undoped silicon thin film by using wet etching, wherein a solution containing hydrogen fluoride (HF), nitric acid and acetic acid, or hydrogen fluoride, nitric acid and water Use a mixed solution.
이 용액의 특징은 실리콘 성분의 박막을 질산에 의한 산화작용 및 산화막을 식각하는 불화수소의 작용을 동시에 가지고 있다는 점이다. 그러므로 실제 식각이 진행되는 과정은 실리콘 박막의 표면을 산화시키고 산화된 표면층을 제거하고, 이때 다시 새로운 표면이 드러나게 되어 다시 산화가 진행되는 과정을 반복적으로 겪게 된다.The solution is characterized in that the thin film of the silicon component has the action of oxidation by nitric acid and hydrogen fluoride to etch the oxide film. Therefore, the actual etching process oxidizes the surface of the silicon thin film and removes the oxidized surface layer. At this time, the new surface is revealed again and the oxidation process is repeated.
한편 박막의 산화 특성이 박막의 도핑여부에 따라 크게 차이가 나게 되기 때문에 도핑된 실리콘 박막과 비도핑된 실리콘 박막 사이에는 식각 선택비가 발생한다. 용액상의 혼합비율에 따라 선택비가 달라지게 되는데, 일반적으로 6:1 이상의 선택비를 가지게 할 수 있다. 이때 식각 선택비는 혼합용액의 각 성분의 조절을 통해 제어가 가능하다.On the other hand, since the oxidation characteristics of the thin film are greatly different depending on the doping of the thin film, an etching selectivity occurs between the doped silicon film and the undoped silicon film. The selection ratio varies depending on the mixing ratio of the solution phase, and in general, it may have a selection ratio of 6: 1 or more. At this time, the etching selectivity can be controlled by adjusting each component of the mixed solution.
도 3a 및 도 3b와 같이 불화 수소의 양을 조절할 경우에 선택비의 변화가 일어나는 것을 볼 수 있다. 이때 사용되는 공정의 특성에 맞게 선택비를 조정하면 되는데, 선택비의 증가는 식각 속도의 증가를 동반하기 때문에 공정의 균일도나 안정성 측면의 약화를 가져 올 수도 있다. 이러한 점들을 모두 고려한다면 공정에 최적화된 용액의 혼합비율 및 공정 조건을 선정할 수 있을 것이다.It can be seen that the change in selectivity occurs when the amount of hydrogen fluoride is adjusted as in FIGS. 3A and 3B. In this case, the selection ratio may be adjusted according to the characteristics of the process used. Since the increase in the selection ratio is accompanied by an increase in the etching rate, the uniformity or stability of the process may be weakened. Considering all of these points, it is possible to select the mixing ratio and process conditions of the solution optimized for the process.
그밖에 본 발명의 특징으로는 건식식각에서 발생하게 되는 플라즈마에 의한 손상을 배제할 수 있기 때문에, 같은 선택비를 가지는 건식 식각 공정이 있다고 하더라고 소자의 특성 측면에서는 장점을 가지고 있다는 것이다.In addition, since the damage caused by the plasma generated in the dry etching can be eliminated, the dry etching process having the same selectivity has advantages in terms of device characteristics.
한편, 상기 마스크패턴(24)은 후속 공정에서 제거할 수도 있고, 그대로 놔둘수도 있으며, 습식 식각후에 드러난 비도핑 실리콘 박막 상에 산화막이 생성되므로 필요에 따라 제거할 수도 있고 그냥 놔둘 수도 있다.Meanwhile, the mask pattern 24 may be removed in a subsequent process, or may be left as it is, or may be removed or left as necessary since an oxide film is formed on the undoped silicon thin film exposed after wet etching.
본 발명에서는 습식 식각을 사용하여 비도핑 실리콘 박막 상부에 있는 도핑된 실리콘 박막을 식각하게 된다. 이때 6:1 이상의 선택비를 가지게 된다. 따라서 도핑된 실리콘 박막의 두껍지 않을 경우 (보통 <500um), 50%까지의 과도 식각을 하더라도 식각되는 비도핑 실리콘 박막의 층의 두께는 40um이하가 되게 된다. 즉, 비도핑 실리콘 박막에는 거의 영향을 주지 않게 된다. 따라서, 비도핑 실리콘 박막이 TFT의 활성층으로 쓰이는 경우에 식각시 손상에 대비하여 불필요하게 두께를 높일 필요가 없어진다.In the present invention, wet etching is used to etch the doped silicon thin film on top of the undoped silicon thin film. In this case, the selection ratio is greater than 6: 1. Therefore, if the thickness of the doped silicon thin film is not thick (usually <500um), even if the excessive etching up to 50% of the etched layer of the undoped silicon thin film is less than 40um. In other words, the undoped silicon thin film has little effect. Therefore, when the undoped silicon thin film is used as the active layer of the TFT, there is no need to increase the thickness unnecessarily in preparation for damage during etching.
또한 습식 식각의 경우 건식식각에서 발생하게 되는 플라즈마에 의한 손상을 배제할 수 있기 때문에, 같은 선택비를 가지는 건식 식각 공정이 있다고 하더라고 소자의 특성 측면에서는 좋은 점을 가지고 있다.In addition, in the case of wet etching, the damage caused by the plasma generated by the dry etching can be eliminated, and therefore, there is a dry etching process having the same selectivity.
따라서, 본 발명을 TFT과 같은 반도체소자 제조 공정에 응용할 경우 반도체소자 제조 공정의 단순화 및 소자 특성을 향상시키는 뛰어난 효과를 가지게 된다.Therefore, when the present invention is applied to a semiconductor device manufacturing process such as a TFT, it has an excellent effect of simplifying the semiconductor device manufacturing process and improving device characteristics.
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| KR20140118125A (en) | 2013-03-28 | 2014-10-08 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20140118455A (en) | 2013-03-29 | 2014-10-08 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20140118147A (en) | 2013-03-28 | 2014-10-08 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20150109880A (en) | 2014-03-21 | 2015-10-02 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20150111733A (en) | 2014-03-26 | 2015-10-06 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20150113482A (en) | 2014-03-31 | 2015-10-08 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20150113621A (en) | 2014-03-31 | 2015-10-08 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
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| JPH06140436A (en) * | 1992-10-29 | 1994-05-20 | Rohm Co Ltd | Compound semiconductor device and its manufacture |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20140118125A (en) | 2013-03-28 | 2014-10-08 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20140118147A (en) | 2013-03-28 | 2014-10-08 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20140118455A (en) | 2013-03-29 | 2014-10-08 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20150109880A (en) | 2014-03-21 | 2015-10-02 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20150111733A (en) | 2014-03-26 | 2015-10-06 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20150113482A (en) | 2014-03-31 | 2015-10-08 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20150113621A (en) | 2014-03-31 | 2015-10-08 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
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