KR20020048616A - Method for forming gate pattern of flash memory device - Google Patents
Method for forming gate pattern of flash memory device Download PDFInfo
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- KR20020048616A KR20020048616A KR1020000077828A KR20000077828A KR20020048616A KR 20020048616 A KR20020048616 A KR 20020048616A KR 1020000077828 A KR1020000077828 A KR 1020000077828A KR 20000077828 A KR20000077828 A KR 20000077828A KR 20020048616 A KR20020048616 A KR 20020048616A
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- film
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000011065 in-situ storage Methods 0.000 abstract description 2
- -1 Silicon Oxy Nitride Chemical class 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000011109 contamination Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 7
- 238000004380 ashing Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로, 좀더 구체적으로는 플래시 메모리 장치의 게이트 패턴 형성 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate pattern of a flash memory device.
최근에는 게이트 전극의 저저항을 확보하기 위해 게이트 전극막으로 폴리실리콘막 및 실리사이드막이 차례로 적층된 폴리사이드막을 사용하는 추세이다. 이와 같이 폴리사이드막을 형성하는 경우, 게이트 패턴을 형성하기 위한 패터닝 공정을 위해 하드 마스크를 사용하는 식각 공정을 적용하는 경우가 많다. 그러나, 경우에 따라서 하드 마스크 상에 포토레지스트 패턴을 추가로 형성한 상태에서 식각 공정이 진행될 수도 있다.Recently, in order to secure a low resistance of the gate electrode, a polysilicon film in which a polysilicon film and a silicide film are sequentially stacked is used as the gate electrode film. In the case of forming the polyside film as described above, an etching process using a hard mask is often applied for the patterning process for forming the gate pattern. However, in some cases, the etching process may be performed while the photoresist pattern is further formed on the hard mask.
특히, 플래시 메모리용 게이트 패턴을 형성하는 경우, 셀 영역과 주변 회로 영역의 공정을 별도로 진행하기 위해 사진 공정을 실시해야 하므로, 게이트 전극막 상에 하드 마스크와 포토레지스트 패턴이 동시에 존재하게 된다. 이러한 경우에는 포토레지스트 패턴만으로도 패터닝 공정이 가능하므로, 하드 마스크막은 불필요하게 된다.In particular, in the case of forming a gate pattern for a flash memory, a photo process must be performed in order to separately process the cell region and the peripheral circuit region, so that a hard mask and a photoresist pattern are simultaneously present on the gate electrode film. In this case, since the patterning process can be performed only by the photoresist pattern, the hard mask film is unnecessary.
이하, 첨부된 도면들을 참조하여 종래 기술의 문제점을 설명한다.Hereinafter, the problems of the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1e는 종래 기술에 의한 게이트 패턴의 형성 방법을 설명하기 위한 단면도들이다.1A to 1E are cross-sectional views illustrating a method of forming a gate pattern according to the prior art.
도 1a를 참조하면, 반도체 기판(10) 상에 게이트 산화막(12)을 형성한다. 게이트 산화막(12) 상에 제 1 폴리실리콘막으로 부유 게이트막(14)을 형성한다. 부유 게이트막(14) 상에 ONO(oxide-nitride-oxide)막으로 절연막(15)을 형성한다. 절연막(15) 상에 제어 게이트막(18)을 형성한다. 제어 게이트막(18)은 차례로 적층된 제 2 폴리실리콘막(16) 및 텅스텐 실리사이드막(17)으로 구성된다. 제어 게이트막(18) 상에 마스크막(20) 및 반사방지막(22)을 차례로 형성한다. 마스크막(20)은 예를 들어, PE-산화막(plasma enhanced oxide)을 사용하여 1000 Å정도의 두께로 형성한다.Referring to FIG. 1A, a gate oxide film 12 is formed on a semiconductor substrate 10. The floating gate film 14 is formed on the gate oxide film 12 as the first polysilicon film. An insulating film 15 is formed on the floating gate film 14 by an oxide-nitride-oxide (ONO) film. The control gate film 18 is formed on the insulating film 15. The control gate film 18 is composed of a second polysilicon film 16 and a tungsten silicide film 17 that are sequentially stacked. The mask film 20 and the anti-reflection film 22 are sequentially formed on the control gate film 18. The mask film 20 is formed to a thickness of about 1000 mW using, for example, a PE-plasma enhanced oxide.
도 1b를 참조하면, 반사방지막(22) 상에 포토레지스트막을 형성한 후 패터닝하여 게이트 패턴을 형성하기 위한 포토레지스트 패턴(25)을 형성한다.Referring to FIG. 1B, a photoresist film 25 is formed on the antireflection film 22 and then patterned to form a photoresist pattern 25 for forming a gate pattern.
도 1c를 참조하면, 포토레지스트 패턴(25)을 식각마스크로 사용하여 제어 게이트막(18)의 상부, 즉 텅스텐 실리사이드막(17)이 노출될 때까지 반사방지막(22) 및 마스크막(20)을 차례로 식각한다. 그러면, 마스크막 패턴(20a), 반사방지막 패턴(22a) 및 포토레지스트 패턴(25)이 차례로 적층된 마스크층이 형성된다. 이때의 식각 공정은 산화막용 식각 설비에서 수행된다.Referring to FIG. 1C, using the photoresist pattern 25 as an etching mask, the anti-reflection film 22 and the mask film 20 until the upper portion of the control gate layer 18, that is, the tungsten silicide layer 17 is exposed. Etch sequentially. Then, a mask layer in which the mask film pattern 20a, the antireflection film pattern 22a, and the photoresist pattern 25 are sequentially stacked is formed. At this time, the etching process is performed in the etching facility for the oxide film.
도 1d를 참조하면, 마스크층을 식각마스크로 사용하여 반도체 기판(10)이 노출될 때까지 제어 게이트막(18), 절연막(15), 부유 게이트막(14) 및 게이트 산화막(12)을 차례로 식각한다. 이와 같은 식각 공정은 폴리실리콘용 식각 설비에서 수행된다.Referring to FIG. 1D, using the mask layer as an etching mask, the control gate layer 18, the insulating layer 15, the floating gate layer 14, and the gate oxide layer 12 are sequentially formed until the semiconductor substrate 10 is exposed. Etch it. This etching process is performed in an etching facility for polysilicon.
도 1e를 참조하면, 반사방지막 패턴(22a) 상에 잔류하는 포토레지스트 패턴(25)을 산소 플라즈마 애싱(O2plasma ashing) 공정으로 제거한다. 포토레지스트 패턴(25)이 제거된 결과물 전면을 습식 세정 용액을 사용하여 세정한다. 그러면, 게이트 산화막 패턴(12a), 부유 게이트(14a), 절연막 패턴(15a), 제어 게이트(18a), 마스크막 패턴(20a) 및 반사방지막 패턴(22a)이 차례로 적층된 게이트 패턴이 형성된다.Referring to FIG. 1E, the photoresist pattern 25 remaining on the anti-reflection film pattern 22a is removed by an O 2 plasma ashing process. The entire surface of the resultant from which the photoresist pattern 25 is removed is cleaned using a wet cleaning solution. Then, a gate pattern in which the gate oxide film pattern 12a, the floating gate 14a, the insulating film pattern 15a, the control gate 18a, the mask film pattern 20a, and the antireflection film pattern 22a are sequentially stacked is formed.
이와 같은 종래 기술에 의하면, 마스크막(20)으로 인해 게이트 패턴을 형성하기 위한 식각 공정이 각기 다른 식각 설비를 사용하는 2 단계의 공정으로 진행된다. 즉, 산화막용 식각 설비에서 마스크막(20) 및 반사방지막(22)을 식각하는 1 단계의 식각 공정을 수행한 후 폴리실리콘용 식각 설비로 반도체 기판(10)을 이동시켜 제어 게이트막(18), 절연막(15), 부유 게이트막(14) 및 게이트 산화막(12)을 식각하는 2 단계의 식각 공정을 수행하는 불연속적인 공정으로 진행된다. 이는 폴리실리콘용 식각 장비를 사용하여 식각을 진행하면, 1000 Å 정도의 두께의 산화막으로 형성된 마스크막(20)을 충분히 식각할 수 없기 때문이다.According to the related art, the etching process for forming the gate pattern due to the mask layer 20 proceeds to a two-step process using different etching facilities. That is, after performing the one-step etching process of etching the mask film 20 and the anti-reflection film 22 in the oxide film etching equipment, the semiconductor substrate 10 is moved to the polysilicon etching equipment to control the gate film 18. Then, the process proceeds to a discontinuous process of performing a two-step etching process for etching the insulating film 15, the floating gate film 14, and the gate oxide film 12. This is because when the etching is performed using an etching apparatus for polysilicon, the mask film 20 formed of an oxide film having a thickness of about 1000 mW cannot be sufficiently etched.
이에 따라, 게이트 패턴을 식각하는 공정에서 불필요한 시간적이 손실이 발생하게 되고, 식각 설비를 변경하는 과정에서 반도체 장치가 파티클(particle)들에 의해 오염되기 쉽다는 문제가 있다.Accordingly, there is a problem in that unnecessary time loss occurs in the process of etching the gate pattern, and the semiconductor device is easily contaminated by particles in the process of changing the etching facility.
본 발명은 상술한 제반 문제들을 해결하기 위해 제안된 것으로, 플래시 메모리 장치의 게이트 패턴을 형성하기 위한 식각 공정을 단일 식각 설비 내에서 연속적으로 수행할 수 있는 게이트 패턴의 형성 방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problems, and an object thereof is to provide a method of forming a gate pattern which can continuously perform an etching process for forming a gate pattern of a flash memory device in a single etching facility. There is this.
도 1a 내지 도 1e는 종래 기술에 의한 플래시 메모리 장치의 게이트 패턴 형성 방법을 설명하기 위한 단면도들이다.1A to 1E are cross-sectional views illustrating a gate pattern forming method of a conventional flash memory device.
도 2a 내지 도 2d는 본 발명의 실시예에 의한 플래시 메모리 장치의 게이트 패턴 형성 방법을 설명하기 위한 단면도들이다.2A to 2D are cross-sectional views illustrating a gate pattern forming method of a flash memory device according to an exemplary embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10, 100 : 반도체 기판12, 102 : 게이트 산화막10, 100: semiconductor substrate 12, 102: gate oxide film
14, 104 : 부유 게이트막15, 105 : 절연막14, 104: floating gate film 15, 105: insulating film
18, 108 : 제어 게이트막20 : 마스크막18, 108: control gate film 20: mask film
22, 112 : 반사방지막25, 115 : 포토레지스트 패턴22, 112: antireflection film 25, 115: photoresist pattern
(구성)(Configuration)
상술한 목적을 달성하기 위하여 본 발명에 의한 플래시 메모리 장치의 게이트 패턴 형성 방법은, 반도체 기판 상에 게이트 산화막을 형성한다. 상기 게이트 산화막 상에 부유 게이트막을 형성한다. 상기 부유 게이트막 상에 절연막을 형성한다. 상기 절연막 상에 제어 게이트막을 형성한다. 상기 제어 게이트막 상에 300 내지 500Å 두께의 반사방지막을 형성한다. 상기 반사방지막 상에 포토레지스트 패턴을 형성한다. 상기 포토레지스트 패턴을 식각마스크로 사용하여 상기 반사방지막, 상기 제어 게이트막, 상기 절연막, 상기 부유 게이트막 및 상기 게이트 산화막을 단일 식각 설비 내에서 차례로 건식 식각하여 게이트 패턴을 형성한다. 반사방지막을 충분히 얇게 형성하여 단일 식각 설비를 사용하는 식각 공정을 가능하게 함으로써, 연속적인 식각 공정으로 게이트 패턴을 형성할 수 있다.In order to achieve the above object, a gate pattern forming method of a flash memory device according to the present invention forms a gate oxide film on a semiconductor substrate. A floating gate film is formed on the gate oxide film. An insulating film is formed on the floating gate film. A control gate film is formed on the insulating film. An anti-reflection film having a thickness of 300 to 500 상 에 is formed on the control gate film. A photoresist pattern is formed on the antireflection film. Using the photoresist pattern as an etching mask, the antireflection film, the control gate film, the insulating film, the floating gate film, and the gate oxide film are sequentially dry-etched in a single etching facility to form a gate pattern. By forming the anti-reflection film sufficiently thin to enable an etching process using a single etching facility, the gate pattern can be formed by a continuous etching process.
본 발명에 있어서, 상기 부유 게이트막은 폴리실리콘막으로 형성하고, 상기 제어 게이트막은 폴리실리콘막 및 텅스텐 실리사이드막을 차례로 적층시켜 형성하는 것이 바람직하다.In the present invention, it is preferable that the floating gate film is formed of a polysilicon film, and the control gate film is formed by sequentially stacking a polysilicon film and a tungsten silicide film.
또한, 상기 절연막은 ONO막으로 형성하고, 상기 반사방지막은 실리콘산화질화막으로 형성하는 것이 바람직하다. 그리고, 절연막 및 반사방지막에 대한 식각 공정은 동일 식각 조건 하에서 CF4기체를 사용하여 실시하는 것이 바람직하다.In addition, the insulating film is preferably formed of an ONO film, and the anti-reflection film is formed of a silicon oxynitride film. In addition, the etching process for the insulating film and the antireflection film is preferably performed using CF 4 gas under the same etching conditions.
(실시예)(Example)
이하, 첨부된 도면들을 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 의한 플래시 메모리 장치의 게이트 패턴의 형성 방법을 설명하기 위한 단면도들이다.2A to 2D are cross-sectional views illustrating a method of forming a gate pattern of a flash memory device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(100) 전면에 열산화막을 성장시켜 게이트 산화막(102)을 형성한다. 게이트 산화막(102) 상에 부유 게이트막(104)을 형성한다. 부유 게이트막(104)은 예를 들어, 제 1 폴리실리콘막으로 형성하고, 1000Å 정도의두께로 형성한다. 부유 게이트막(104) 상에 절연막(105)을 형성한다. 절연막(105)은 예를 들어, ONO(oxide-nitride-oxide)막으로 형성하고, 200Å 정도의 두께로 형성한다. 절연막(105) 상에 제어 게이트막(108)을 형성한다. 제어 게이트막(108)은 제 2 폴리실리콘막(106) 및 텅스텐 실리사이드막(107)을 차례로 적층시켜 형성하는 것이 바람직하다. 제 2 폴리실리콘막(106) 및 텅스텐 실리사이드막(107)은 예를 들어, 각각 1000Å정도의 두께로 형성한다.Referring to FIG. 2A, a thermal oxide film is grown on the entire surface of the semiconductor substrate 100 to form a gate oxide film 102. The floating gate film 104 is formed on the gate oxide film 102. The floating gate film 104 is formed of, for example, a first polysilicon film, and has a thickness of about 1000 GPa. An insulating film 105 is formed on the floating gate film 104. The insulating film 105 is formed of, for example, an oxide-nitride-oxide (ONO) film, and is formed to a thickness of about 200 GPa. The control gate film 108 is formed on the insulating film 105. The control gate film 108 is preferably formed by stacking the second polysilicon film 106 and the tungsten silicide film 107 in this order. The second polysilicon film 106 and the tungsten silicide film 107 are each formed to a thickness of, for example, about 1000 mW.
제어 게이트막(108) 상에 본 발명의 특징인 반사방지막(112)을 형성한다. 반사방지막(112)은 게이트 패턴을 형성하기 위한 사진 식각 공정시 하부막, 즉 텅스텐 실리사이드막(107) 상에서 광원이 난반사되는 것을 방지하기 위한 것이다. 반사방지막(112)은 예를 들어, 실리콘산화질화막(siliconoxynitride; SION)으로 형성한다. 또한, 반사방지막(112)은 게이트 패턴을 형성하는 식각 공정이 하나의 식각 설비 내에서 연속적으로 진행될 수 있도록 충분히 얇은 두께로 형성한다. 이는 게이트 패턴의 대부분을 구성하는 폴리실리콘막을 식각하기 위한 설비를 사용하여 식각 공정이 진행될 경우, 통상적으로 폴리실리콘막용 식각 설비는 낮은 플라즈마 형성용 전력을 사용하므로, 반사방지막과 같은 절연막 계열의 막의 두께가 두꺼워지면 충분히 제거하기 어렵기 때문이다. 따라서, 반사방지막(112)은 300 내지 500 Å 정도의 두께로 형성하는 것이 바람직하다.An antireflection film 112, which is a feature of the present invention, is formed on the control gate film 108. The anti-reflection film 112 is to prevent diffuse reflection of the light source on the lower layer, that is, the tungsten silicide layer 107 during the photolithography process for forming the gate pattern. The anti-reflection film 112 is formed of, for example, silicon oxynitride (SION). In addition, the anti-reflection film 112 is formed to have a sufficiently thin thickness so that the etching process for forming the gate pattern can be continuously performed in one etching facility. This is because when the etching process is performed using the equipment for etching the polysilicon film that constitutes most of the gate pattern, the etching equipment for the polysilicon film typically uses low plasma forming power, and thus the thickness of the insulating film-based film such as an antireflection film It is because it is difficult to remove the thick enough. Therefore, the anti-reflection film 112 is preferably formed to a thickness of about 300 to 500 kPa.
도 2b 및 도 2c를 참조하면, 반사방지막(112) 상에 포토레지스트막을 형성한 후 패터닝하여 게이트 패턴을 형성하기 위한 포토레지스트 패턴(115)을 형성한다. 포토레지스트 패턴(115)을 식각마스크로 사용하여 반사방지막(112), 제어게이트막(108), 절연막(105), 부유 게이트막(104) 및 게이트 산화막(102)을 차례로 건식 식각하여 게이트 패턴을 형성한다.2B and 2C, a photoresist film is formed on the antireflection film 112 and then patterned to form a photoresist pattern 115 for forming a gate pattern. Using the photoresist pattern 115 as an etching mask, the antireflection film 112, the control gate film 108, the insulating film 105, the floating gate film 104, and the gate oxide film 102 are sequentially dry-etched to form a gate pattern. Form.
이와 같은 식각 공정은 종래 기술과는 달리 단일 식각 설비를 사용하는 연속적인 공정으로 진행된다. 구체적으로, 개별막을 식각하는 공정은 압력, 플라즈마 형성용 전력 및 자기력 등과 같은 공정 조건과 식각 기체의 종류를 달리하여 진행한다. 예를 들면, 반사방지막(112)은 기존의 ONO막을 식각하기 위한 공정 레서피(recipe)와 동일한 조건으로 CF4기체를 주입한 후 소정 시간 동안 식각하여 반사방지막 패턴(112a)을 형성한다. 이후, 기존의 텅스텐 실리사이드막에 대한 공정 레서피로 공정 조건을 변경시킨 후 SF6기체 및 Cl2기체를 주입하여 텅스텐 실리사이드막(107)을 식각한다. 이어서, 기존의 폴리실리콘막을 식각하는 공정 레서피 하에서 HBr 기체 및 Cl2기체를 주입하여 제 2 폴리실리콘막(106)을 식각한다. 그러면, 제 2 폴리실리콘막 패턴(106a) 및 텅스텐 실리사이드막 패턴(107a)이 차례로 적층된 제어 게이트(108a)가 형성된다. 그리고, 절연막(105) 및 제 1 폴리실리콘막(104)은 각각 반사방지막(112) 및 제 2 폴리실리콘막(106)의 식각 공정과 동일한 조건으로 식각하여 절연막 패턴(105a) 및 제 1 폴리실리콘막 패턴(104a)를 형성한다. 제 1 폴리실리콘막 패턴(104a)는 부유 게이트에 해당한다.This etching process, unlike the prior art, proceeds with a continuous process using a single etching facility. Specifically, the process of etching the individual film proceeds by varying the process conditions such as pressure, plasma forming power and magnetic force, and the type of etching gas. For example, the anti-reflection film 112 is injected with CF 4 gas under the same conditions as the process recipe for etching the conventional ONO film, and then etched for a predetermined time to form the anti-reflection film pattern 112a. Subsequently, after changing the process conditions with the conventional recipe for the tungsten silicide layer, the tungsten silicide layer 107 is etched by injecting SF 6 gas and Cl 2 gas. Subsequently, the second polysilicon film 106 is etched by injecting HBr gas and Cl 2 gas under the conventional recipe for etching the polysilicon film. Then, the control gate 108a in which the second polysilicon film pattern 106a and the tungsten silicide film pattern 107a are sequentially stacked is formed. The insulating film 105 and the first polysilicon film 104 are etched under the same conditions as the etching process of the anti-reflection film 112 and the second polysilicon film 106, respectively, to form the insulating film pattern 105a and the first polysilicon. The film pattern 104a is formed. The first polysilicon film pattern 104a corresponds to a floating gate.
도 2d를 참조하면, 반사방지막 패턴(112a) 상의 포토레지스트 패턴(115)을 산소 플라즈마 애싱 공정으로 제거한다. 포토레지스트 패턴(115)이 제거된 결과물 전면을 습식 세정 용액을 사용하여 세정하여 게이트 패턴을 포함하는 반도체기판(100)에 잔류하는 오염 물질들을 게거한다. 그러면, 게이트 산화막 패턴(102a), 부유 게이트(104a), 절연막 패턴(105a), 제어 게이트(108a) 및 반사방지막 패턴(112a)으로 구성된 플래시 메모리 장치용 게이트 패턴이 완성된다.Referring to FIG. 2D, the photoresist pattern 115 on the antireflection film pattern 112a is removed by an oxygen plasma ashing process. The entire surface of the resultant from which the photoresist pattern 115 is removed is cleaned using a wet cleaning solution to remove contaminants remaining on the semiconductor substrate 100 including the gate pattern. Then, the gate pattern for the flash memory device including the gate oxide film pattern 102a, the floating gate 104a, the insulating film pattern 105a, the control gate 108a, and the antireflection film pattern 112a is completed.
본 발명은 단일 식각 설비 내에서 연속적으로 식각 공정을 진행하여 게이트 패턴을 형성함으로써, 공정 시간을 단축시키고 식각 공정을 단순화할 수 있을 뿐만 아니라, 하나의 식각 설비 내에서 인시츄(in-situ) 공정으로 식각 공정을 진행하므로, 반도체 장치가 오염 물질들에 의해 오염되는 것을 최소화할 수 있다.The present invention not only shortens the process time and simplifies the etching process by continuously performing the etching process in a single etching facility to form a gate pattern, but also in-situ process in one etching facility. Since the etching process is performed, the semiconductor device may be minimized from being contaminated by contaminants.
Claims (6)
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1323425C (en) * | 2003-11-03 | 2007-06-27 | 海力士半导体有限公司 | Method for manufacturing flash memory device |
| KR100735625B1 (en) * | 2005-12-28 | 2007-07-04 | 매그나칩 반도체 유한회사 | Manufacturing method for control gate in electrically erasable programmable read only memory |
| KR100800379B1 (en) * | 2006-08-29 | 2008-02-01 | 삼성전자주식회사 | Method for manufacturing gate of non volatile memory device |
| KR100859485B1 (en) * | 2006-09-12 | 2008-09-24 | 동부일렉트로닉스 주식회사 | Manufacturing Method of Flash Memory Device |
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2000
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1323425C (en) * | 2003-11-03 | 2007-06-27 | 海力士半导体有限公司 | Method for manufacturing flash memory device |
| US7259067B2 (en) | 2003-11-03 | 2007-08-21 | Hynix Semiconductor Inc. | Method for manufacturing flash memory device |
| KR100735625B1 (en) * | 2005-12-28 | 2007-07-04 | 매그나칩 반도체 유한회사 | Manufacturing method for control gate in electrically erasable programmable read only memory |
| KR100800379B1 (en) * | 2006-08-29 | 2008-02-01 | 삼성전자주식회사 | Method for manufacturing gate of non volatile memory device |
| KR100859485B1 (en) * | 2006-09-12 | 2008-09-24 | 동부일렉트로닉스 주식회사 | Manufacturing Method of Flash Memory Device |
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