JP2001015587A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device by which roughness of side surfaces of a mask for forming an element pattern can be prevented so that a desired element shape can be formed uniformly and stably, and that the yield and reliability of the semiconductor device can be improved. SOLUTION: To smooth a mask aperture sidewall surface in a silicon nitride film 13 which has irregularities and grooves on side surfaces after patterned by using a photoresist, another silicon nitride film 45 is formed. All the silicon nitride film 45 on a region where a gate electrode of a polycrystalline silicon film 12 is not formed is removed to expose the polycrystalline silicon film 12. The silicon nitride film 45 remains only at a sidewall portion of the aperture of the silicon nitride film 13. These two silicon nitride films 13, 45 are used as a mask 46 to etch the polycrystalline silicon film 12. Thus, a gate electrode in a desired shape is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a fine processing technique for processing an element pattern through a mask material.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor devices, the precision of element pattern formation has become important. That is,
Since the precision of element pattern formation greatly affects, for example, the occurrence of a short channel effect in a MOS transistor and the insulating property of element isolation, high reliability is required for semiconductor processing technology.

The first type of semiconductor processing technology conventionally used is
First, a method of forming a gate electrode in a MOS transistor will be described.

FIGS. 23 to 27 are cross-sectional views sequentially showing the outline of a conventional process of manufacturing a gate electrode. First, as shown in FIG. 23, a silicon oxide film 11 serving as a gate insulating film is formed to a thickness of 10 nm on a silicon substrate 10 using a thermal oxidation technique, and a gate electrode is formed on the surface thereof using an LP-CVD technique. The polycrystalline silicon film 12 to be
A silicon nitride film 13 serving as a mask material for forming a gate electrode is sequentially formed to a thickness of 300 nm on the surface thereof. Next, as shown in FIG. 24, after applying a photoresist 14 to a thickness of about 800 nm on the entire surface, a mask of a desired gate electrode pattern is formed on the photoresist 14 by a lithography technique.
Then, as shown in FIG. 25, using the photoresist 14 as a mask, the silicon nitride film 13 is patterned using the RIE technique. Thereafter, as shown in FIG. 26, the photoresist 14 is removed using the asher technique. Next, FIG.
RIE using the silicon nitride film 13 as a mask
The polycrystalline silicon film 12 is patterned into a desired gate electrode shape by performing etching using a technique.

Conventionally, a gate electrode layer is manufactured by such a method. However, in a photoresist patterning process by a lithography technique shown in FIG.
In recent years, chemically amplified photoresists have been widely used. However, this chemically amplified photoresist has a problem that the acid contained in the photoresist material is locally shaded. Due to the non-uniformity of diffusion of the acid in the photoresist material, the photoresist after development may have irregularities on the surface, so-called surface roughness. Further, at the time of exposure, a standing wave may be generated due to interference between incident light applied to the photoresist and reflected light from the lower layer film, and this standing wave effect also causes the photoresist surface to be roughened. It is known. The surface roughness of the photoresist due to these factors causes deterioration of the etching resistance of the photoresist edge, and the like.
In etching the silicon nitride film 13 shown in FIG.
The unevenness of the photoresist side wall is enlarged, and minute vertical unevenness is transferred to the side surface of the silicon nitride film 13. In the patterning of the gate electrode shown in FIG. 27, polycrystalline silicon 12, which is a gate electrode material, is etched by using this silicon nitride film 13 as a mask material. The vertical streaks are transferred to the gate electrode side walls as they are.

FIG. 28 illustrates this problem.
29. FIG. 28 and 29 are plan views of the silicon nitride film 13 and the polycrystalline silicon 12 in FIG. 27 at positions corresponding to the lines aa 'and bb', respectively. Grooves may be formed in the above-described surface roughness of the photoresist, and the grooves formed on the sidewalls of the photoresist may include a silicon nitride film 13 patterned as shown in FIGS. 28 and 29 and a polycrystalline silicon film. Groove 1 on 12 sidewalls
5 is naturally transferred. Therefore, the length of the gate electrode 12 is locally changed by the groove 15 formed on the side wall of the patterned polycrystalline silicon film 12 as shown in FIG. 29, and the gate length 17 is shorter than the desired gate length 16.
Region occurs locally. The occurrence of such a region having a short gate length accelerates the short channel effect and the like, causing a problem that the performance as a semiconductor element is deteriorated and that the rate of miniaturization is determined.

Next, as a second example of semiconductor processing technology conventionally used, STI (Shallow Trench)
A method for forming an element isolation region using an (hIsolation) technique will be described.

FIGS. 30 to 40 are sectional views sequentially showing the outline of a conventional process of manufacturing an element isolation region using a silicon oxide film. First, as shown in FIG. 30, a silicon nitride film 21 having a thickness of 400 nm is formed on a silicon substrate 20 by LP-CVD technology to serve as a mask material when trenching the silicon substrate 20.
Next, as shown in FIG. 31, a photoresist 22 is applied on the entire surface to a thickness of about 800 nm, and a mask having a desired element isolation pattern is formed on the photoresist 22 by lithography. Then, using the photoresist 22 as a mask as shown in FIG. 32, the silicon nitride film 21 is etched by the RIE technique, and the photoresist 22 is removed by the asher technique as shown in FIG. Next, FIG.
As shown in FIG. 4, the silicon substrate 20 is etched by the RIE technique using the silicon nitride film 21 as a mask to form a trench 23 having a depth of 400 nm serving as an element isolation region.
To form Thereafter, as shown in FIG. 35, a silicon oxide film 24 is deposited to a thickness of 1 μm by the LP-CVD technique,
The aforementioned trench 23 is buried. Then, as shown in FIG. 36, the silicon oxide film 24 is cut and flattened by the CMP technique using the silicon nitride film 21 as a stopper. Thereafter, as shown in FIG. 37, the silicon nitride film 21 is removed by a wet etching technique. Further, as shown in FIG. 38, the silicon substrate 23 is formed by a wet etching technique.
The silicon oxide film 24 embedded in the trench 23 is etched to a thickness of about 50 nm to reduce a step between the surface of the silicon substrate 20 and the surface of the silicon oxide film 24 caused by the removal of the silicon nitride film 21 described above. The purpose of reducing this step is to improve a processing margin in forming a gate electrode later. Next, as shown in FIG. 39, a silicon oxide film 25 serving as a gate insulating film is formed to a thickness of 10 nm by using a dry oxidation technique, and thereafter, as shown in FIG. A polycrystalline silicon film 26 is deposited to a thickness of 200 nm.

Conventionally, an element isolation region is formed by the above-described steps. However, silicon as a mask material for forming a trench 23 in a silicon substrate 20 by a method similar to the first example described above. Since the photolithography technique is used for patterning the nitride film 21, fine vertical streaks and grooves or grooves are generated on the side wall of the opening of the mask of the formed silicon nitride film 21.
Is transferred directly to the trench side wall formed at the same time.

FIGS. 41 to 43 show this state.
It is. 41 and 42 show aa ′ of the silicon nitride film 21 and the silicon substrate 20 in FIG. 34, respectively.
It is a top view of a position corresponding to a line and a bb 'line. FIG.
The trench 27 formed in the silicon nitride film 21 as the mask material shown in FIG.
A region having an element formation region width 29 that is also present on the side wall and is smaller than a desired element formation region width 28 is locally generated. FIG.
FIG. 43 shows a longitudinal section at a position corresponding to the line cc ′ in FIG. 1, that is, a sectional view of a portion where the groove 27 exists. The narrowing of the element formation region can be clearly seen.
This causes, for example, a decrease in channel current when a MOS transistor is formed in the element formation region, causing a problem of deteriorating the performance as a semiconductor element.

Further, the trench 23 of the semiconductor substrate 20
In the step of embedding the silicon oxide film 24 with the silicon oxide film 24 by the LP-CVD technique, the portion of the groove 27 generated on the side wall of the trench 23 is a very narrow region. A phenomenon occurs in which the deposition of the silicon oxide film 24 proceeds while leaving a simple cavity. That is, the step coverage of the film becomes a problem in an extremely small area.

FIGS. 44 to 48 illustrate this state.
It is. 44 and 45 show aa ′ of the silicon nitride film 21 and the silicon substrate 20 in FIG. 35, respectively.
It is a top view of a position corresponding to a line and a bb 'line. FIG.
FIG. 46 shows a cross-sectional view at a position corresponding to the line cc ′ in FIG. 5, that is, a vertical cross-section of a portion where the cavity 30 exists. 47 and 48 are enlarged views of the cavity 30 of the silicon oxide film 24 formed in the silicon nitride film 21 and the groove 27 of the silicon substrate 20, respectively.

The silicon substrate 20 shown in FIG.
And silicon oxide film 2 which is a filling member of trench 23
In the step of shaving the silicon oxide film 24 by wet etching in order to reduce the step formed on the surface of No. 4, when the etching liquid enters the cavity 30 of the silicon oxide film 24 formed in the groove 27, the etching liquid is removed. The cavity 30 is enlarged by the etching action, causing a phenomenon that the shape of the element isolation region is broken. FIG. 49 shows a vertical cross section taken along the line cc ′ when the etchant enters the cavity 30 of FIG. 44 and etches the silicon oxide film 24 to enlarge the cavity 30. The shape of the element isolation region is destroyed. You can see that In this way, the enlargement of a minute cavity by wet etching involves making a hole in the insulating film in the element isolation region,
This causes a problem of deteriorating the insulation.

[0014]

As described above, in a conventional semiconductor processing technique such as formation of an element pattern, a process using a photoresist is indispensable to form a mask having a desired pattern. However, when exposing the photoresist, due to the non-uniformity of the acid in the photoresist material and the standing wave effect due to the interference of the irradiation light used for the exposure, etc., the surface of the side wall of the photoresist after patterning has a slight Unevenness occurs. As a result, minute vertical streak-like irregularities are also formed on the side wall surface of the opening of the mask material after processing, which causes side surface roughness of the element pattern.
In a semiconductor device that has been miniaturized in recent years, there is a problem that this side surface roughness leads to deterioration of element performance.

The present invention has been made in view of the above circumstances, and an object of the present invention is to suppress roughness of the side wall surface of an opening of a mask for forming an element pattern due to roughness of a side surface of a photoresist. Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which a desired element shape can be formed stably and uniformly, and the yield and reliability of the semiconductor device can be improved.

[0016]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a surface region to be patterned on a semiconductor substrate; and forming the surface region on the surface region. Forming a first insulating film to be a mask layer for patterning, patterning the first insulating film to form a mask layer having an opening, and removing a side wall surface of the opening of the formed mask layer. The method is characterized by including a step of smoothing and a step of patterning the surface region using a mask layer having a smoothed side wall surface of the opening.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the step of smoothing a sidewall surface of the opening of the mask layer includes the step of forming the mask layer having the opening formed therein. Depositing a second insulating film on the surface and in the opening, and etching the deposited second insulating film to remove the second insulating film on the surface region in the opening Exposing the surface region to be patterned by etching, wherein the etching process is performed so that the second insulating film deposited on the side wall surface of the opening is left.

According to the first aspect of the present invention, after the unevenness of the side wall of the patterned mask layer is smoothed, patterning of an element having a desired shape is performed using the mask layer. The shape can be stably and uniformly formed, and the yield and reliability of the semiconductor device can be easily improved.

Further, as a smoothing process, the second insulating film is applied to the side wall of the first insulating film serving as the mask layer, so that the surface of the side wall of the mask layer can be formed in a simple process. Can be smoothed.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

FIGS. 1 to 3 are views for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention. FIGS. ing. First, the structure shown in FIG. 26 is formed by the well-known technique of FIGS. That is, on a silicon substrate (semiconductor substrate) 10, a silicon oxide film 11,
A polycrystalline silicon film 12 and a silicon nitride film 13 are sequentially formed, and then the silicon nitride film 13 is patterned to form a mask. Next, as shown in FIG.
A silicon nitride film 45 is deposited again to a thickness of 30 nm by the technique, and covers the surface of the silicon nitride film mask 13, the mask side walls, and the polycrystalline silicon film 12 exposed at the bottom of the mask opening. Then, as shown in FIG. 2, the silicon nitride film 45 is etched back by the RIE technique to expose the polycrystalline silicon film 12. At this time, the silicon nitride film 45 is entirely removed from the region of the polycrystalline silicon film 12 where the gate electrode is not formed, and is left only on the side wall of the silicon nitride film 13. Using these two silicon nitride films 13 and 45 as a mask material 46, as shown in FIG. 3, the polycrystalline silicon film 12 is etched by RIE to form a gate electrode. The gate electrode width depends on the two silicon nitride films 13 and 45, but can be controlled with high accuracy by the thickness of the silicon nitride film 45 and the conditions for etching the silicon nitride film 45 by RIE.

Also in the case of this manufacturing method, a vertical line is formed on the side wall surface of the opening of the mask of the silicon nitride film 13 which constitutes a part of the mask material due to the side surface roughness generated upon exposure of the patterned photoresist. Although irregularities are formed, the mask material 4 is again formed on the side wall of the silicon nitride film 13.
By forming the silicon nitride film 45 constituting another part of 6, the roughness of the side surface of the polycrystalline silicon film 12 forming the mask material 46 and the gate electrode can be reduced. This situation will be described with reference to FIGS. 4 to 7 in the same manner as described in the related art.

FIGS. 4 and 5 are cross-sectional views of a process of etching the polycrystalline silicon film 12 using the mask material 46 to form a gate electrode, respectively. It is a top view of the position corresponding to the -b 'line. The surface roughness generated on the side wall of the photoresist causes a groove 47 to be formed on the side wall surface of the opening of the mask of the silicon nitride film 13, and when the silicon nitride film 45 is deposited by the LP-CVD technique which is the next step, the groove 47 is formed. As shown in FIG. 4, there is a possibility that a state in which a cavity 48 is formed between the silicon nitride films 13 and 45 in the groove 47 portion occurs. However, the silicon nitride film 13
By depositing the silicon nitride film 45 again on the side wall of the silicon nitride film 13, the influence of the groove 47 on the side wall of the silicon nitride film 13 can be neglected when the polycrystalline silicon film 12 is etched. The surface roughness of the side wall is reduced. Further, as shown in FIG. 5, a cavity 4 formed in a groove 47 portion between the silicon nitride films 13 and 45 is formed.
Since the region 8 is very narrow, the radical molecules do not sufficiently reach the cavity 48 when the polycrystalline silicon 42 is etched by the RIE technique, and the polycrystalline silicon film 12 below the cavity 48 is not etched. That is, this cavity 4
The presence of 8 has no effect on the formation of the gate electrode. 6 and 7 show the cavity 48 of the silicon nitride film shown in FIG.
5 and an enlarged view of a gate electrode side wall formed of the polycrystalline silicon film 12 not affected by the cavity 48 shown in FIG.

According to the above-described manufacturing method, the surface roughness of the side wall of the opening of the mask material 46 for the gate electrode can be reduced by forming the silicon nitride film 45 again on the side wall of the silicon nitride film 13. It is possible to suppress the side surface roughness of the element pattern due to the side surface roughness of the photoresist, thereby stably and uniformly forming a desired element shape.
The yield and reliability of the semiconductor device can be improved.

Next, as a second embodiment of the present invention,
A method for forming an element isolation region using the STI technique will be described with reference to FIGS.

FIGS. 8 to 16 are sectional views sequentially showing the outline of the steps of manufacturing an element isolation region using an oxide film. First,
After a patterned silicon nitride film 21 is formed on a silicon substrate 10 by the well-known technique of FIGS. 30 to 33 described in the related art, as shown in FIG. 30n by CVD technology
m, and covers the surface of the silicon nitride film mask 21, the side wall of the opening, and the surface of the silicon substrate 20 exposed in the opening. Next, as shown in FIG. 9, the silicon nitride film 53 is etched back by the RIE technique to expose the surface of the silicon substrate 20 in the mask opening again. At this time,
The silicon nitride film 53 on the region where the trench is not formed in the silicon substrate 20 is entirely removed to expose the silicon substrate 20 and remain only on the side wall of the mask opening of the silicon nitride film 21. Then, using the two silicon nitride films 21 and 53 as a mask material 54, the silicon substrate 20 is etched by the RIE technique to form a trench 55 having a depth of about 400 nm serving as an element isolation region as shown in FIG. The trench width is two silicon nitride films 2
Although it depends on 1 and 53, highly accurate control is possible by the thickness of the silicon nitride film 53 and the conditions for etching the silicon nitride film 53 by RIE. Next, as shown in FIG. 11, in order to fill the trench 55 formed earlier, a silicon oxide film 56 is
m. Then, the silicon oxide film 56 is shaved by the CMP technique, and the surface is flattened as shown in FIG. At this time, the silicon nitride films 21 and 53 function as stoppers. Thereafter, as shown in FIG. 13, the silicon nitride films 21 and 53 are removed by a wet etching technique, and in order to reduce a step formed between the surface of the silicon substrate 20 and the surface of the silicon oxide film 56 as shown in FIG. Then, the silicon oxide film 56 is etched to a thickness of about 50 nm again by the wet etching technique. The purpose of reducing the step between the silicon substrate 20 and the silicon oxide film 56 is to improve a processing margin in forming a gate electrode later. Next, as shown in FIG. 15, a silicon oxide film 57 serving as a gate insulating film is formed to a thickness of about 10 nm by a dry oxidation technique. Then, as shown in FIG. 16, a polycrystalline silicon film 58 serving as a gate electrode is deposited to a thickness of 200 nm by the LP-CVD technique.

According to this manufacturing method, the silicon nitride film 21 constituting a part of the mask material 54 is formed by the side surface roughness generated when the patterned photoresist is exposed.
Vertical stripe-shaped irregularities are formed on the surface of the opening side wall of the mask of FIG.
By forming the silicon nitride film 53 constituting another part of the fourth embodiment, the side surface roughness of the mask material 54 and the trench 55 can be reduced as in the first embodiment.

FIG. 10 is a sectional view showing a step of forming a trench for element isolation.
17 and 18, which are plan views of positions corresponding to the line bb ′, the surface roughness generated on the side wall of the photoresist causes a groove 59 on the side wall of the silicon nitride film 54,
The silicon nitride film 53 is formed by the next process, LP-CVD.
At the time of deposition, as shown in FIG. 17, the reaction gas does not sufficiently reach the groove 59, and a cavity 60 is formed between the silicon nitride films 21 and 53 in the groove 59. However, by depositing the silicon nitride film 53 again on the side wall of the silicon nitride film 21, the influence of the groove on the side wall of the silicon nitride film 21 can be neglected when the silicon substrate 20 is etched. The surface roughness of the side walls of the silicon nitride film 21 is alleviated, and the region of the cavity 60 formed between the silicon nitride films 21 and 53 is very narrow.
Since the radical molecules do not sufficiently reach the silicon substrate 20 and the silicon substrate 20 under the cavity 60 is not etched as shown in FIG. 18, the presence of the cavity 60 has no influence on the formation of the element isolation region.

Also, according to the manufacturing method of the present embodiment, the cavities generated in the silicon oxide film buried in the conventional trench and deteriorating the insulation are reduced in the unevenness of the trench side wall of the silicon substrate so that no sharp groove is formed. Does not occur because.

FIGS. 19 to 2 show this state.
2. FIGS. 19 and 20 are cross-sectional views of a step of embedding a trench 55 formed in the silicon substrate 20 with a silicon oxide film 56, and are respectively aa ′ in FIG.
FIG. 4 is a plan view of a position corresponding to the line bb ′, but no cavity is formed in the silicon oxide film 56 because the unevenness of the side wall of the mask material is reduced. 21 and 22 are enlarged views of FIGS. 19 and 20, respectively. FIG.
In the wet etching process of the silicon oxide film 56 for removing the silicon nitride films 21 and 53 as the mask material on the silicon substrate 20 shown in FIG. However, since the trenches are not present on the trench sidewalls due to the alleviation of the irregularities on the mask material sidewalls, no voids are formed in the silicon oxide film, and the element isolation shape is not disrupted. Therefore, the loss of the element formation region width due to the groove can be reduced, and a stable element isolation shape can be obtained.

According to the above-described manufacturing method, by forming the silicon nitride film 53 again on the side wall of the silicon nitride film 21, the surface roughness of the side wall of the mask material 54 for forming the trench can be alleviated. The side surface roughness of the element pattern due to the side surface roughness of the resist is suppressed, whereby a desired element shape can be stably and uniformly formed, and the yield and reliability of the semiconductor device can be improved.

In the above embodiment, the silicon nitride films 13 and 21 formed by the LP-CVD technique have been described as examples of the mask material for forming the element pattern.
Similar effects can be obtained by using a silicon oxide film formed by another technique such as a normal pressure CVD, a plasma CVD technique, or other materials, or a multilayer film of a different material. Also, an example has been described in which the gate electrode and the element isolation region are formed by processing the polycrystalline silicon film 12 and the silicon substrate 20, but the material to be processed is a high melting point material such as tungsten, a silicide film, an aluminum alloy. Low-resistance material such as metal wiring formation, contact holes,
Similar effects can be obtained by applying the present invention to plug formation and the like.

Further, the film thickness of each layer is not limited to the value described in the embodiment. In particular, the film thickness of the silicon nitride films 45 and 53 depends on the relationship with etching conditions by RIE to obtain desired gate width and trench width. Is determined by The thickness of the silicon nitride films 45 and 53 for embedding the grooves depends on the size of the grooves, but generally needs to be about 10 nm or more, and is limited in a direction in which the thickness does not affect the element size. Is not received.

When forming a trench in a semiconductor substrate, as a modification of the mask layer smoothing technique, instead of forming a silicon nitride film 53 to alleviate the roughness of the side wall of the mask material 54, a silicon nitride film is formed. For example, there is a method in which the surface of the silicon nitride film 21 is smoothed by wet etching the surface of the silicon nitride film 21 with, for example, warmed phosphoric acid. With this method, it is also possible to avoid generating a cavity in the silicon oxide film 56 filling the trench, and the same effect as in the above embodiment can be obtained.

[0035]

As described above, according to the present invention, the side surface roughness of the mask for forming an element pattern due to the side surface roughness of the photoresist is suppressed by a relatively simple process, thereby stabilizing a desired element shape. And a semiconductor device manufacturing method capable of improving the yield and reliability of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a first embodiment of the present invention, showing a first manufacturing step of forming a gate electrode using a MOS transistor as an example.

FIG. 2 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a second manufacturing step of forming a gate electrode using a MOS transistor as an example.

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a third manufacturing step of forming a gate electrode using a MOS transistor as an example.

FIG. 4 is a diagram for explaining the effect of the method for manufacturing a semiconductor device according to the first embodiment of the present invention;
5 is a plan view of a position corresponding to the line aa ′ in FIG.

FIG. 5 is a diagram for explaining the effect of the method for manufacturing a semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a plan view of a position corresponding to the line bb ′ in FIG.

FIG. 6 is a diagram for explaining the effect of the method for manufacturing a semiconductor device according to the first embodiment of the present invention;
An enlarged view of FIG.

FIG. 7 is a diagram for explaining the effect of the method for manufacturing a semiconductor device according to the first embodiment of the present invention;
An enlarged view of FIG.

FIG. 8 is a sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention and illustrating a first manufacturing step of forming an element isolation region.

FIG. 9 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention, showing a second manufacturing step of forming an element isolation region.

FIG. 10 is a sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention and illustrating a third manufacturing step of forming an element isolation region.

FIG. 11 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention, showing a fourth manufacturing step of forming an element isolation region.

FIG. 12 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention, showing a fifth manufacturing step of forming an element isolation region.

FIG. 13 is a sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention and illustrating a sixth manufacturing step of forming an element isolation region.

FIG. 14 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention and illustrating a seventh manufacturing step of forming an element isolation region.

FIG. 15 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention, showing an eighth manufacturing step of forming an element isolation region.

FIG. 16 is a sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention and illustrating a ninth manufacturing step of forming an element isolation region.

FIG. 17 is a plan view for explaining the effect of the method for manufacturing a semiconductor device according to the second embodiment of the present invention, which is at a position corresponding to the line aa ′ in FIG. 10;

FIG. 18 is a plan view for explaining the effect of the method for manufacturing a semiconductor device according to the second embodiment of the present invention, which is at a position corresponding to line bb ′ in FIG. 10;

FIG. 19 is a plan view for explaining the effect of the method for manufacturing a semiconductor device according to the second embodiment of the present invention, which is at a position corresponding to the line aa ′ in FIG. 11;

FIG. 20 is a plan view for explaining the effect of the method for manufacturing the semiconductor device according to the second embodiment of the present invention, which is at a position corresponding to line bb ′ in FIG. 11;

FIG. 21 is an enlarged view of FIG. 19 for describing the effect of the method for manufacturing a semiconductor device according to the second embodiment of the present invention;

FIG. 22 is an enlarged view of FIG. 20 for describing the effect of the method for manufacturing a semiconductor device according to the second embodiment of the present invention;

FIG. 23 is a cross-sectional view for explaining the conventional method for manufacturing a semiconductor device related to a MOS transistor, and illustrating a first manufacturing step in forming a gate electrode.

FIG. 24 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device related to a MOS transistor and illustrating a second manufacturing step in forming a gate electrode.

FIG. 25 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device related to a MOS transistor, and illustrating a third manufacturing step in forming a gate electrode.

FIG. 26 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device related to a MOS transistor and illustrating a fourth manufacturing step in forming a gate electrode.

FIG. 27 is a cross-sectional view for explaining the conventional method for manufacturing a semiconductor device relating to a MOS transistor and showing a fifth manufacturing step in forming a gate electrode.

FIG. 28 is a plan view of a position corresponding to the line aa ′ in FIG. 27 for describing a problem of the conventional method of manufacturing a semiconductor device relating to a MOS transistor.

FIG. 29 is a plan view of a position corresponding to the line bb ′ in FIG. 27 for describing a problem of a conventional method of manufacturing a semiconductor device relating to a MOS transistor.

FIG. 30 is a cross-sectional view for explaining the conventional method for manufacturing the semiconductor device and showing a first manufacturing step for forming an element isolation region.

FIG. 31 is a cross-sectional view for explaining the conventional method for manufacturing the semiconductor device and showing a second manufacturing step for forming an element isolation region.

FIG. 32 is a cross-sectional view for explaining the conventional method for manufacturing the semiconductor device and showing a third manufacturing step for forming an element isolation region.

FIG. 33 is a cross-sectional view for explaining the conventional method for manufacturing the semiconductor device and showing a fourth manufacturing step for forming an element isolation region.

FIG. 34 is a cross-sectional view for explaining the conventional method for manufacturing the semiconductor device and showing a fifth manufacturing step for forming an element isolation region.

FIG. 35 is a cross-sectional view for explaining the conventional method for manufacturing the semiconductor device and showing a sixth manufacturing step for forming an element isolation region.

FIG. 36 is a cross-sectional view for explaining the conventional method for manufacturing the semiconductor device and illustrating a seventh manufacturing step for forming an element isolation region.

FIG. 37 is a cross-sectional view for explaining the conventional method for manufacturing the semiconductor device and illustrating an eighth manufacturing step for forming an element isolation region.

FIG. 38 is a cross-sectional view for explaining the conventional method for manufacturing the semiconductor device and showing a ninth manufacturing step for forming an element isolation region.

FIG. 39 is a cross-sectional view for explaining the conventional method for manufacturing the semiconductor device and showing a tenth manufacturing step for forming an element isolation region.

FIG. 40 is a cross-sectional view for explaining the conventional method for manufacturing the semiconductor device and showing an eleventh manufacturing step for forming an element isolation region.

FIG. 41 is a plan view of a position corresponding to the line aa ′ in FIG. 34 for describing a problem of the conventional method of manufacturing a semiconductor device.

42 is a plan view of a position corresponding to the line bb ′ in FIG. 34 for describing a problem of the conventional method of manufacturing a semiconductor device.

FIG. 43 is a longitudinal sectional view at a position corresponding to the line cc ′ in FIG. 41 for describing a problem of the conventional method of manufacturing a semiconductor device.

FIG. 44 is a plan view of a position corresponding to the line aa ′ in FIG. 35 for describing the problem of the conventional method of manufacturing a semiconductor device.

45 is a plan view of a position corresponding to the line bb ′ in FIG. 35 for describing a problem of the conventional method of manufacturing a semiconductor device.

FIG. 46 is a longitudinal sectional view at a position corresponding to the line cc ′ in FIG. 44 for describing a problem of the conventional method of manufacturing a semiconductor device.

FIG. 47 is an enlarged view of FIG. 44 for describing a problem of a conventional method of manufacturing a semiconductor device.

FIG. 48 is an enlarged view of FIG. 45 for explaining a problem of a conventional method of manufacturing a semiconductor device.

FIG. 49 is a longitudinal sectional view at a position corresponding to line cc ′ in FIG. 44 for describing a problem of the conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 10, 20 ... silicon substrate 11, 24, 25, 56, 57 ... silicon oxide film 12, 26, 58 ... polycrystalline silicon film 13, 21, 45, 53 ... silicon nitride film 14, 22 ... photoresist 15, 27, 47, 59: groove 16: desired gate length 17: gate length changed by influence of groove 23, 55: trench 28: desired element formation region width 29: element formation region width changed by influence of groove 30: silicon oxide Cavities generated in the film 46, 54: Mask material 48, 60: Cavity generated between silicon nitride films

Claims (2)

[Claims] A step of forming a surface region to be patterned on a semiconductor substrate; a step of forming a first insulating film serving as a mask layer for patterning the surface region on the surface region; Forming a mask layer having an opening by patterning an insulating film; smoothing a sidewall surface of the opening of the formed mask layer; and using the mask layer having a smoothed sidewall surface of the opening. Performing a patterning of the surface region. 2. The step of smoothing the surface of the side wall of the opening of the mask layer, the step of:
Applying the insulating film, and etching the applied second insulating film to remove the second insulating film applied to the surface region in the opening and the surface to be patterned Exposing a region, wherein the etching is performed on a second side surface of the side wall of the opening.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed such that the insulating film is left.