KR100516771B1 - Method of forming gate electrode in semiconductor device - Google Patents
Method of forming gate electrode in semiconductor device Download PDFInfo
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- KR100516771B1 KR100516771B1 KR10-2003-0049040A KR20030049040A KR100516771B1 KR 100516771 B1 KR100516771 B1 KR 100516771B1 KR 20030049040 A KR20030049040 A KR 20030049040A KR 100516771 B1 KR100516771 B1 KR 100516771B1
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- hard mask
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 238000000059 patterning Methods 0.000 claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 게이트 전극 형성방법에 관한 것으로, 게이트 식각 공정시에 포토레지스트 패턴에 의해 패터닝된 질화막을 이용하여 하부층인 하드 마스크층에 언더 컷이 생기도록 하드 마스크층을 패터닝하고, 포토레지스트 패턴의 크기보다 작은 크기를 갖는 패터닝된 하드 마스크층을 이용하여 폴리실리콘층을 패터닝하므로, 포토 공정에 의한 패턴 크기보다 작은 게이트 전극을 형성할 수 있어, 기존의 노광 장비를 가지고도 소자의 고집적화를 실현할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode of a semiconductor device, wherein a hard mask layer is patterned so that an undercut is formed in a lower hard mask layer using a nitride film patterned by a photoresist pattern during a gate etching process, and a photoresist is formed. By patterning the polysilicon layer using a patterned hard mask layer having a size smaller than the size of the pattern, a gate electrode smaller than the size of the pattern by the photo process can be formed, thereby achieving high integration of the device even with existing exposure equipment. It can be realized.
Description
본 발명은 반도체 소자의 게이트 전극 형성방법에 관한 것으로, 특히 포토 공정의 패턴 사이즈보다 작은 게이트 전극을 형성할 수 있는 반도체 소자의 게이트 전극 형성방법에 관한 것이다.The present invention relates to a method of forming a gate electrode of a semiconductor device, and more particularly to a method of forming a gate electrode of a semiconductor device capable of forming a gate electrode smaller than the pattern size of a photo process.
반도체 소자가 고집적화 되어감에 따라 게이트 전극의 선폭은 계속하여 감소하고 있다. 하지만 게이트 전극의 선폭 감소를 위해서는 제고 공정 중에 많은 요구 사항이 충족되어야 하며, 특히 포토 공정의 미세 패터닝 능력이 절실히 요구되어진다. 이를 위해 ArF를 이용한 고해상도 노광 장비가 등장하고 있지만, 장비 개발의 한계성으로 인해 게이트 전극의 선폭 감소 추세를 모두 만족시킬 수 없다.As semiconductor devices become more integrated, the line width of gate electrodes continues to decrease. However, in order to reduce the line width of the gate electrode, many requirements must be met during the manufacturing process, and in particular, the fine patterning capability of the photo process is urgently required. For this purpose, high-resolution exposure equipment using ArF has emerged, but due to the limitation of equipment development, it is impossible to satisfy all the trends of decreasing the line width of the gate electrode.
도 1a 내지 1c는 종래 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of a device for explaining a gate electrode forming method of a conventional semiconductor device.
도 1a를 참조하면, 소자분리 공정 및 웰 형성 공정을 실시한 반도체 기판(11) 상에 게이트 산화막(12) 및 폴리실리콘층(13)을 형성한다.Referring to FIG. 1A, a gate oxide film 12 and a polysilicon layer 13 are formed on a semiconductor substrate 11 on which a device isolation process and a well formation process are performed.
도 1b를 참조하면, 게이트 패턴을 형성하기 위해 포토레지스트 도포, 노광, 현상 공정을 진행하여 폴리실리콘층(13) 상에 포토레지스트 패턴(14)을 형성한다. 이때, 소자의 집적도가 점점 증가하여 포토 공정의 미세 패터닝 기술이 요구되며, 이를 위해 ArF를 이용한 고해상도 노광 장비가 등장하고 있지만, 장비 개발의 한계성으로 인해 포토레지스트 패턴(14)의 크기를 줄이는데 한계가 있다.Referring to FIG. 1B, a photoresist pattern 14 is formed on the polysilicon layer 13 by performing photoresist coating, exposure, and development processes to form a gate pattern. At this time, the degree of integration of the device is gradually increased, and fine patterning technology of the photo process is required. For this, high-resolution exposure equipment using ArF has emerged. However, due to the limitation of the development of the device, there is a limit to reducing the size of the photoresist pattern 14. have.
도 1c를 참조하면, 포토레지스트 패턴(14)을 식각 마스크로 한 게이트 식각 공정으로 폴리실리콘층(13)의 노출된 부분을 제거하여 게이트 전극(130)을 형성한다. 게이트 식각 공정은 Cl2 가스 및 HBr 가스를 주로 사용하며, 소자 집적도가 증가하면서 게이트 산화막(12)의 두께 또한 감소하기 때문에 산화물과의 높은 선택비를 갖는 HeO2 가스가 적용되고 있다.Referring to FIG. 1C, the gate electrode 130 is formed by removing the exposed portion of the polysilicon layer 13 by a gate etching process using the photoresist pattern 14 as an etching mask. The gate etching process mainly uses Cl 2 gas and HBr gas, and since the thickness of the gate oxide film 12 decreases as the device density increases, a HeO 2 gas having a high selectivity with oxide is applied.
상기한 바와 같이, 종래 방법으로는 게이트 포토 공정의 노광장비의 한계성으로 미세 선폭 예를 들어 0.1 ㎛ 이하의 게이트 전극 선폭을 갖는 고집적 소자를 구현할 수 없다.As described above, the conventional method cannot implement a highly integrated device having a fine line width, for example, a gate electrode line width of 0.1 μm or less due to the limitation of the exposure equipment of the gate photo process.
따라서, 본 발명은 포토 공정의 패턴 사이즈보다 작은 게이트 전극을 용이하게 형성할 수 있어, 소자의 신뢰성을 향상시킬 뿐만 아니라 소자의 고집적화 실현을 가능하게 하는 반도체 소자의 게이트 전극 형성방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for forming a gate electrode of a semiconductor device, which can easily form a gate electrode smaller than the pattern size of a photo process, thereby improving the reliability of the device and enabling high integration of the device. There is this.
이러한 목적을 달성하기 위한 본 발명의 실시예에 따른 반도체 소자의 게이트 전극 형성방법은 반도체 기판 상에 게이트 산화막 및 폴리실리콘층을 형성하는 단계; 상기 폴리실리콘층 상에 하드 마스크층 및 희생막을 형성하는 단계; 포토레지스트 패턴을 이용한 식각 공정으로 상기 희생막을 패터닝하는 단계; 상기 패터닝된 희생막을 식각 장벽으로한 식각 공정으로 상기 하드 마스크층을 패터닝하되, 언더 컷이 생기도록 하는 단계; 상기 패터닝된 희생막을 제거하는 단계; 상기 패터닝된 하드 마스크층을 식각 마스크로 한 게이트 식각 공정으로 상기 폴리실리콘층을 패터닝하는 단계; 및 상기 패터닝된 하드 마스크층을 제거하는 단계를 포함한다.A method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention for achieving the above object comprises the steps of forming a gate oxide film and a polysilicon layer on a semiconductor substrate; Forming a hard mask layer and a sacrificial layer on the polysilicon layer; Patterning the sacrificial layer by an etching process using a photoresist pattern; Patterning the hard mask layer by an etching process using the patterned sacrificial layer as an etch barrier, thereby causing an undercut to occur; Removing the patterned sacrificial layer; Patterning the polysilicon layer by a gate etching process using the patterned hard mask layer as an etching mask; And removing the patterned hard mask layer.
상기에서, 하드 마스크층과 상기 희생막은 상호 식각 선택비가 높은 물질로 각각 형성하는데, 상기 하드 마스크층은 산화물 계통의 물질로 형성하며, 상기 희생막은 질화물 계통의 물질로 형성한다.The hard mask layer and the sacrificial layer are each formed of a material having a high etch selectivity. The hard mask layer is formed of an oxide-based material, and the sacrificial layer is formed of a nitride-based material.
상기 하드 마스크층은 희석된 HF 용액이나 BOE 용액을 이용한 습식 식각 방식으로 패터닝하고, 제거한다.The hard mask layer is patterned and removed by a wet etching method using diluted HF solution or BOE solution.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써, 본 발명을 상세하게 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information.
도 2a 내지 2e는 본 발명의 실시예에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 소자의 단면도이다.2A through 2E are cross-sectional views of devices for describing a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 소자분리 공정 및 웰 형성 공정을 실시한 반도체 기판(21) 상에 게이트 산화막(22) 및 폴리실리콘층(23)을 형성한다. 폴리실리콘층(23) 상에 하드 마스크층(210) 및 희생막(220)을 형성한다.Referring to FIG. 2A, a gate oxide film 22 and a polysilicon layer 23 are formed on a semiconductor substrate 21 on which a device isolation process and a well formation process are performed. The hard mask layer 210 and the sacrificial layer 220 are formed on the polysilicon layer 23.
상기에서 하드 마스크층(210)과 희생막(220)은 상호 식각 선택비가 높은 물질로 각각 형성하여야 한다. 즉, 하드 마스크층(210)은 산화물 계통의 물질로 형성하며, 게이트 식각 공정시 식각 마스크 역할을 하며, 따라서 폴리실리콘층(23)과의 선택비를 고려하여 최소한의 두께로 예를 들어, 400 Å 이하의 두께, 바람직하게는 300 ~ 400 Å의 두께로 형성한다. 희생막(220)은 하드 마스크층(210)과의 식각 선택비가 큰 질화물 계통의 물질로 형성하며, 후속 공정시 하드 마스크층(210)의 언더-컷(under cut) 형성시 식각 장벽(etch barrier) 역할을 한다.The hard mask layer 210 and the sacrificial layer 220 should be formed of a material having a high etch selectivity. That is, the hard mask layer 210 is formed of an oxide-based material, and serves as an etching mask in the gate etching process, and thus, for example, has a minimum thickness in consideration of the selectivity with the polysilicon layer 23. It is formed to a thickness of less than or equal to, preferably, 300 to 400 mm. The sacrificial layer 220 is formed of a nitride-based material having a large etching selectivity with respect to the hard mask layer 210, and an etch barrier when an under cut of the hard mask layer 210 is formed in a subsequent process. ) Plays a role.
도 2b를 참조하면, 게이트 패턴을 형성하기 위해 포토레지스트 도포, 노광, 현상 공정을 진행하여 희생막(220) 상에 포토레지스트 패턴(24)을 형성한다. 이때, 포토레지스트 패턴(24)은 기존과 동일한 크기로 형성한다.Referring to FIG. 2B, a photoresist pattern 24 is formed on the sacrificial layer 220 by performing photoresist coating, exposure, and development processes to form a gate pattern. At this time, the photoresist pattern 24 is formed to the same size as the conventional.
도 2c를 참조하면, 포토레지스트 패턴(24)을 식각 마스크로 한 식각 공정으로 희생막(220)을 패터닝하고, 포토레지스트 패턴(24)을 제거한다. 이후 세정 공정을 진행하여 웨이퍼를 클리닝(cleaning)한다.Referring to FIG. 2C, the sacrificial layer 220 is patterned by an etching process using the photoresist pattern 24 as an etching mask, and the photoresist pattern 24 is removed. Thereafter, the cleaning process is performed to clean the wafer.
상기에서, 희생막(220)은 질화물 계통의 물질로 형성하며, CF4/CHF3 가스를 이용한 건식 식각 방식으로 패터닝한다. 포토레지스트 패턴(24)은 O2 플라즈마를 이용하여 제거한다.In the above, the sacrificial layer 220 is formed of a nitride-based material, and patterned by a dry etching method using CF 4 / CHF 3 gas. The photoresist pattern 24 is removed using an O 2 plasma.
도 2d를 참조하면, 패터닝된 희생막(220)을 식각 장벽으로한 식각 공정으로 하부층인 하드 마스크층(210)을 패터닝하되, 언더 컷이 생기도록 하여 패터닝된 희생막(220)의 크기보다 작은 패터닝된 하드 마스크층(210)을 형성한다.Referring to FIG. 2D, the hard mask layer 210 is patterned by an etching process using the patterned sacrificial layer 220 as an etch barrier, and the undercut is formed to be smaller than the size of the patterned sacrificial layer 220. The patterned hard mask layer 210 is formed.
상기에서, 패터닝된 하드 마스크층(210)을 형성하기 위한 식각 공정은 희석된(dilute) HF 용액이나 BOE(buffer oxide etchant) 용액을 이용한 습식 식각 방식으로 진행한다. 언더 컷의 깊이는 식각 시간에 비례하는데, 원하는 게이트 전극의 임계치수(critical dimension; CD) 조절은 식각 시간을 조절함으로 이루어질 수 있다.The etching process for forming the patterned hard mask layer 210 is performed by a wet etching method using a dilute HF solution or a buffer oxide etchant (BOE) solution. The depth of the undercut is proportional to the etching time, and the adjustment of the critical dimension (CD) of the desired gate electrode can be achieved by adjusting the etching time.
도 2e를 참조하면, 패터닝된 희생막(220)을 제거하고, 포토 공정의 패턴 사이즈보다 작게 패터닝된 하드 마스크층(210)을 식각 마스크로 한 게이트 식각 공정으로 폴리실리콘층(23)의 노출된 부분을 제거하여 미세 선폭의 게이트 전극(230)을 형성한다. 이후, 패터닝된 하드 마스크층(210)을 제거한다.Referring to FIG. 2E, the patterned sacrificial layer 220 is removed, and the polysilicon layer 23 is exposed by a gate etching process using the hard mask layer 210 patterned as an etching mask smaller than the pattern size of the photo process. The portion is removed to form the gate electrode 230 having a fine line width. Thereafter, the patterned hard mask layer 210 is removed.
상기에서, 패터닝된 희생막(220)은 가열된(hot) H3PO4 용액을 이용한 습식 식각 방식으로 제거한다. 게이트 식각 공정은 Cl2 가스 및 HBr 가스를 주로 사용하며, 소자 집적도가 증가하면서 게이트 산화막(22)의 두께 또한 감소하기 때문에 산화물과의 높은 선택비를 갖는 HeO2 가스를 첨가한다. 하드 마스크층(210)은 희석된(dilute) HF 용액이나 BOE(buffer oxide etchant) 용액을 이용한 습식 식각 방식으로 제거한다.In the above, the patterned sacrificial layer 220 is removed by a wet etching method using a hot H 3 PO 4 solution. The gate etching process mainly uses Cl 2 gas and HBr gas, and adds a HeO 2 gas having a high selectivity to oxide because the thickness of the gate oxide film 22 also decreases as the device density increases. The hard mask layer 210 is removed by a wet etching method using a dilute HF solution or a buffer oxide etchant (BOE) solution.
상기한 본 발명의 실시예에 의한 게이트 전극 형성방법은 패터닝된 하드 마스크층(210)의 임계치수 감소로 인해 최종 게이트 전극(230)의 길이가 포토 공정의 패턴 사이즈 보다 감소하게 된다.In the gate electrode forming method according to the embodiment of the present invention, the length of the final gate electrode 230 is reduced than the pattern size of the photo process due to the reduction of the critical dimension of the patterned hard mask layer 210.
상술한 바와 같이, 본 발명은 게이트 포토 공정에서 정의된 게이트 길이보다 작은 게이트 전극 길이를 갖는 소자를 제조할 수 있고, 포토 공정에서 미세 게이트 패터닝을 위한 고해상도 노광장비 개발에 있어 시간적인 마진을 확보할 수 있으며, 기존 장비로도 미세 게이트 패터닝을 가능하게 하여 반도체 소자의 집적도를 향상시킬 수 있으며, 하드 마스크층의 언더컷 공정으로 인해 포토 공정에서 정의된 임계치수 보다 작은 임계치수의 구현이 가능해져 추가 응용 공정에 적용할 수 있다.As described above, the present invention can manufacture a device having a gate electrode length smaller than the gate length defined in the gate photo process, and secure a time margin in developing high resolution exposure equipment for fine gate patterning in the photo process. It is possible to improve the integration of semiconductor devices by enabling fine gate patterning even with existing equipment, and the undercut process of the hard mask layer enables the implementation of a critical dimension smaller than the critical dimension defined in the photo process. Applicable to the process.
도 1a 내지 1c는 종래 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a gate electrode forming method of a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 소자의 단면도.2A to 2E are cross-sectional views of a device for explaining a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11, 21: 반도체 기판 12, 22: 게이트 산화막11, 21: semiconductor substrate 12, 22: gate oxide film
13, 23: 폴리실리콘층 130, 230: 게이트 전극13, 23: polysilicon layer 130, 230: gate electrode
14, 24: 포토레지스트 패턴 210: 하드 마스크층14 and 24: photoresist pattern 210: hard mask layer
220: 희생막220: sacrifice
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