KR20100076763A - Method for fabricating fine pattern in semiconductor device - Google Patents

Method for fabricating fine pattern in semiconductor device Download PDF

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Publication number
KR20100076763A
KR20100076763A KR1020080134922A KR20080134922A KR20100076763A KR 20100076763 A KR20100076763 A KR 20100076763A KR 1020080134922 A KR1020080134922 A KR 1020080134922A KR 20080134922 A KR20080134922 A KR 20080134922A KR 20100076763 A KR20100076763 A KR 20100076763A
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KR
South Korea
Prior art keywords
thin film
etching
pattern
spacer
semiconductor device
Prior art date
Application number
KR1020080134922A
Other languages
Korean (ko)
Inventor
김명옥
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080134922A priority Critical patent/KR20100076763A/en
Publication of KR20100076763A publication Critical patent/KR20100076763A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE: A fine pattern manufacturing method of a semiconductor device is provided to form a fine pattern of a resolution for the exposure device by using a spacer. CONSTITUTION: A first thin film, a second thin film, and a third thin film are successively formed on a etch target layer(201). A sacrificial layer pattern is formed on the third thin film by the photo lithography process. A spacer(203A) is formed on a sidewall of the sacrificial layer pattern. The sacrificial layer pattern is removed. A third thin film on a part exposed by the removal of the sacrificial layer pattern is etched.

Description

METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a fine pattern of a semiconductor device.

As is well known, according to the high integration of semiconductor devices, finer pattern is essential. However, patterns required for the implementation of semiconductor devices, such as line and space patterns (hereinafter referred to as L / S patterns), are difficult to form fine patterns due to the resolution limitation of photolithography equipment.

Various semiconductor processes have been proposed to overcome the resolution limitation of such equipment, and one of them is a method using a spacer.

That is, by forming a spacer through deposition of a thin film on a predetermined pattern sidewall and etching the spacer, and then using the spacer as an etching mask, a technique is proposed to overcome the resolution limitation of the exposure equipment.

However, a spacer formed by deposition of a thin film and spacer etching has an asymmetrical shape. Here, the spacer etching means full anisotropic etching.

FIG. 1 is a photograph of a substrate in which a spacer is formed, and as shown in FIG. 1, the widths of spaces formed on the left and right sides of the spacer have different asymmetry.

Due to this difference, when the subsequent lower etching layer is etched, the large open width has a relatively strong etching bias, so that the final pattern formed by etching the etching layer is also asymmetric.

In addition, due to the asymmetry of the spacer, a bridge problem due to the scum of the photoresist occurs in a process such as pad opening.

The present invention has been proposed to solve the problems of the prior art, and provides a method of manufacturing a fine pattern of a semiconductor device that performs the manufacture of a fine pattern using a spacer, and also solves the problem of asymmetry of the pattern according to the use of the spacer. The purpose is.

In order to achieve the above object, a method of manufacturing a fine pattern may include: sequentially stacking a first thin film, a second thin film, and a third thin film on an etching target layer; Forming a sacrificial layer pattern on the third thin film by a photolithography process; Forming a spacer on sidewalls of the sacrificial layer pattern; Removing the sacrificial layer pattern; Etching the third thin film in a portion exposed by removing the sacrificial layer pattern; Etching the second thin film in a portion exposed by the etching of the third thin film; Removing spacers remaining on the second thin film by over etching; Etching the first thin film and the etching target layer of the portion exposed by the etching of the second thin film.

Preferably, the first thin film, the second thin film, and the third thin film are materials having different etching rates. In addition, the first thin film and the third thin film may be formed of materials having similar etching rates to each other, and the second thin film may be formed of materials having different etching rates from those of the first and third thin films.

In the improved fine pattern forming method, a spacer is formed on the first, second and third thin films of three layers, and an etch mask pattern is formed of the three layer thin film using the spacer as an etch mask. In addition, the etching mask pattern of the three-layer thin film is formed in a symmetrical pattern different from the spacer.

As a result, while forming a fine pattern beyond the resolution of the exposure equipment by using the spacer, the problem of asymmetry of the pattern according to the use of the spacer can be caused.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2A to 2I are cross-sectional views illustrating a method of manufacturing a fine pattern of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, a first thin film 202, a second thin film 203, and a third thin film 204 are stacked on the etching target layer 201. Subsequently, the sacrificial layer 205 and the BARC (Bottom Anti Reflection Coating) layer 206 are formed, and a photoresist pattern 207 is formed.

Importantly, the first thin film 202 and the third thin film 204 may be thin films having the same etching rate, but the second thin film 203 should be formed of a heterogeneous thin film having different etching rates from the first and third thin films 202 and 204.

To this end, the first, second and third thin films may be formed of an oxide, nitride, oxynitride, amorphous carbon layer, polysilicon, or the like. For example, the first and third thin films are oxide films, and the second thin film uses polysilicon. Alternatively, the first and third thin films may be used as the nitride film, and the second thin film may use an oxide film.

The photoresist pattern 207 determines the line width of the pattern based on the resolution of the equipment. The space between the adjacent photoresist patterns 207 may be formed to have a size about three times the line width of the photoresist pattern 207. This is for subsequent spacers formed.

In the present exemplary embodiment, the thin film under the first thin film 202 is described as the etching target layer 201, but the etching target layer 201 may be a hard mask in the semiconductor device manufacturing process. In this case, an etching target layer exists as a hard mask lower layer.

Subsequently, as illustrated in FIG. 2B, the sacrificial layer 205 is etched using the photoresist pattern 207 as an etching barrier, thereby forming the sacrificial layer pattern 205A. When the sacrificial layer 205 is etched, the etch stop occurs in the third thin film 204.

During the etching of the sacrificial layer 205, both the photoresist pattern 207 and the BARC layer 206 are lost. Further cleaning may be performed to remove debris from the photoresist pattern 207 and BARC layer 206.

Next, as shown in FIG. 2C, a thin film 208 for spacers is formed on the entire surface of the substrate on which the sacrificial pattern 205A is formed. It is preferable to use the thin film 208 for spacers as a thin film from which an etching rate differs from another adjacent thin film.

In addition, the deposition of the thin film 208 for the spacer may be formed using a deposition method with good step coverage.

Subsequently, spacer etching is performed to form spacers 208A on sidewalls of the sacrificial layer pattern 205A, as shown in FIG. 2D.

It is preferable to perform sufficient over etching so that no residues remain during the etching of the spacer, and the third thin film 204 and the lower second thin film 203 exposed by the over etching are partially lost.

Next, the sacrificial layer pattern 205A is removed as shown in FIG. 2E. Removal of the sacrificial layer pattern 205A may be accomplished using a dry method such as a plasma strip or wet using a chemical solution. It is also possible to use a mixing method thereof.

Next, FIG. 2F is a state in which the third thin film 204 exposed by removing the sacrificial layer pattern 205A is etched. As a result, a third thin film pattern 204A is formed. In the etching process, the exposed portions of the spacer 208A and the second thin film 203 are partially lost.

Next, as illustrated in FIG. 2G, the second thin film 203 is etched to stop the etching in the first thin film 202. As a result, the second thin film pattern 203A is formed.

On the other hand, spacer 208A is partially lost at this stage but still remains.

Next, FIG. 2H illustrates a state in which the over etch is performed to remove the spacer 208A of the asymmetric shape remaining after the etching of the second thin film 203.

In this case, since the third thin film pattern 204A is a thin film having an etching rate different from that of the second thin film 203, the asymmetry problem caused by the deformation of the third thin film pattern 204A does not occur.

Subsequently, as illustrated in FIG. 2I, the exposed first thin film 202 is etched to form a second thin film pattern 202A, and the etching target layer 201 is continuously etched to form a recess 209.

As described above, the method for forming a fine pattern according to the exemplary embodiment of the present invention may form a fine pattern having a resolution higher than that of exposure equipment using a spacer, and may also cause asymmetry of the pattern according to the use of the spacer.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a photograph showing that the asymmetry of the pattern occurs when producing a fine pattern using a spacer.

2A to 2I are cross-sectional views illustrating a method of manufacturing a fine pattern of a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

201: etching target layer 202A: first thin film pattern

203A: Second Thin Film Pattern 204A: Third Thin Film Pattern

205A: sacrificial layer pattern 206: BARC layer

207: photoresist pattern 208A: spacer

209 recess

Claims (5)

Sequentially stacking a first thin film, a second thin film, and a third thin film on the etching target layer; Forming a sacrificial layer pattern on the third thin film by a photolithography process; Forming a spacer on sidewalls of the sacrificial layer pattern; Removing the sacrificial layer pattern; Etching the third thin film in a portion exposed by removing the sacrificial layer pattern; Etching the second thin film in a portion exposed by the etching of the third thin film; Removing spacers remaining on the second thin film by over etching; Etching the first thin film and the etch target layer of a portion exposed by the etching of the second thin film. Method for producing a fine pattern of a semiconductor device. The method of claim 1, The first thin film, the second thin film, and the third thin film are materials having different etching rates from each other. Method for producing a fine pattern of a semiconductor device. The method of claim 1, The first thin film and the third thin film are materials having similar etching rates to each other, and the third thin film is a material having a different etching rate from the first and second thin films. Method for producing a fine pattern of a semiconductor device. The method of claim 1, The first and third thin films are oxide films, and the second thin film is polysilicon. Method for producing a fine pattern of a semiconductor device. The method of claim 1, The first and third thin films are nitride films, and the second thin films are oxide films. Method for producing a fine pattern of a semiconductor device.
KR1020080134922A 2008-12-26 2008-12-26 Method for fabricating fine pattern in semiconductor device KR20100076763A (en)

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KR1020080134922A KR20100076763A (en) 2008-12-26 2008-12-26 Method for fabricating fine pattern in semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150015765A (en) * 2013-08-01 2015-02-11 삼성디스플레이 주식회사 Method for constituting structure including micro pattern, method for constituting nano pattern, and method for manufacturing display panel for liquid crystal display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150015765A (en) * 2013-08-01 2015-02-11 삼성디스플레이 주식회사 Method for constituting structure including micro pattern, method for constituting nano pattern, and method for manufacturing display panel for liquid crystal display

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