KR20100076763A - Method for fabricating fine pattern in semiconductor device - Google Patents
Method for fabricating fine pattern in semiconductor device Download PDFInfo
- Publication number
- KR20100076763A KR20100076763A KR1020080134922A KR20080134922A KR20100076763A KR 20100076763 A KR20100076763 A KR 20100076763A KR 1020080134922 A KR1020080134922 A KR 1020080134922A KR 20080134922 A KR20080134922 A KR 20080134922A KR 20100076763 A KR20100076763 A KR 20100076763A
- Authority
- KR
- South Korea
- Prior art keywords
- thin film
- etching
- pattern
- spacer
- semiconductor device
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000010409 thin film Substances 0.000 claims abstract description 88
- 125000006850 spacer group Chemical group 0.000 claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 238000000206 photolithography Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 50
- 239000010408 film Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a fine pattern of a semiconductor device.
As is well known, according to the high integration of semiconductor devices, finer pattern is essential. However, patterns required for the implementation of semiconductor devices, such as line and space patterns (hereinafter referred to as L / S patterns), are difficult to form fine patterns due to the resolution limitation of photolithography equipment.
Various semiconductor processes have been proposed to overcome the resolution limitation of such equipment, and one of them is a method using a spacer.
That is, by forming a spacer through deposition of a thin film on a predetermined pattern sidewall and etching the spacer, and then using the spacer as an etching mask, a technique is proposed to overcome the resolution limitation of the exposure equipment.
However, a spacer formed by deposition of a thin film and spacer etching has an asymmetrical shape. Here, the spacer etching means full anisotropic etching.
FIG. 1 is a photograph of a substrate in which a spacer is formed, and as shown in FIG. 1, the widths of spaces formed on the left and right sides of the spacer have different asymmetry.
Due to this difference, when the subsequent lower etching layer is etched, the large open width has a relatively strong etching bias, so that the final pattern formed by etching the etching layer is also asymmetric.
In addition, due to the asymmetry of the spacer, a bridge problem due to the scum of the photoresist occurs in a process such as pad opening.
The present invention has been proposed to solve the problems of the prior art, and provides a method of manufacturing a fine pattern of a semiconductor device that performs the manufacture of a fine pattern using a spacer, and also solves the problem of asymmetry of the pattern according to the use of the spacer. The purpose is.
In order to achieve the above object, a method of manufacturing a fine pattern may include: sequentially stacking a first thin film, a second thin film, and a third thin film on an etching target layer; Forming a sacrificial layer pattern on the third thin film by a photolithography process; Forming a spacer on sidewalls of the sacrificial layer pattern; Removing the sacrificial layer pattern; Etching the third thin film in a portion exposed by removing the sacrificial layer pattern; Etching the second thin film in a portion exposed by the etching of the third thin film; Removing spacers remaining on the second thin film by over etching; Etching the first thin film and the etching target layer of the portion exposed by the etching of the second thin film.
Preferably, the first thin film, the second thin film, and the third thin film are materials having different etching rates. In addition, the first thin film and the third thin film may be formed of materials having similar etching rates to each other, and the second thin film may be formed of materials having different etching rates from those of the first and third thin films.
In the improved fine pattern forming method, a spacer is formed on the first, second and third thin films of three layers, and an etch mask pattern is formed of the three layer thin film using the spacer as an etch mask. In addition, the etching mask pattern of the three-layer thin film is formed in a symmetrical pattern different from the spacer.
As a result, while forming a fine pattern beyond the resolution of the exposure equipment by using the spacer, the problem of asymmetry of the pattern according to the use of the spacer can be caused.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .
2A to 2I are cross-sectional views illustrating a method of manufacturing a fine pattern of a semiconductor device according to an embodiment of the present invention.
Referring to FIG. 2A, a first
Importantly, the first
To this end, the first, second and third thin films may be formed of an oxide, nitride, oxynitride, amorphous carbon layer, polysilicon, or the like. For example, the first and third thin films are oxide films, and the second thin film uses polysilicon. Alternatively, the first and third thin films may be used as the nitride film, and the second thin film may use an oxide film.
The
In the present exemplary embodiment, the thin film under the first
Subsequently, as illustrated in FIG. 2B, the
During the etching of the
Next, as shown in FIG. 2C, a
In addition, the deposition of the
Subsequently, spacer etching is performed to form
It is preferable to perform sufficient over etching so that no residues remain during the etching of the spacer, and the third
Next, the
Next, FIG. 2F is a state in which the third
Next, as illustrated in FIG. 2G, the second
On the other hand,
Next, FIG. 2H illustrates a state in which the over etch is performed to remove the
In this case, since the third
Subsequently, as illustrated in FIG. 2I, the exposed first
As described above, the method for forming a fine pattern according to the exemplary embodiment of the present invention may form a fine pattern having a resolution higher than that of exposure equipment using a spacer, and may also cause asymmetry of the pattern according to the use of the spacer.
Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
1 is a photograph showing that the asymmetry of the pattern occurs when producing a fine pattern using a spacer.
2A to 2I are cross-sectional views illustrating a method of manufacturing a fine pattern of a semiconductor device in accordance with an embodiment of the present invention.
* Explanation of symbols for the main parts of the drawings
201:
203A: Second
205A: sacrificial layer pattern 206: BARC layer
207:
209 recess
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080134922A KR20100076763A (en) | 2008-12-26 | 2008-12-26 | Method for fabricating fine pattern in semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080134922A KR20100076763A (en) | 2008-12-26 | 2008-12-26 | Method for fabricating fine pattern in semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20100076763A true KR20100076763A (en) | 2010-07-06 |
Family
ID=42638430
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1020080134922A KR20100076763A (en) | 2008-12-26 | 2008-12-26 | Method for fabricating fine pattern in semiconductor device |
Country Status (1)
Country | Link |
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KR (1) | KR20100076763A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150015765A (en) * | 2013-08-01 | 2015-02-11 | 삼성디스플레이 주식회사 | Method for constituting structure including micro pattern, method for constituting nano pattern, and method for manufacturing display panel for liquid crystal display |
-
2008
- 2008-12-26 KR KR1020080134922A patent/KR20100076763A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150015765A (en) * | 2013-08-01 | 2015-02-11 | 삼성디스플레이 주식회사 | Method for constituting structure including micro pattern, method for constituting nano pattern, and method for manufacturing display panel for liquid crystal display |
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