KR20110076661A - Method for forming micropattern in semiconductor device - Google Patents

Method for forming micropattern in semiconductor device Download PDF

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Publication number
KR20110076661A
KR20110076661A KR1020090133415A KR20090133415A KR20110076661A KR 20110076661 A KR20110076661 A KR 20110076661A KR 1020090133415 A KR1020090133415 A KR 1020090133415A KR 20090133415 A KR20090133415 A KR 20090133415A KR 20110076661 A KR20110076661 A KR 20110076661A
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South Korea
Prior art keywords
forming
pattern
hard mask
semiconductor device
fine pattern
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KR1020090133415A
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Korean (ko)
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정진기
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주식회사 하이닉스반도체
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Priority to KR1020090133415A priority Critical patent/KR20110076661A/en
Publication of KR20110076661A publication Critical patent/KR20110076661A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

In the method of forming a fine pattern of a semiconductor device to which the trimming process is applied, the formation of the fine pattern of the semiconductor device can prevent the etched layer from being trimmed to a desired critical dimension due to abnormal polymers sticking to the sidewall of the etched layer. To provide a method, the present invention provides a step of providing a substrate on which the etched layer is formed, forming a hard mask pattern on the etched layer, both side walls of the hard mask pattern when forming the hard mask pattern A method of forming a fine pattern of a semiconductor device, the method comprising: removing an abnormal polymer adhering to and reducing a width of the hard mask pattern to a target threshold by performing a trimming etching process.

Description

METHOD FOR FORMING MICROPATTERN IN SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a fine pattern of a semiconductor device using a trimming process in a semiconductor device manufacturing process.

In the semiconductor device manufacturing process, the reduction of line width is a key factor for improving yield. Due to this reduction in line width, masks are also increasingly smaller in size. However, due to the limitation of photo equipment, a lot of difficulties are involved in the etching process in the device of 40 nm or less. For this reason, the most popular technology in recent years is the trimming technology.

Trimming technology can reduce the critical dimension of the final etched layer pattern by the etching process by etching a side of the lower stack of the mask through a separate etching process even if the patterning is large in the mask process. That is the process method. This trimming technique was introduced to overcome the limitations of photo equipment and to improve the critical dimension.

In particular, such a trimming technique is currently usefully applied when forming a gate electrode for a transistor in a peripheral circuit region. The reason is that the gate electrode threshold of not only the cell region but also the peripheral circuit region must be reduced due to the reduction of the line width due to the high integration of the semiconductor device. Here, the cell region represents a region where a memory cell of a semiconductor device is formed, and the peripheral circuit region represents an region where a peripheral circuit including a driving circuit for driving a cell is formed.

Hereinafter, a method of forming a fine pattern of a semiconductor device to which a trimming process according to the related art is applied will be described as an example of a method of forming a gate electrode in a current peripheral circuit region.

First, an amorphous carbon (AC) film is sequentially formed on the semiconductor substrate using a nitride film as a gate oxide film, a conductive film for forming a gate electrode, and a hard mask for protecting a gate electrode, and then a SiON film thereon. And an antireflection film and a photosensitive film pattern for forming a gate electrode.

Subsequently, the antireflection film and the SiON film are etched using the photoresist pattern as an etching mask. As a result, an antireflection film pattern and a SiON film pattern are formed.

Subsequently, after removing the photoresist pattern and the anti-reflection film pattern, the amorphous carbon film is etched through the SiON film pattern. As a result, an amorphous carbon film pattern is formed.

Subsequently, a separate trimming etching process is performed to trim the amorphous carbon film pattern to a desired critical dimension.

Subsequently, after the nitride film is etched through the amorphous carbon film pattern to form the nitride film pattern, the conductive film is etched using the nitride film pattern as an etching mask. This completes the gate electrode.

However, when the method for forming a micropattern of a semiconductor device using the trimming process according to the prior art is applied, the following problem occurs. That is, as shown in FIG. 1, the amorphous carbon film pattern AC does not trim to a desired target threshold even after a separate trimming etching process is performed for trimming after forming the amorphous carbon film pattern AC. Occurs. Thus, a problem arises in that the gate electrode is not patterned to a desired target threshold.

Specifically, (a) of FIG. 1 is a scanning electron microscope (SEM) photograph showing a gate electrode of a peripheral circuit region after forming an amorphous carbon film pattern (AC), and FIG. 1 (b) is for trimming. A SEM photograph showing the gate electrode of the peripheral circuit region after the amorphous carbon film pattern AC is etched with the O 2 / HBr / Ar mixed gas separately. At this time, as in FIGS. 1A and 1B, the amorphous carbon film patterns AC have the same width W. FIG. Referring to this, it can be seen that the amorphous carbon film pattern AC is not trimmed even after the amorphous carbon film pattern AC is formed and the trimming etching process is performed.

The reason why the trimming is not performed even after the trimming etching process is performed is that the abnormal polymers (foreign materials, polymers) generated by etching the nitride film at the bottom of the amorphous carbon film pattern during the formation of the amorphous carbon film pattern may be formed in the amorphous carbon film pattern. It sticks to both sidewalls and remains because these abnormal polymers are not removed during the trimming etching process.

The present invention has been proposed to solve the above problems of the prior art, and in the method of forming a micropattern of a semiconductor device to which a trimming process is applied, the etched layer has a desired critical dimension due to abnormal polymers that adhere to sidewalls of the etched layer. It is an object of the present invention to provide a method for forming a fine pattern of a semiconductor device which can prevent the trimming.

According to an aspect of the present invention, there is provided a substrate on which an etched layer is formed, forming a hard mask pattern on the etched layer, and forming the hard mask pattern when the hard mask pattern is formed. It provides a method of forming a fine pattern of a semiconductor device comprising the step of removing the abnormal polymer adhering to both side walls of the, and reducing the width of the hard mask pattern to a target threshold dimension by performing a trimming etching process.

According to another aspect of the present invention, there is provided a method of forming an etching target layer on a substrate including a first region and a second region, and forming a hard mask pattern on the etching layer. Removing the abnormal polymer stuck to both sidewalls of the hard mask pattern when the hard mask pattern is formed, forming a photoresist pattern having a structure in which the second region is opened, and etching the photoresist pattern into an etch mask. A method of forming a fine pattern of a semiconductor device, the method comprising: reducing the width of the hard mask pattern of the second region to a target threshold by performing a trimming etching process.

According to the present invention described above, the amorphous carbon film pattern used as a sacrificial hard mask pattern when forming the fine pattern of the semiconductor device to remove the abnormal polymer generated by etching the etching layer of the bottom portion of the amorphous carbon film pattern partially formed By applying a trimming etching process for trimming the amorphous carbon film pattern after the separate cleaning process, it is possible to prevent the amorphous carbon film pattern from being trimmed to a desired target critical dimension by the abnormal polymers. Thus, the etched layer pattern can be trimmed to a desired target threshold.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. Also, throughout the specification, the same reference numerals denote the same elements.

Example

2A to 2F are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device to which a trimming process according to an embodiment of the present invention is applied. As an example, a method of selectively trimming the gate electrode of the peripheral circuit region will be described.

First, as shown in FIG. 2A, a gate insulating layer (not shown) is formed on a semiconductor substrate 10 including a cell region CELL and a peripheral circuit region PERI D, and then a gate electrode is formed thereon. The polysilicon film 11 is formed as a lower layer of the conductive film. In this case, the polysilicon film 11 is formed of a doped polysilicon film doped with impurities or an un-doped polysilicon film not doped with impurities.

Subsequently, the metal film 12 is formed on the polysilicon film 11 as the upper layer of the conductive film for forming a gate electrode. For example, the metal film 12 may be formed as a single film of tungsten (W) or a laminated film of tungsten nitride film (WN) / tungsten film. At this time, when the metal film 12 is a laminated film of tungsten nitride film / tungsten film, the formation of the polysilicon film 11 which is the lower layer of the gate conductive film may be omitted.

Next, the nitride film 13 is formed on the metal film 12 with the hard mask for gate electrode protection.

Subsequently, after forming the amorphous carbon film 14 on the nitride film 13 with a sacrificial hard mask, a SiON film 15 is formed thereon. In this case, all materials containing carbon may be applied instead of the amorphous carbon film 14. For reference, the SiON film 15 serves to protect the amorphous carbon film 14 during a photo process (including an exposure and development process using a photo mask).

Subsequently, a bottom anti-reflective coating (BARC) 16 is formed on the SiON film 15, and then the photoresist pattern 17, which is an etching mask for forming a gate electrode, is formed on the anti-reflective film 16 through a photo process. ).

Subsequently, as shown in FIG. 2B, the antireflection film 16 (see FIG. 2A) and the SiON film 15 (see FIG. 2A) are etched using the photoresist pattern 17 (see FIG. 2A) as an etching mask. As a result, an antireflection film pattern (not shown) and a SiON film pattern 15A are formed.

Subsequently, a strip process is performed to remove the photoresist pattern 17 and the anti-reflection film pattern, and then the amorphous carbon film 14 (see FIG. 2A) is etched using the SiON film pattern 15A as an etching mask. As a result, the amorphous carbon film pattern 14A is formed.

When the amorphous carbon film pattern 14A is formed, an abnormal polymer that is generated when the upper surface of the nitride film 13 at the bottom of the amorphous carbon film pattern 14A is partially etched (for example, about 100 to 150 Å is lost) ( 18) adhere to both side walls of the amorphous carbon film pattern 14A. Thereby, the amorphous carbon film pattern 14A is patterned to a width W 1 larger than the target critical dimension in the mask process.

Subsequently, as shown in FIG. 2C, the abnormal polymers 18 (see FIG. 2B) adhered to both side walls of the amorphous carbon film pattern 14A are removed. For example, the abnormal polymers 18 are separately removed by performing a wet cleaning process or a plasma treatment using a wet chemical. As a result, the amorphous carbon film pattern 14A is reduced to the same width W 2 as the target critical dimension in the mask process.

At this time, the wet cleaning process uses a chemical containing HF. For example, BOE (Buffered Oxdie Etchant)-a solution in which HF and NH 4 F are mixed at 100: 1 or 300: 1. In the plasma treatment, a gas containing fluorine (F), such as CF 4 gas, is used.

Meanwhile, the cleaning process may be performed after the subsequent photosensitive film pattern 19 (see FIG. 2D) forming process.

Subsequently, as illustrated in FIG. 2D, a photosensitive film pattern 19 having a structure of opening the peripheral circuit region PERI is formed on the entire structure on which the amorphous carbon film pattern 14A is formed.

Subsequently, as shown in FIG. 2E, the amorphous carbon film pattern 14A of the peripheral circuit region PERI opened by using the photoresist pattern 19 as an etching mask for selective trimming of the peripheral circuit region PERI is separately provided. Etch it. For example, a trimming etching process using an O 2 / HBr / Ar or O 2 / N 2 / Ar mixed gas is performed to recess both side walls of the amorphous carbon film pattern 14A by a predetermined thickness recess ('D' region), respectively. The width of the amorphous carbon film pattern 14A is reduced to 'W 3 '. Thereby, the width W 3 of the amorphous carbon film pattern 14A of the peripheral circuit region PERI is trimmed to the desired final target threshold.

In this case, O 2 gas is used as an etching gas for trimming, and HBr or N 2 gas is used as a passivation gas.

Here, the critical dimension of the amorphous carbon film pattern 14A may be adjusted in proportion to the time of the trimming etching process.

In addition, in the trimming etching process, the substrate temperature is maintained at about −30 to 100 ° C., the pressure is 1 to 50 mTorr, the power is applied in the range of 200 to 1500 W, and the process is preferably performed for about 60 seconds.

Subsequently, as shown in FIG. 2F, a strip process is performed to remove the photoresist pattern 19 (see FIG. 2E).

Subsequently, although not shown in the figure, the nitride film pattern (not shown) is formed by etching the nitride film 13 using the amorphous carbon film pattern 14A as an etching mask.

Subsequently, the metal film 12, the polysilicon film 11, and the gate insulating film (not shown) are sequentially etched using the nitride film pattern as an etching mask. This completes the gate electrode.

In this case, the gate electrode forming hard mask and the conductive layer as the etched layer may be trimmed to a desired final target dimension in the peripheral circuit region PERI. This is because the gate electrode is patterned using the amorphous carbon film pattern 14A of the peripheral circuit region PERI trimmed to a desired final target threshold value as an etching mask.

On the other hand, Figure 3 is a SEM photograph showing the structure of the peripheral circuit region in the state of Figure 2b is completed, Figure 4 is a SEM photograph showing the structure of the peripheral circuit region in the state of Figure 2c is completed, Figure 5 FIG. 2E is a SEM photograph showing the structure of the peripheral circuit region in which the process of FIG. 2E is completed.

3 to 5, the amorphous carbon film after the amorphous carbon film pattern AC has the largest width W 1 , and the abnormal polymer removal step is performed. The width W 2 of the pattern AC is reduced than immediately after the formation of the amorphous carbon film pattern AC, and the width W 3 of the amorphous carbon film pattern AC after applying the trimming etching process is abnormal. It can be seen that the decrease than after proceeding. This indicates that the amorphous carbon film pattern (AC) width in the peripheral circuit region is trimmed to normal in the case of the embodiment of the present invention.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

Figure 1 (a) is a SEM (Scanning Electron Microscope) photograph showing the gate electrode of the peripheral circuit region after forming the amorphous carbon film pattern by applying a method for forming a micro pattern of a semiconductor device according to the prior art.

Figure 1 (b) is a gate electrode of the peripheral circuit region after etching the amorphous carbon film pattern by O 2 / HBr / Ar mixed plasma separately for trimming by applying a method of forming a fine pattern of a semiconductor device according to the prior art SEM photograph shown.

2A to 2F are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device to which a trimming process according to an embodiment of the present invention is applied.

Figure 3 is a SEM photograph showing the structure of the peripheral circuit area in the process of Figure 2b is completed.

Figure 4 is a SEM photograph showing the structure of the peripheral circuit area in the process of Figure 2c is completed.

5 is a SEM photograph showing the structure of the peripheral circuit area in the state of FIG. 2E is completed.

<Explanation of symbols for the main parts of the drawings>

CELL: Cell area PERI: Peripheral circuit area

10 substrate 11 polysilicon film

12 metal film 13 nitride film

14: amorphous carbon film 15: SiON film

16: antireflection film 17, 19: photosensitive film pattern

18: or more polymer 15A: SiON film pattern

14A: amorphous carbon film pattern

Claims (17)

Providing a substrate on which an etched layer is formed; Forming a hard mask pattern on the etched layer; Removing the abnormal polymer stuck to both sidewalls of the hard mask pattern when the hard mask pattern is formed; And Performing a trimming etching process to reduce the width of the hard mask pattern to a target critical dimension; Method of forming a fine pattern of a semiconductor device comprising a. The method of claim 1, After performing the trimming etching process, Etching the etched layer through the hard mask pattern Method of forming a fine pattern of a semiconductor device further comprising. The method according to claim 1 or 2, The hard mask pattern is a fine pattern forming method of a semiconductor device formed of a material containing carbon. The method of claim 3, wherein Forming the hard mask pattern, Depositing a hard mask containing carbon on the etched layer; Forming a SiON film on the hard mask; Forming an anti-reflection film pattern on the SiON film; And Etching the SiON layer and the hard mask through the anti-reflection layer pattern Method of forming a fine pattern of a semiconductor device comprising a. The method according to claim 1 or 2, The etching pattern layer is a fine pattern forming method of a semiconductor device to form a stacked structure of a conductive film for forming a gate electrode and a hard mask for protecting the gate electrode. The method according to claim 1 or 2, Removing the abnormal polymer, A method of forming a fine pattern of a semiconductor device by performing a wet cleaning process using a chemical containing HF or a plasma treatment using a gas containing fluorine. The method according to claim 1 or 2, The trimming etching process is a method of forming a fine pattern of a semiconductor device using O 2 / HBr / Ar or O 2 / N 2 / Ar mixed gas. The method according to claim 1 or 2, In the trimming etching process, the substrate temperature is maintained at -30 to 100 ° C., and the fine pattern forming method of the semiconductor device is performed by applying a pressure of 1 to 50 mTorr and a power of 200 to 1500 W. Forming an etched layer on a substrate comprising a first region and a second region; Forming a hard mask pattern on the etched layer; Removing the abnormal polymer stuck to both sidewalls of the hard mask pattern when the hard mask pattern is formed; Forming a photoresist pattern having a structure that opens the second region; And Performing a trimming etching process using the photoresist pattern as an etching mask to reduce a width of the hard mask pattern of the second region to a target threshold dimension; Method of forming a fine pattern of a semiconductor device comprising a. The method of claim 9, After performing the trimming etching process, Removing the photoresist pattern; And Etching the etched layer through the hard mask pattern Method of forming a fine pattern of a semiconductor device further comprising. The method of claim 9, Removing the abnormal polymer, The method of forming a fine pattern of a semiconductor device after the step of forming the photosensitive film pattern. The method according to any one of claims 9 to 11, The hard mask pattern is a fine pattern forming method of a semiconductor device formed of a material containing carbon. 13. The method of claim 12, Forming the hard mask pattern, Depositing a hard mask containing carbon on the etched layer; Forming a SiON film on the hard mask; Forming an anti-reflection film pattern on the SiON film; And Etching the SiON layer and the hard mask through the anti-reflection layer pattern Method of forming a fine pattern of a semiconductor device comprising a. The method according to any one of claims 9 to 11, The etching pattern layer is a fine pattern forming method of a semiconductor device to form a stacked structure of a conductive film for forming a gate electrode and a hard mask for protecting the gate electrode. The method according to any one of claims 9 to 11, Removing the abnormal polymer, A method of forming a fine pattern of a semiconductor device by performing a wet cleaning process using a chemical containing HF or a plasma treatment using a gas containing fluorine. The method according to any one of claims 9 to 11, The trimming etching process is a method of forming a fine pattern of a semiconductor device using O 2 / HBr / Ar or O 2 / N 2 / Ar mixed gas. The method according to any one of claims 9 to 11, In the trimming etching process, the substrate temperature is maintained at -30 to 100 ° C., and the fine pattern forming method of the semiconductor device is performed by applying a pressure of 1 to 50 mTorr and a power of 200 to 1500 W.
KR1020090133415A 2009-12-29 2009-12-29 Method for forming micropattern in semiconductor device KR20110076661A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8906757B2 (en) 2011-12-06 2014-12-09 Samsung Electronics Co., Ltd. Methods of forming patterns of a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8906757B2 (en) 2011-12-06 2014-12-09 Samsung Electronics Co., Ltd. Methods of forming patterns of a semiconductor device

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