JPH10261710A - Formation of wiring and manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely form a wiring layer having a narrower line width than the minimum line width formed by exposure technology by exposing a patterned mask layer by removing a frame layer and a diameter-reducing side wall, anisotropically etching a conductive material layer by using a mask layer as a mask and forming the wiring layer. SOLUTION: Resist is etched back by, for example, oxygen reactive ion etching, for 200 nm, a groove is buried, and a resist 143 of a wiring pattern having a height of 400 nm is formed (f). A silicon oxide layer 121 and a side wall 123 are entirely removed by hydrofluoric acid aqueous solution, and the resist 143 of the wiring pattern having a width of 0.15 μm and a height of 400 nm is left (g). A polysilicon layer 131 is anisotropically etched for 100 nm by using ECR system poly-etcher with the resist 143 as a mask, and a polysilicon layer 131 is formed into a wiring pattern 132. Then, the resist 143 is removed, and a reduced polysilicon wiring layer 132 having a width of 0.15 μm is formed (h).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method applicable in the field of manufacturing semiconductor devices and capable of reducing a line width by a processing technique, and a method of manufacturing a semiconductor device using this method.

[0002]

2. Description of the Related Art LSI
In three years, high integration has progressed to the next generation, and the design rule has been reduced by 70% of the previous generation, and with the reduction in size, the speed of transistors has also been increased. This integration has been achieved by advances in microfabrication technology, particularly by increasing the resolution of light exposure technology. High resolution of the light exposure technology has been achieved by improving the performance of an exposure apparatus and a resist material / resist process while satisfying dimensional accuracy and overlay accuracy corresponding to design rules. When the pattern size is from 1.0 μm to 0.1 μm.
The light exposure technology of 5 μm is, for example, 1 MDR in a memory.
Corresponding to AM to 16 MDRAM, the major change during this time was the shortening of the exposure technology wavelength from g-line (436 nm) to i-line (365 nm). At present, LSI of 0.35 μm rule using i-line is the mainstay,
In the μm rule, KrF excimer laser (248.8n
m) is being used for development and mass production.

However, in the recently announced exposure apparatus for mass production of 0.25 μm, it is becoming difficult to maintain the trend of miniaturization of the cell size. This is due to a lack of improvement in the variation in the alignment of the stepper, and the variation in the alignment is large, so that the design margin for the alignment must be increased. As a result, it is difficult to reduce the cell size despite the reduced wiring width. Therefore, a cell size reduction technique that does not depend on the exposure technique has been demanded.

[0004] As the method, there are a self-aligned contact technique and a resist wiring pattern reduction technique.

The former self-aligned contact technology is currently being actively studied, and in particular, Si ₃ N ₄ (silicon nitride)
The most famous method is to use the film as an etching stopper. This method has an advantage that the cost increase is relatively small because the number of exposure steps is not increased, but it requires an extremely advanced dry etching technique and has many problems. The biggest issues among them are the selectivity to the silicon nitride film at the shoulder of the sidewall and the etch stop.

An ideal self-aligned contact technique is to form an insulating sidewall 21 on the side of a gate electrode 31 of a MOS transistor formed on a semiconductor substrate 10 as shown in FIG. Gate electrode 3
An etching stopper film 22 made of silicon nitride is formed so as to cover the entire surface of the silicon nitride film 1 and the sidewalls 21, and an interlayer insulating film 23 of a silicon oxide film covering the etching stopper film 22 is formed. Then, contact hole patterning of the resist R1 is performed on the planarized interlayer insulating film 23. Next, as shown in FIG. 25B, the etching is stopped on the stopper layer 22 using the condition of high selectivity to silicon nitride, and the interlayer silicon oxide film 23 is stopped.
Is etched. Next, as shown in FIG. 25C, the stopper layer 22 is etched under silicon nitride etching conditions.
Is etched to expose an impurity diffusion layer (not shown) of the silicon substrate 10, and a contact hole 40 is formed.

However, when the selectivity to silicon nitride is slightly low, as shown in FIG.
The stopper layer 22 at the shoulder is etched, the sidewalls 21 are shaved, and the distance between the gate electrode 31 and the wiring plug is shortened, thereby causing a withstand voltage failure. Therefore, when etching conditions with a high selectivity to silicon nitride are used, as shown in FIG. 27, the interlayer silicon oxide 23a in the slit portion where the side wall at the bottom of the contact hole is exposed and the diameter of the contact hole is reduced is completely etched. Etch stop occurs.
The reason is that in order to increase the selectivity to silicon nitride, C
It is thought that this is due to a synergistic effect of excessive supply of CF radicals, which are seeds of the F protective film, and reduction of ions (microloading effect) that can enter because the aspect ratio locally increases in the slit portion. Therefore, it is difficult to form a self-aligned contact with a large margin using only the dry etching technique, and it is necessary to adopt a structure in which the slit width is increased without increasing the cell size. That is, it has a structure having a gate electrode having a rule of 0.25 μm or less, and a technology for reducing the gate electrode, that is, the wiring width is required.

On the other hand, as the latter technique for reducing a wiring pattern, there is a technique for reducing a wiring pattern of a resist. As shown in FIG. 28, after the patterning of the resists 51 to 55 is completed, the resist is ashed isotropically using oxygen plasma to reduce the width of the resist wiring pattern.

However, in principle, the amount of resist etching changes depending on the density of the pattern, and as shown in FIG.
Even if the wiring pattern width is the same regardless of the density, as shown in FIG. 29, after the oxygen plasma processing, the isolated resist pattern 55 is preferentially subjected to ashing and the width of the dense resist patterns 51 to 54 is reduced. It becomes wider (51a-55a). Since it is extremely difficult to control the uniform reduction of the wiring pattern, the practicality of this technique is still low. Therefore, there is a need for a technology for reducing wiring that does not depend on the density of patterns.

As described above, there is a demand for a wiring reduction technology as a cell size reduction technology. In addition, since the cut-off frequency of the MOS transistor is inversely proportional to the square of the effective channel length L when the speed of the transistor is increased, the gate electrode width is reduced, that is, L is reduced. Also in this respect, a technology for reducing the gate electrode width (wiring) is eagerly desired.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a wiring forming method capable of reducing a wiring width from a design rule by a processing technique, and a method of manufacturing a semiconductor device using this method.

[0012]

In order to achieve the above object, the present invention firstly forms a step of forming a conductive material layer on a substrate, and forms a mold layer on the conductive material layer. Forming a groove of a wiring pattern penetrating the form layer, forming a sidewall for reducing the diameter on a side wall of the groove of the wiring pattern, and masking the groove formed with the sidewall with a mask layer. A step of exposing the mold layer and the side wall for diameter reduction to expose a patterned mask layer, and anisotropically etching the conductive material layer using the mask layer as a mask to form a wiring. And a step of forming a layer.

Second, a step of forming a conductive material layer on the substrate, a step of forming a first mask layer on the conductive material layer, and a step of forming the first mask layer on the first mask layer Forming a groove of the wiring pattern while leaving the bottom of the wiring pattern, forming a sidewall for reducing the diameter on the side wall of the groove of the wiring pattern, and filling the groove formed with the sidewall with a second mask layer. Using the second mask layer as a mask, removing the first mask layer and the sidewall for diameter reduction by anisotropic etching to obtain a laminate of the first mask layer and the second mask layer having a wiring pattern. And forming a wiring layer by anisotropically etching the conductive material layer using the first mask layer or a laminate of the first mask layer and the second mask layer as a mask. Provided is a wiring forming method.

Third, a step of forming a conductive material layer on the semiconductor substrate, a step of forming a mold layer on the conductive material layer, and a groove of a gate electrode pattern penetrating the mold layer Forming, forming a sidewall for reducing the diameter on the side wall of the groove of the gate electrode pattern, filling the groove on which the sidewall has been formed with a mask layer, Removing the wall to expose a patterned mask layer; forming a gate electrode by anisotropically etching the conductive material layer using the mask layer as a mask; and forming a side wall on a side wall of the gate electrode. Forming an impurity diffusion layer on the semiconductor substrate by ion implantation using the gate electrode and / or the sidewall as a mask, and forming an interlayer insulating film covering the gate electrode. Providing a step of forming a contact hole in the interlayer insulating film on the impurity diffusion layer, a method of manufacturing a semiconductor device characterized by a step of forming a plug by filling the contact hole with a conductive material.

Fourth, a step of forming a conductive material layer on the semiconductor substrate, a step of forming a first mask layer on the conductive material layer, and a step of forming the first mask layer on the first mask layer Forming a groove of the gate electrode pattern while leaving the bottom of the gate electrode, forming a sidewall for reducing the diameter on the side wall of the groove of the gate electrode pattern, and filling the groove formed with the sidewall with a second mask layer. A step of removing the first mask layer and the sidewalls for reducing the diameter by anisotropic etching using the second mask layer as a mask, and forming a gate electrode patterned first mask layer and second mask layer; Obtaining a
Forming a gate electrode by anisotropically etching the conductive material layer using the first mask layer or a laminate of the first mask layer and the second mask layer as a mask; and forming sidewalls on sidewalls of the gate electrode. Forming a gate electrode and / or
A step of forming an impurity diffusion layer on the semiconductor substrate by ion implantation using the sidewall as a mask, a step of forming an interlayer insulating film covering the gate electrode, and a step of contacting the impurity diffusion layer penetrating the interlayer insulating film. A method for manufacturing a semiconductor device, comprising: a step of forming a hole; and a step of forming a plug by filling the contact hole with a conductive material.

According to the wiring forming method of the present invention, a conductive material layer for wiring such as polysilicon, and a mold layer (first mask layer) such as silicon oxide are laminated, and a minimum line width of 0 mm is formed on the mold layer. .
After forming a wiring groove having a width of 0.25 μm according to the 25 μm rule, a silicon oxide film having a thickness of, for example, 50 nm is deposited in the wiring groove, and etched back to reduce the diameter of the wiring groove to a thickness of 50 nm on the side wall. Forming side walls. Thus, the width of the wiring groove becomes 0.15 μm.
Then, the wiring groove thus reduced is filled with, for example, a resist (second mask layer, mask layer), and then the mold layer and the sidewalls are removed.

At this time, if the wiring groove is formed by penetrating the form layer, the form layer and the sidewall are all removed to expose the resist of the wiring pattern having the reduced line width.
When the conductive material layer is etched using the resist having a width of 0.15 μm as a mask for anisotropic etching, 0.15 μm is obtained.
A wiring layer having a width of μm can be formed (first invention).

On the other hand, when the wiring groove is formed so as to leave the bottom of the mold layer, the mold layer and the sidewalls are removed by anisotropic etching using the resist as a mask. A mold layer (first mask layer) of a wiring pattern having a line width of .15 μm is formed. Then, by etching the conductive material layer using the first mask layer as a mask, a wiring layer having a width of 0.15 μm can be formed (second invention).

The line width reduction technique by such a processing technique can form a wiring pattern narrower than the width of the opening of the original wiring pattern, and the width can be easily controlled by changing the thickness of the sidewall. . Therefore, according to the wiring forming method of the present invention, the wiring groove is formed with the minimum line width,
A wiring layer having a smaller line width can be surely formed.

If this technique is applied to the formation of a gate electrode of a semiconductor device, the gate electrode width (channel length) can be made smaller than the design rule. As a result, the distance from the contact hole becomes longer, so that the withstand voltage failure is less likely to occur, and the yield of the semiconductor device is improved.
At the same time, the speed of the transistor can be increased.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments.

[First Embodiment] The first embodiment shows an example in which the wiring forming method of the present invention is applied to the formation of a polysilicon wiring, which will be described with reference to FIGS. FIG. 1 shows the first step, in which (a1) is a plan view and (a2) is a cross-sectional view. First, steps leading to the structure shown in these figures will be described.

On the interlayer insulating film 120 made of, for example, silicon oxide formed on a semiconductor substrate or the like,
Polysilicon layer 131 as wiring material layer by VD method
Is deposited to a thickness of 100 nm. Subsequently, a silicon oxide film 121 as a mold layer is formed to a thickness of 500 nm by, for example, a normal pressure CVD method.
Form a film. Thereafter, a resist 141 is applied by spin coating or the like, and patterning of a wiring having an opening width of, for example, 0.25 μm is performed by an exposure technique according to a minimum design rule. In this case, unlike a normal pattern, the pattern is a negative pattern, and a portion serving as a wiring is opened. Thus, the structures shown in FIGS. 1A1 and 1A2 are obtained.

Next, as shown in FIG. 1B, using the resist 141 as a mask, the silicon oxide layer 121 is formed by using a magnetron type silicon oxide etcher.
The trench 1 of the wiring pattern which is etched by 00 nm and penetrates the silicon oxide layer 121 to reach the polysilicon layer 131
Form 50.

Next, as shown in FIG. 2C, the resist 141 is removed using, for example, a downflow type asher, and then the silicon oxide film 122 is formed by a method having good step coverage such as a low pressure CVD method. 50n
m is formed. In this example, the same silicon oxide as the mold layer was deposited, but since this layer functions as a sidewall and is to be removed later, a different material from the mold layer may be used.

Next, as shown in FIG. 2D, the silicon oxide film 122 is etched back by 50 nm using, for example, a parallel plate type silicon oxide etcher. As a result, the diameter reducing sidewall 123 having a thickness of 50 nm is formed on the side wall of the groove 150 of the wiring pattern of the form layer, and the width of the opening of the groove 150 is reduced from 0.25 μm width to 0.15 μm width.

Next, as shown in FIG. 2E, for example, a resist is applied as a mask layer, the groove is filled, and a resist 142 is formed on the form layer so as to have a height of about 100 nm. . Note that the resist 142 as the mask layer
As long as the etching selectivity with the mold layer 121, the sidewall 123 and the wiring material layer 131 can be obtained, other materials can be used.

Next, as shown in FIG. 3 (f), the resist 142 is subjected to, for example, oxygen-reactive ion etching (an apparatus for etching or ashing the resist by irradiating with oxygen ions, which is also commercially available as an asher).
Then, the trench 150 is buried, and a resist 143 having a wiring pattern of 400 nm in height is formed.

Next, as shown in FIG. 3 (g), the silicon oxide layer 121 and the sidewall 123 are entirely removed with, for example, a hydrofluoric acid aqueous solution, and the width is 0.15 μm and the height is 4 μm.
The resist 143 of the 00 nm wiring pattern is left.

Next, as shown in FIG. 3H, the polysilicon layer 131 is anisotropically etched to a thickness of 100 nm using, for example, an ECR type poly etcher by using the patterned resist 143 as a mask.
Is formed on the wiring pattern 132. Then, resist 1
By removing 43, a reduced polysilicon wiring layer 132 having a width of 0.15 μm can be formed.

Through the above steps, a finer 0.15 .mu.m wide polysilicon wiring could be formed with good controllability using the 0.25 .mu.m rule exposure technique.
Conventionally, such a wiring layer having a reduced line width can prevent such a positioning variation even if a short circuit or insulation failure is caused by a variation in the positioning of a contact hole (via hole). Since there is a margin of 50 nm, short circuit and insulation failure are less likely to occur than before, and the yield can be improved and the cell size can be reduced.

[Embodiment 2] A second embodiment shows an example in which the wiring forming method of the present invention is applied to aluminum wiring formation, and will be described with reference to FIGS. FIG. 4 shows the first step, in which (a1) is a plan view and (a2) is a cross-sectional view. The steps leading to the structure shown in these figures will be described.

An aluminum layer 231 is formed to a thickness of 100 nm by, for example, a sputtering method on an interlayer insulating film 220 made of, for example, silicon oxide formed on a semiconductor substrate or the like. The silicon oxide layer 221 is formed to a thickness of 600 nm by, for example, a normal pressure CVD method. Thereafter, a resist 241 is applied by spin coating or the like, and patterning of a wiring having an opening width of, for example, 0.25 μm is performed by an exposure technique according to a minimum design rule. In this case, unlike a normal pattern, the pattern is a negative pattern, and a portion serving as a wiring is opened.

Next, as shown in FIG. 4B, using the resist 241 as a mask, the silicon oxide layer 221 is formed by using a magnetron type silicon oxide film etcher.
Patterning is performed by etching by 00 nm. Thereby, the groove 250 of the wiring pattern is formed in the silicon oxide layer 221.
Is formed, and there is a 100 nm thick silicon oxide layer remaining on the aluminum layer on the bottom surface of the groove 250.

Next, as shown in FIG. 5C, the resist 241 is removed by using, for example, a downflow type asher, and then the silicon oxide 222 is made to have a thickness of, for example, 50 nm by a good step coverage method such as a low pressure CVD method.
Is formed with a film thickness of In this example, the same silicon oxide as the first mask layer 221 was deposited, but since this layer functions as a sidewall and is to be removed later, a material different from that of the first mask layer 221 may be used.

Next, as shown in FIG. 5D, the silicon oxide film 222 is etched back by, for example, 50 nm using a parallel plate type silicon oxide etcher. As a result, a 50 nm-thick sidewall for reduction 223 is formed on the side wall of the groove 250 of the wiring pattern of the silicon oxide layer 221,
The width of the opening of the groove 250 is changed from 0.25 μm width to 0.15 μm.
Reduce to m width.

Next, as shown in FIG. 5E, for example, a resist 242 is applied as a second mask layer to fill the groove,
A resist 242 is formed over the silicon oxide layer 221 so as to have a height of about 100 nm. As the resist as the second mask layer, another material can be used as long as the etching selectivity with the first mask layer 221, the sidewall 223, and the wiring material layer 231 can be obtained.

Next, as shown in FIG. 6F, the resist 242 is removed by, for example, oxygen reactive ion etching.
Etch back by 00nm, fill groove, 400n height
A resist having a wiring pattern of m is formed.

Next, as shown in FIG. 6G, the silicon oxide layer 221 is etched to a thickness of 600 nm using, for example, a magnetron type silicon oxide etcher, using the patterned resist 243 filling the groove as a mask.
Thus, a laminate of the resist 243 and the silicon oxide mask 221a thereunder is formed in a wiring pattern, and the line width of these laminates is 0.15 μm.

Then, as shown in FIG. 6H, the patterned resist 243 and the silicon oxide layer 221a are formed.
The aluminum layer 231 is etched to a thickness of 100 nm using, for example, an ECR type aluminum etcher using the mask as a mask, and the resist 243 is removed.
Aluminum wiring 232 having a width of 5 μm is formed.

Through the above steps, a finer aluminum wiring having a width of 0.15 μm can be formed with good controllability by using the 0.25 μm rule exposure technique.
Conventionally, such a wiring layer having a reduced line width can prevent such a positioning variation even if a short circuit or insulation failure is caused by a variation in the positioning of a contact hole (via hole). Since there is a margin of 50 nm for the line width reduction, short-circuiting and insulation failure are less likely to occur than before, and the yield can be improved and the cell size can be reduced.

In the above example, the aluminum wiring was etched using a laminate of a resist and a silicon oxide layer as a mask. However, as in the first embodiment, the aluminum was etched using only the resist as a mask. Is also good. However, since anisotropic etching of aluminum uses a polymer containing a resist decomposition product as a sidewall protective film, the selectivity to resist is low in principle, and it becomes difficult to control the shape when the resist film thickness is small. That is, as the etching proceeds, the resist shape becomes triangular, the bottom side recedes, and accordingly, the aluminum shape also becomes tapered. Therefore, when an inorganic mask such as silicon oxide is used, the shape can be controlled regardless of the resist shape. Further, this embodiment is also effective for polysilicon wiring. Although the decomposed product of the polysilicon etching does not work as a sidewall protective film, generally, since the selectivity of the commercially available polysilicon etcher to the resist is low,
This is also effective for etching polysilicon. Thus, in this embodiment, the conductive material layer can be etched using an inorganic mask such as silicon oxide.

[Embodiment 3] A third embodiment shows an example in which the wiring forming method of the present invention is applied to a MOS transistor forming step, which will be described with reference to FIGS. FIG.
Indicates the beginning of the process, (a1) is a plan view, (a2)
Is a sectional view. The steps leading to these figures will be described.

Gate oxide film 32 on silicon substrate 310
1 is formed to a thickness of 10 nm by dry oxidation, a polysilicon layer 331 is formed as a wiring material layer by, for example, 100 nm by low pressure CVD, and a silicon oxide layer 322 as a mold layer is formed by atmospheric pressure CVD. Then, a resist 341 for patterning this silicon oxide layer is applied by spin coating or the like, and the opening width is set to, for example, 0.25 μm according to a minimum design rule by an exposure technique.
Patterning of the wiring of m is performed. In this case, as shown in the figure, unlike a normal pattern, the pattern is a negative pattern, and a portion serving as a wiring is opened. This allows
The structure shown in FIGS. 7A1 and 7A2 is obtained.

Next, as shown in FIG. 7B, using the resist 341 as a mask, the silicon oxide layer 3 as a mold layer is formed.
22 is etched using, for example, a magnetron type silicon oxide etcher to a thickness of 500 nm to form a groove of a wiring pattern that penetrates the silicon oxide layer 322 and reaches the polysilicon layer 331.

Next, as shown in FIG. 8C, the resist 341 is removed by using, for example, a downflow type asher, and then the silicon oxide film 323 is formed by, for example, a low-pressure CVD method or the like with good step coverage. 50n
m is formed. In this example, the same silicon oxide as that of the mold layer 322 was deposited. However, this layer functions as a sidewall and is to be removed later.
A material different from 2 may be used.

Next, as shown in FIG. 8D, the silicon oxide film 323 is etched back by 50 nm using, for example, a parallel plate type silicon oxide etcher. As a result, the side wall of the groove 350 of the wiring pattern of the mold layer 322 has a thickness of 50 n.
m is formed, and a groove 350 is formed.
Is reduced from 0.25 μm width to 0.15 μm width.

Next, as shown in FIG. 8E, for example, a resist 342 is applied as a mask layer, the groove 350 is filled, and the resist 342 is formed on the mold layer 322 so as to have a height of about 100 nm. Form a film. The resist 342 serving as the mask layer can be made of another material as long as the etching selectivity with respect to the mold layer 322, the sidewall 324, and the wiring material layer 331 can be obtained.

Next, as shown in FIG. 9F, the resist 342 is removed by, for example, oxygen reactive ion etching.
Etch back by 00nm, fill groove, 400n height
A resist 343 having a wiring pattern of m is formed.

Next, as shown in FIG. 9 (g), the silicon oxide layer 322 and the sidewalls 324 are completely removed with, for example, a hydrofluoric acid aqueous solution, and the width is 0.15 μm and the height is 4 μm.
The resist 343 having a wiring pattern of 00 nm is left.

Next, as shown in FIG. 9H, using the patterned resist 343 as a mask, the polysilicon layer 331 is anisotropically etched to a thickness of 100 nm using, for example, an ECR type poly etcher.
Is formed on the gate electrode pattern 332 to form a reduced gate electrode 332 having a width of 0.15 μm. afterwards,
Impurity ion implantation is performed using the gate electrode 332 and the resist 343 as a mask, and an LDD (Lightly Doped Dr.
ain) After forming 311, the resist 343 is removed.

Next, as shown in FIG. 9I, a silicon oxide layer is formed to a thickness of 100 nm by, for example, a normal pressure CVD method, and then this silicon oxide layer is formed by using, for example, a parallel plate type silicon oxide etcher. By performing 100 nm etch-back, a sidewall 326 made of silicon oxide is formed on the side of the gate electrode, and then ion implantation of impurities is performed using the gate electrode 332 and the sidewall 326 as a mask to form a source / drain diffusion layer. 312 is formed.

Next, as shown in FIG. 10 (j), for example, a silicon oxide layer 327 is formed as an interlayer insulating film to a thickness of 600 nm by a normal pressure CVD method, and is planarized by polishing by, for example, a CMP method.

Next, as shown in FIG. 10 (k), a resist 344 is applied on the interlayer insulating film 327, and a contact hole having a diameter of, for example, 0.3 μm is patterned using an exposure technique. The interlayer insulating film 327 and the gate oxide film 321 are etched using, for example, a magnetron type silicon oxide etcher as a mask,
The source / drain diffusion layer 312 of the substrate is exposed, and a contact hole 351 is formed.

Next, as shown in FIG. 10 (l), after removing the resist 344 by using, for example, a downflow type asher, a tungsten layer is formed to a thickness of 300 nm by, for example, a plasma CVD method, and a contact hole is formed by tungsten. Then, the tungsten layer is etched back by 300 nm using a parallel plate type tungsten etcher to form a tungsten plug 333 connected to the source / drain 312.

Through the above steps, a MOS transistor having a finer 0.15 μm-wide gate electrode could be formed by using the 0.25 μm rule exposure technique.
The alignment during the formation of the contact hole varies, and the gate electrode formed in the above process is 50 nm thicker than in the past, even if the distance between the contact hole and the gate electrode causes a short circuit or insulation failure due to this variation. Since the width is reduced, the distance from the contact hole is increased by that amount, short-circuiting and insulation failure are unlikely to occur, the yield is improved, and the cell size can be reduced. Further, since the effective channel length of the gate electrode is shorter than in the past, a MOS transistor capable of operating at high speed could be formed.

[Embodiment 4] The fourth embodiment shows an example in which the wiring forming method of the present invention is applied to the process of forming a MOS transistor having an extremely thin gate oxide film.
This will be described with reference to FIG.

FIG. 11 shows the beginning of the process, in which (a1) is a plan view and (a2) is a sectional view. The steps leading to these figures will be described. A gate oxide film 421 is formed to a thickness of 5 nm on the silicon substrate 410 by a dry oxidation method, then a polysilicon layer 431 is formed as a wiring material layer to a thickness of 100 nm by, for example, low pressure CVD, and then an oxidization is performed as a first mask layer. A silicon layer 422 is formed to a thickness of 600 nm by a normal pressure CVD method, and then a resist 441 for patterning the silicon oxide layer is applied by spin coating or the like. Patterning of the wiring. in this case,
As shown in the drawing, unlike a normal pattern, the pattern is a negative pattern, and a portion serving as a wiring is opened. Thus, the structures shown in FIGS. 11A1 and 11A2 are obtained.

Next, as shown in FIG. 11B, using the resist 441 as a mask, the silicon oxide layer 422 as the first mask layer is etched to a thickness of 500 nm using, for example, a magnetron type silicon oxide etcher. As a result, the silicon oxide layer 422 has the groove 4 of the wiring pattern.
A polysilicon layer 43 is formed on the bottom of the groove.
There is a remaining 100 nm thick silicon oxide layer on top of 1.

Next, as shown in FIG. 12C, the resist 441 is removed using, for example, a downflow type asher, and then the silicon oxide film 423 is formed by, for example, a low-pressure CVD method or the like with good step coverage. 50
The film is formed with a thickness of nm. In this example, the first mask layer 42
The same silicon oxide as that of No. 2 was deposited, but since this layer functions as a sidewall and is to be removed later, a material different from that of the first mask layer 422 may be used.

Next, as shown in FIG. 12D, the silicon oxide film 423 is etched back by 50 nm using, for example, a parallel plate type silicon oxide etcher. As a result, a 50 nm-thickness reducing wall 424 having a thickness of 50 nm is formed on the side wall of the groove 450 of the wiring pattern of the silicon oxide layer 422, and the width of the opening of the groove 450 is reduced from 0.25 μm width to 0.1%.
Reduce to 5 μm width.

Next, as shown in FIG. 12E, for example, a resist 442 is applied as a second mask layer, and a groove 450 is formed.
And a resist 442 is formed on the silicon oxide layer 422 so as to have a height of about 100 nm. Note that the resist 442 as the second mask layer is composed of the first mask layer 422, the sidewall 424, and the wiring material layer 431.
If the etching selectivity can be obtained, other materials can be used.

Next, as shown in FIG. 13F, the resist 442 is etched back by 200 nm by, for example, oxygen reactive ion etching to fill the groove 450 and form a resist 443 having a wiring pattern of 400 nm in height.

Next, as shown in FIG.
The silicon oxide layer 422 and the sidewalls 424 are etched to a thickness of 600 nm using, for example, a magnetron type silicon oxide etcher, using the patterned resist 443 that fills 0 as a mask. As a result, the resist 443 and the underlying silicon oxide mask 4 are formed in the wiring pattern.
22a is formed. The line width of these laminates is 0.15 μm.

Next, as shown in FIG. 13H, the patterned resist 443 is removed using, for example, an asher and the patterned silicon oxide layer 422a is removed.
Is used as a mask, the polysilicon layer 431 is anisotropically etched to a thickness of 100 nm using, for example, a poly etcher of the ECR method to form the polysilicon layer 431 in a gate electrode pattern. Thus, a stacked body of the reduced gate electrode 432 having a width of 0.15 μm and the offset oxide film 422a thereon is formed. Thereafter, the offset oxide film 42
Impurity ion implantation is performed using 2a and the gate electrode 431 as a mask to form an LDD 411.

Next, as shown in FIG. 13I, a silicon oxide layer is formed to a thickness of 200 nm by, for example, a normal pressure CVD method.
Subsequently, this silicon oxide layer is etched back by 200 nm using, for example, a parallel plate type silicon oxide etcher to form a sidewall 426 made of silicon oxide on the side of the gate electrode 432. The impurity ions are implanted using the gate and sidewall 426 as a mask to form the source / drain diffusion layer 4.
12 is formed.

Next, as shown in FIG. 14 (j), for example, silicon oxide 427 is formed as an interlayer insulating film to a thickness of 600 nm by a normal pressure CVD method, and is planarized by polishing by, for example, a CMP method.

Next, as shown in FIG. 14K, a resist 444 is applied on the interlayer insulating film 427, and a contact hole patterning 451 having a diameter of, for example, 0.3 μm is performed by using an exposure technique. Using the mask as a mask, the interlayer insulating film 427 and the gate oxide film 421 are etched using, for example, a magnetron type silicon oxide etcher to expose the source / drain diffusion layer 412 of the substrate and form a contact hole 451.

Next, as shown in FIG. 14 (l), after removing the resist 444 by using, for example, a downflow type asher, a tungsten layer is formed to a thickness of 300 nm by, for example, a plasma CVD method to form a contact hole 451. The tungsten layer is filled with tungsten, and then the tungsten layer is etched back by 300 nm using a parallel plate type tungsten etcher to form a tungsten plug 433 connected to the source / drain.

Through the above steps, a MOS transistor having a gate electrode of 0.15 μm width having a gate insulating film of 5 nm thickness and an offset oxide film was formed by using the exposure technique of the 0.25 μm rule. When the thickness of the gate oxide film is thinner than the conventional one, for example, 10 nm or less, when the polysilicon layer serving as the gate electrode is etched using a polysilicon etcher with a resist as a mask, the selectivity to silicon oxide is insufficient. The oxide film is etched. However, in this embodiment, the gate oxide film can be used as an etching stopper layer by using the offset oxide film as the inorganic oxide film. The reason is that when the resist is used as a mask, the carbon from the resist reacts with the oxygen of the silicon oxide due to the ion energy, and the etching proceeds.However, in the case of the inorganic mask, the carbon is not supplied, so that the etching conditions are the same. This is because the selectivity to silicon oxide is improved.

As in the third embodiment, it is possible to form a MOS transistor capable of operating at high speed without causing a short circuit with the plug or poor insulation.

[Embodiment 5] The fifth embodiment shows an example in which the wiring forming method of the present invention is applied to a process of forming a MOS transistor having a self-aligned contact using a silicon nitride layer as a stopper. This will be described with reference to FIG.

FIG. 15 shows the beginning of the process, in which (a1) is a plan view and (a2) is a sectional view. The steps leading to these figures will be described. A gate oxide film 521 is formed to a thickness of 10 nm on a silicon substrate 510 by a dry oxidation method, and then a polysilicon layer 531 is formed as a wiring material layer by, for example, low pressure CVD.
Then, a silicon oxide layer 522 as a mask layer is formed to a thickness of 600 nm by a normal pressure CVD method.
Subsequently, a resist 541 for patterning the silicon oxide layer 522 is applied by spin coating or the like, and patterning of a wiring having an opening width of, for example, 0.25 μm is performed by an exposure technique according to a minimum design rule. In this case, as shown in the figure, unlike a normal pattern, the pattern is a negative pattern, and a portion serving as a wiring is opened. Thus, the structure shown in FIGS. 15A1 and 15A2 is obtained.

Next, as shown in FIG. 15B, using the resist 541 as a mask, the silicon oxide layer 522 as a mask layer is etched by 500 nm using, for example, a magnetron type silicon oxide etcher. Thereby, the groove 550 of the wiring pattern is formed in the silicon oxide layer 522.
Is formed, and a polysilicon layer 5 is formed on the bottom of the groove 550.
There is a 100 nm thick silicon oxide layer left over 31.

Next, as shown in FIG. 16C, the resist 541 is removed by using, for example, a downflow type asher, and then the silicon oxide film 523 is formed by, for example, a low-pressure CVD method or the like with good step coverage. 50
The film is formed with a thickness of nm. In this example, the same silicon oxide as that of the mask layer 522 is deposited, but since this layer functions as a sidewall and is to be removed later, a material different from that of the mask layer 522 may be used.

Next, as shown in FIG. 16D, the silicon oxide film 523 is etched back by 50 nm using, for example, a parallel plate type silicon oxide etcher. As a result, a 50 nm-thickness reducing wall 524 having a thickness of 50 nm is formed on the side wall of the groove 550 of the wiring pattern of the silicon oxide layer 522, and the width of the opening of the groove 550 is changed from 0.25 μm width to 0.1%.
Reduce to 5 μm width.

Next, as shown in FIG. 16E, for example, a resist 542 is applied to fill the groove 550, and a resist 542 is formed on the silicon oxide layer 522 so as to have a height of about 100 nm. . As the resist 542, another material can be used as long as the etching selectivity with the mask layer 522, the sidewall 524, and the wiring material layer 531 can be obtained.

Next, as shown in FIG. 17F, the resist 542 is etched back by 200 nm by, for example, oxygen reactive ion etching to fill the groove 550 and form a resist 543 having a wiring pattern of 400 nm in height.

Next, as shown in FIG.
The silicon oxide layer 522 and the sidewall 524 are etched to a thickness of 600 nm by using, for example, a magnetron type silicon oxide etcher, using the patterned resist 543 that fills 0 as a mask. As a result, the resist 543 and the underlying silicon oxide mask 5
22a is formed. The line width of these laminates is 0.15 μm.

Next, as shown in FIG. 17H, the patterned resist 543 is removed using, for example, an asher and the patterned silicon oxide layer 522a is removed.
Is used as a mask to anisotropically etch the polysilicon layer 531 using, for example, an ECR type poly etcher to form a polysilicon layer in a gate electrode pattern. Thus, a stacked body of the reduced gate electrode 532 having a width of 0.15 μm and the offset oxide film 522a thereon is formed. Then, the offset oxide film 522a
Then, ion implantation of impurities is performed using the gate electrode 532 as a mask to form an LDD 511.

Next, as shown in FIG. 17I, a silicon oxide layer is formed to a thickness of 200 nm by, for example, a normal pressure CVD method.
Subsequently, this silicon oxide layer is etched back by, for example, 200 nm using a parallel plate type silicon oxide etcher to form a side wall 526 made of silicon oxide on the side of the gate electrode 532. The impurity ion implantation is performed using the mask and the sidewalls 526 as masks to form the source / drain diffusion layers 5.
12 is formed.

Next, as shown in FIG. 18J, the silicon nitride layer 527 as a stopper layer is
A 50 nm film is formed by a method D, and a silicon oxide layer 528 is subsequently formed as an interlayer insulating film to a thickness of 500 nm by a normal pressure CVD method.
A film is formed and planarized by polishing, for example.

Next, as shown in FIG. 18 (k), a resist 544 is applied on the interlayer insulating film 528, and a contact hole having a diameter of, for example, 0.3 μm is patterned using an exposure technique. Using, for example, a magnetron type silicon oxide etcher as a mask, the interlayer insulating film 528 is etched to a position above the stopper layer 527 under a high selectivity ratio to silicon nitride.

Next, as shown in FIG. 18 (l), after the resist 544 is removed using, for example, a downflow type asher, the stopper layer 527 exposed at the bottom of the contact hole 551 is removed, for example, using a magnetron type. The source / drain diffusion layer 512 of the substrate 510 is exposed by etching with a silicon nitride etcher at a selectivity to silicon oxide of 50 nm.

Next, as shown in FIG. 18M, a tungsten layer is formed to a thickness of 300 nm by, for example, a plasma CVD method, and the contact holes are filled with tungsten. Then, the tungsten layer is formed using a parallel plate type tungsten etcher. Etch back by 300 nm to form a tungsten plug 533 connected to the source / drain 512.

Through the above steps, a MOS transistor having a gate electrode having a width of 0.15 μm and an offset oxide film and having a self-aligned contact structure can be formed by using the 0.25 μm rule exposure technique. According to the present embodiment,
Even if the selectivity to silicon nitride is slightly lower, the stopper layer at the sidewall shoulder is etched, and the distance between the gate electrode and the wiring plug becomes shorter, the gate electrode formed in the above process has a line width of 50 nm compared to the conventional one. Since the size is reduced, the distance from the contact hole increases by that much,
Short circuit and insulation failure are less likely to occur, and the yield is improved. Also,
When an etching condition with a high selectivity to silicon nitride was used, the width of the slit portion at the bottom of the contact hole was widened, so that the occurrence of an etch stop could be suppressed.

When this embodiment is used in a DRAM cell, a cross-sectional structure as shown in FIG. 19, for example, could be formed. 19, the same components as those in FIG. 18 are denoted by the same reference numerals. Also in this case, since the gate electrode width can be formed narrow without increasing the cell size, the slit width can be increased and the occurrence of etch stop can be suppressed.

[Embodiment 6] In a sixth embodiment, a method for forming a wiring according to the present invention is a MOS having a self-aligned contact in which an offset insulating film laminated on a side wall of a gate electrode side wall and a gate electrode is made of silicon nitride. An example in which the present invention is applied to a transistor forming step will be described with reference to FIGS.

FIG. 20 shows the beginning of the process, in which (a1) is a plan view and (a2) is a cross-sectional view. The steps leading to these figures will be described. A gate oxide film 621 is formed to a thickness of 10 nm on the silicon substrate 610 by a dry oxidation method, and then a polysilicon layer 631 is formed as a wiring material layer by, for example, low pressure CVD.
And a silicon nitride layer 6 as a mask layer functioning as an offset insulating film and a mold layer.
22 is formed to a thickness of 600 nm by a normal pressure CVD method, and then a resist 641 for patterning the silicon nitride layer 622 is applied by spin coating or the like.
Patterning of a μm wiring is performed. In this case, as shown in the figure, unlike a normal pattern, the pattern is a negative pattern, and a portion serving as a wiring is opened. As a result, the structures shown in FIGS. 20 (a1) and (a2) are obtained.

Next, as shown in FIG. 20B, using the resist 641 as a mask, the silicon nitride layer 622 is etched by 500 nm using, for example, a magnetron type silicon nitride etcher. As a result, a groove 650 of a wiring pattern is formed in the silicon nitride layer 622, and the bottom of the groove 650 has a 100 nm-thick silicon nitride layer remaining on the polysilicon layer 631.

Next, as shown in FIG. 21C, the resist 641 is removed using, for example, a downflow type asher, and thereafter, silicon nitride is removed to a thickness of, for example, 50 nm by a method having good step coverage such as a low pressure CVD method. The film is formed to have a thickness. In this example, the same silicon nitride as the mask layer 622 was deposited, but since this layer functions as a sidewall and is to be removed later, the mask layer 622 is used.
And different materials.

Next, as shown in FIG. 21D, the silicon nitride film 623 is etched back by, for example, a parallel plate silicon nitride etcher of 50 nm. As a result, a thickness of 5
A sidewall 624 for reducing the diameter of 0 nm is formed.
The width of the opening 50 is reduced from 0.25 μm width to 0.15 μm width.

Next, as shown in FIG. 21E, a resist 642 is applied to fill the groove 650, and the silicon nitride layer 6 is formed.
A resist 642 is formed on the substrate 22 so as to have a height of about 100 nm. As the resist 642, another material can be used as long as the etching selectivity with the mask layer 622, the sidewall 624, and the wiring material layer 631 can be obtained.

Next, as shown in FIG. 22F, the resist is removed by, for example, oxygen reactive ion etching.
Etch-back is performed to fill the groove, and a resist 643 having a wiring pattern of 400 nm in height is formed.

Next, as shown in FIG. 22 (g), the silicon nitride layer 622 and the sidewalls 624 are formed by using, for example, a magnetron type silicon nitride etcher with the patterned resist 643 filling the groove as a mask.
Etch 00 nm. Thereby, the resist 643 and the silicon nitride mask 622a thereunder are formed in the wiring pattern.
Is formed. The line width of these laminates is 0.
15 μm.

Next, as shown in FIG. 22H, the patterned resist 643 is removed using, for example, an asher, and the patterned silicon nitride layer 622a is removed.
Is used as a mask, the polysilicon layer 632 is anisotropically etched by 100 nm using, for example, an ECR type poly etcher to form a polysilicon layer 631 as a gate electrode pattern. Thus, a stacked body of the reduced gate electrode 632 having a width of 0.15 μm and the offset nitride film 622a thereon is formed. Thereafter, the offset nitride film 62
Using the 2a and the gate electrode 632 as a mask, impurity ions are implanted to form an LDD 611.

Next, as shown in FIG. 22I, a silicon nitride layer is formed to a thickness of 200 nm by, for example, a normal pressure CVD method.
Subsequently, this silicon nitride layer is etched back by 200 nm using, for example, a parallel plate type silicon nitride etcher to form a sidewall 626 made of silicon nitride on the side of the gate electrode 632. The impurity ions are implanted using the gate and sidewall 626 as a mask, and the source / drain diffusion layer 6
Form 10.

Next, as shown in FIG. 23J, for example, a silicon oxide layer 627 is formed as an interlayer insulating film to a thickness of 600 nm by a normal pressure CVD method, and is flattened by, for example, polishing by a CMP method.

Next, as shown in FIG. 23K, a resist 644 is applied on the interlayer insulating film 627, and a contact hole patterning 651 having a diameter of, for example, 0.3 μm is performed by using an exposure technique. Is used as a mask, for example, a magnetron type silicon oxide etcher is used, and the interlayer insulating film 627 is formed under a high selectivity ratio to silicon nitride.
And the gate oxide film 621 are etched and the source
The drain diffusion layer 612 is exposed, and the contact hole 6 is exposed.
51 are formed.

Next, as shown in FIG. 23 (l), after removing the resist 644 using, for example, a downflow type asher, a tungsten layer is formed to a thickness of 300 nm by, for example, a plasma CVD method to form a contact hole. Then, the tungsten layer is etched back by 300 nm using a parallel plate type tungsten etcher to form a tungsten plug 633 connected to the source / drain.

By the above steps, a MOS transistor having a gate electrode of 0.15 μm width and an offset nitride film and having a self-aligned contact structure was formed by using the 0.25 μm rule exposure technique. According to the present embodiment,
Since the gate electrode is surrounded by a thick etching stopper layer, the selectivity to silicon nitride is slightly lower,
Even if the side wall made of silicon nitride is etched, it does not affect the breakdown voltage of the gate electrode. In addition, when etching conditions with a high selectivity to silicon nitride were used, the width of the slit at the bottom of the contact hole was widened, so that the occurrence of etch stop could be suppressed.

When this embodiment is used in a DRAM cell, a cross-sectional structure as shown in FIG. 24, for example, could be formed. 24, the same components as those in FIG. 23 are denoted by the same reference numerals. Also in this case, since the gate electrode width can be formed narrow without increasing the cell size, the slit width can be increased and the occurrence of etch stop can be suppressed.

The present invention is not limited to the above embodiment. For example, the etching plasma source, apparatus configuration, sample structure, etching process conditions, and the like can be variously changed without departing from the spirit of the present invention.

[0104]

According to the wiring forming method of the present invention, it is possible to surely form a wiring layer having a line width smaller than the minimum line width by the exposure technique.

According to the method of manufacturing a semiconductor device of the present invention,
By applying this wiring forming method, a gate electrode narrower than the minimum line width by the exposure technique can be surely formed.

[Brief description of the drawings]

FIGS. 1 (a1), (a2), and (b) are cross-sectional views illustrating manufacturing steps of a first embodiment.

FIGS. 2 (c) to 2 (e) are cross-sectional views showing a step that follows the step of FIG.

FIGS. 3 (f) to 3 (h) are cross-sectional views showing steps subsequent to FIG.

FIGS. 4 (a1), (a2) and (b) are cross-sectional views showing manufacturing steps of the second embodiment.

FIGS. 5 (c) to 5 (e) are cross-sectional views showing steps subsequent to FIG.

FIGS. 6 (f) to 6 (h) are cross sections showing steps subsequent to FIG.

FIGS. 7 (a1), (a2), and (b) are cross-sectional views showing manufacturing steps of the third embodiment.

8 (c) to 8 (e) are cross-sectional views showing a step that follows the step of FIG.

FIGS. 9 (f) to 9 (i) are cross-sectional views showing steps subsequent to FIG.

FIGS. 10 (j) to (l) are cross-sectional views showing a step that follows the step of FIG.

FIGS. 11 (a), (a2), and (b) are cross-sectional views showing manufacturing steps of the fourth embodiment.

FIGS. 12 (c) to 12 (d) are cross-sectional views showing a step that follows the step of FIG.

13 (f) to (i) are cross-sectional views showing a step following the step shown in FIG.

FIGS. 14 (j) to (l) are cross-sectional views showing steps subsequent to FIG.

FIGS. 15 (a1), (a2), and (b) are cross-sectional views showing manufacturing steps of the fifth embodiment.

16 (c) to (e) are cross-sectional views showing a step that follows the step of FIG.

17 (f) to 17 (i) are cross-sectional views showing a step that follows the step of FIG.

18 (j) to (m) are cross-sectional views showing a step that follows the step of FIG.

FIG. 19 is a cross section showing an example in which the fifth embodiment is applied to a DRAM cell.

FIGS. 20 (a1), (a2), and (b) are cross-sectional views showing manufacturing steps of the sixth embodiment.

21 (c) to (e) are cross sections showing a step following the step shown in FIG.

FIGS. 22 (f) to (i) are cross-sections showing a step that follows the step shown in FIG. 21.

FIGS. 23 (j) to (l) are cross-sectional views showing a step following the step shown in FIG. 22.

FIG. 24 is a sectional view showing an example in which the sixth embodiment is applied to a DRAM cell.

FIGS. 25A to 25C are cross-sectional views showing steps of a conventional self-aligned contact.

FIG. 26 is a cross-sectional view showing a problem of a conventional self-aligned contact.

FIG. 27 is a cross-sectional view showing a problem of a conventional self-aligned contact.

FIG. 28 is a cross-sectional view illustrating a conventional resist thinning technique.

FIG. 29 is a cross-sectional view for explaining a problem of a conventional resist thinning technique.

[Explanation of symbols]

123: sidewall for reducing diameter, 121: formwork layer, 13
DESCRIPTION OF SYMBOLS 1 ... Conductive material layer, 143 ... Resist with reduced diameter, 13
2. Wiring layer with reduced diameter

Claims (9)

[Claims] 1. A step of forming a conductive material layer on a substrate, a step of forming a mold layer on the conductive material layer, and forming a groove of a wiring pattern penetrating the mold layer. Forming a sidewall for reducing the diameter of the groove of the wiring pattern, filling the groove formed with the sidewall with a mask layer, removing the mold layer and the sidewall for reducing the diameter. A step of exposing a mask layer patterned by the step (c), and a step of forming a wiring layer by anisotropically etching the conductive material layer using the mask layer as a mask. 2. The method according to claim 1, wherein said mask layer is a resist. 3. A step of forming a conductive material layer on the substrate, a step of forming a first mask layer on the conductive material layer, and a step of forming a bottom of the first mask layer on the first mask layer. Forming a groove of the wiring pattern while leaving the groove, a step of forming a sidewall for reducing diameter on a side wall of the groove of the wiring pattern, a step of filling the groove formed with the sidewall with a second mask layer, Using the second mask layer as a mask, removing the first mask layer and the sidewalls for diameter reduction by anisotropic etching to obtain a laminate of the first mask layer and the second mask layer having a wiring pattern; Forming a wiring layer by anisotropically etching the conductive material layer using the first mask layer or a laminate of the first mask layer and the second mask layer as a mask. 4. The method according to claim 3, wherein said first mask layer is made of an inorganic material. 5. A step of forming a conductive material layer on a semiconductor substrate, a step of forming a mold layer on the conductive material layer, and forming a groove of a gate electrode pattern penetrating the mold layer. Forming, forming a sidewall for reducing the diameter on the side wall of the groove of the gate electrode pattern, filling the groove on which the sidewall has been formed with a mask layer, and forming the mold layer and the sidewall for reducing the diameter. Exposing the patterned mask layer to form a gate electrode by anisotropically etching the conductive material layer using the mask layer as a mask; forming sidewalls on sidewalls of the gate electrode; Forming an impurity diffusion layer on the semiconductor substrate by ion implantation using the gate electrode and / or the sidewall as a mask; and forming an interlayer insulating film covering the gate electrode. A method of manufacturing a semiconductor device, comprising: forming a contact hole to the impurity diffusion layer in the interlayer insulating film; and filling the contact hole with a conductive material to form a plug. 6. The method of manufacturing a semiconductor device according to claim 5, wherein said interlayer insulating film is formed after forming an etching stopper layer covering said sidewalls and a gate electrode. 7. A step of forming a conductive material layer on a semiconductor substrate, a step of forming a first mask layer on the conductive material layer, and a step of forming the first mask layer on the first mask layer. Forming a groove of the gate electrode pattern while leaving the bottom; forming a sidewall for reducing diameter on a side wall of the groove of the gate electrode pattern; filling the groove formed with the sidewall with a second mask layer Using the second mask layer as a mask, removing the first mask layer and the sidewalls for diameter reduction by anisotropic etching, and forming a stacked body of the first mask layer and the second mask layer patterned into a gate electrode. Obtaining, a step of forming a gate electrode by anisotropically etching the conductive material layer using the first mask layer or a laminate of the first mask layer and the second mask layer as a mask, and a side wall of the gate electrode. Side wall Forming an impurity diffusion layer in the semiconductor substrate by ion implantation using the gate electrode and / or the sidewall as a mask; forming an interlayer insulating film covering the gate electrode; Forming a contact hole to an impurity diffusion layer that penetrates through the contact hole, and forming a plug by filling the contact hole with a conductive material. 8. The method of manufacturing a semiconductor device according to claim 7, wherein said first mask layer and sidewalls of a side wall of said gate electrode are made of silicon nitride. 9. The method of manufacturing a semiconductor device according to claim 7, wherein said interlayer insulating film is formed after forming an etching stopper layer covering said sidewall and gate electrode.