JPH01170031A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH01170031A JPH01170031A JP32712387A JP32712387A JPH01170031A JP H01170031 A JPH01170031 A JP H01170031A JP 32712387 A JP32712387 A JP 32712387A JP 32712387 A JP32712387 A JP 32712387A JP H01170031 A JPH01170031 A JP H01170031A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- air
- layers
- wiring
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000007747 plating Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims abstract 18
- 239000011229 interlayer Substances 0.000 claims abstract 4
- 239000011810 insulating material Substances 0.000 claims abstract 2
- 239000002184 metal Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 2
- 239000011800 void material Substances 0.000 claims 2
- 239000000463 material Substances 0.000 abstract description 6
- 238000000576 coating method Methods 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係り、特に超高速、超高周波動作
に好適な金属配線構造の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a method for manufacturing a metal wiring structure suitable for ultra-high speed and ultra-high frequency operation.
半導体装置の金属配線において、配線部分の寄生容量を
減少させることが、半導体装置の高速化に有利であり(
例えばT 、 Enoki et aΩ:エレクトロニ
クスレター、Vofl、22、Na2.PP68(19
86)に記載されている。)、その具体的な方法として
、いわゆるエアーブリッジ方式が有効である事は公知で
ある(例えば、T 、 Andrade :ソリツドス
テートテクノロジー誌、1985年版。In the metal wiring of semiconductor devices, reducing the parasitic capacitance of the wiring portion is advantageous for increasing the speed of semiconductor devices (
For example, T. Enoki et aΩ: Electronics Letters, Vofl, 22, Na2. PP68 (19
86). ), it is well known that the so-called air bridge method is effective as a specific method (for example, T. Andrade: Solid State Technology Magazine, 1985 edition).
第2号、PP199に記載されている。)。No. 2, PP199. ).
上記従来技術では、金属配線層が空中に走るため、通常
の厚さでは強度が不十分で、通常〜1.5μm以上の厚
さを必要としていた。この方法として、所定の部分に選
択的に厚い金属配線層とするため、ホトレジストなどで
マスクした選択メッキ法が用いられていた。この方法で
は、厚くて、かつ微細な配線パターンを簡便に形成でき
る利点を有するが、空気配線層を2層以上(配線層が空
気を介して交替する部分が、最低2層以上)とするよう
なプロセスには適用ができなかった。In the above-mentioned conventional technology, since the metal wiring layer runs in the air, the strength is insufficient with a normal thickness, and a thickness of 1.5 μm or more is usually required. As this method, a selective plating method using a mask such as photoresist has been used in order to selectively form a thick metal wiring layer in a predetermined portion. This method has the advantage of being able to easily form thick and fine wiring patterns, but it is recommended that there be two or more air wiring layers (at least two or more layers where wiring layers are alternated through air). It could not be applied to other processes.
本発明の目的は、空中配線層を形成する方法において、
プロセス上、平坦な表面を保って加工を行なうことによ
って、少なくとも2層以上の空中配線を実現する方法を
提供することにある。An object of the present invention is to provide a method for forming an aerial wiring layer,
The object of the present invention is to provide a method for realizing at least two or more layers of aerial wiring by performing processing while maintaining a flat surface.
上記目的は、選択メッキを行なうために、あらかじめ薄
い金属層を被着する工程(多くの場合、全面に被着する
)において、上記金属層が、酸化又はエツチングを容易
に行なえるような材質又は構成で製造されることを特徴
とした方法により、達成される。The above purpose is to make the metal layer made of a material that can be easily oxidized or etched or This is achieved by a method characterized in that it is manufactured in a configuration.
配線等を施こすための選択メッキを行なうために、あら
かじめ薄い第1の金属層を被着し、この金属層が、酸化
又はエツチングを容易になし得る材質又は構成にしてい
るため、極めて容易に除去され、エアーブリッジ配線が
可能となる。In order to perform selective plating for wiring, etc., a thin first metal layer is deposited in advance, and this metal layer is made of a material or structure that can be easily oxidized or etched, so it is extremely easy to oxidize or etch. removed, allowing air bridge wiring.
以下、本発明の一実施例を第1図(a)と(b)により
説明する。本例はGaAs ICにおけるMESFE
Tに第1.第2の金属配線層をエアーブリッジで形成し
たものである。半絶縁性GaAs基板結晶101に、n
又はn小型G a A s層102を形成し、ソース電
極103.ゲート電極104、ドレイン電極105を周
知の方法で形成したFETにCVD法による5iOz膜
105を被着した。An embodiment of the present invention will be described below with reference to FIGS. 1(a) and 1(b). This example is a MESFE in GaAs IC.
First to T. The second metal wiring layer is formed by an air bridge. On the semi-insulating GaAs substrate crystal 101, n
Alternatively, an n-sized GaAs layer 102 is formed, and a source electrode 103 . A 5iOz film 105 was deposited by CVD on an FET in which a gate electrode 104 and a drain electrode 105 were formed by a well-known method.
この後、所定の部分にコンタクト孔を加工して、全面に
わたってMO層201を1100nの厚さ、被着した。Thereafter, contact holes were formed in predetermined portions, and an MO layer 201 with a thickness of 1100 nm was deposited over the entire surface.
この後、約3μmの厚さのホトレジスト層に第1金属配
線層の部分202の孔をあけて、上述したMo層201
を電解メッキの陰極板として、Auを約3μmの厚さに
メッキして第1金属配線層202を形成した。つづいて
、上記レジストを残したまN、約500nm厚さの第2
のコンタクトホール用レジスト層302を加工して、全
面にわたってMo層203を1100nの厚さ、被着し
た。この後、同様の方法で、第2金属配線層の部分20
4の孔をあけて、この部分にAuを約3μmの厚さにメ
ッキで形成した(第1図(a))。After this, a hole is made in the photoresist layer with a thickness of about 3 μm for the portion 202 of the first metal wiring layer, and the above-mentioned Mo layer 202 is formed.
was used as a cathode plate for electrolytic plating, and Au was plated to a thickness of about 3 μm to form a first metal wiring layer 202. Next, leaving the above resist, a second layer with a thickness of about 500 nm was applied.
The contact hole resist layer 302 was processed, and a Mo layer 203 with a thickness of 1100 nm was deposited over the entire surface. Thereafter, in the same manner, the portion 20 of the second metal wiring layer is
A hole No. 4 was made, and Au was plated on this portion to a thickness of about 3 μm (FIG. 1(a)).
このような形状をえたあと、レジスト層303を02ア
ツシヤで除去し、つづいて現われるMo層203をCF
4系のガスを用いたRIE (リアクティブイオンエッ
チ)で除去し、さらに再び現われたレジスト層302と
301を02アツシヤで除去し、つづいて現われたMO
層201をRIEで除去した。こうした後、第1−第2
金属層間は空中でクロスして太られている。さらに5i
ft膜105はHF系のウェットエッチで静かに除去し
て、全ての層間をエアーブリッジで形成した(第1図(
b))。この断面図が第1図(a)から(b)に示され
ている。After obtaining such a shape, the resist layer 303 is removed by 02 assher, and the Mo layer 203 that appears subsequently is removed by CF.
The resist layers 302 and 301 that appeared again were removed by RIE (reactive ion etching) using a 4-based gas, and then the resist layers 302 and 301 that appeared again were removed using a 02 assher.
Layer 201 was removed by RIE. After this, 1st-2nd
The metal layers are thickened by crossing each other in the air. Further 5i
The ft film 105 was gently removed by HF-based wet etching, and air bridges were formed between all layers (see Figure 1).
b)). This cross-sectional view is shown in FIGS. 1(a) to 1(b).
本発明の製造方法において、第1層の金属配線層が厚い
(〜3μm)、にかかわらず、第2,1i9jが平坦な
平面に加工できるのは、ホトレジスト層301と302
をプロセスの途中で取除かないためである。従来では、
第1の金属配線層をメッキで形成したあと、レジスト層
301に除去して、メッキ陰極として使った導電層20
1をエツチングしていた。これでは段差が出きすぎて、
微細なパターンからなる第2層配線層を加工することが
できなかった。本発明で述べたように、最下部層に5i
Oz膜を用いた効果は次の理由による。−般にG a
A s ME!5FETはドライエッチに弱く、o2プ
ラズマやRIEでは、特性が劣化する。このため、HF
で静かに除去できるS i Ox膜をFETに接してい
る部分に用いている。In the manufacturing method of the present invention, the second layer 1i9j can be processed into a flat surface regardless of the thickness of the first metal wiring layer (~3 μm) because of the photoresist layers 301 and 302.
This is because they are not removed in the middle of the process. Conventionally,
After forming the first metal wiring layer by plating, the resist layer 301 is removed and the conductive layer 20 is used as a plating cathode.
I was etching 1. This creates too many steps,
It was not possible to process the second wiring layer consisting of a fine pattern. As mentioned in the present invention, 5i in the bottom layer
The effect of using the Oz film is due to the following reason. -Generally Ga
As ME! 5FET is susceptible to dry etching, and its characteristics deteriorate with O2 plasma or RIE. For this reason, HF
A SiOx film, which can be gently removed with a vacuum cleaner, is used in the area in contact with the FET.
本発明の実施例では、電解メッキの陰極にMOを用いた
例を述べた。これはドライエッチで容易に取除けるため
で、この他の材料としてNi。In the embodiments of the present invention, an example was described in which MO was used as a cathode for electrolytic plating. This is because it can be easily removed by dry etching, and other materials include Ni.
Ti、Cu、W、WSixなどを用いてもよい。Ti, Cu, W, WSix, etc. may also be used.
この場合、電解メッキの初期段階でAuが被着しにくい
ものもあるが、ストライクメッキをしたり、あるいはN
i、Cuなどをわずかバインダーとしてメッキしておく
だけで良好なものがえられる。In this case, it may be difficult for Au to adhere at the initial stage of electrolytic plating, but strike plating or N
A good product can be obtained by simply plating with a small amount of i, Cu, etc. as a binder.
なお本発明の実施例をGaAsICとして述べたが、本
発明がInP他種他種化合物半導体装置、あるいはSi
半導体装置において、超高速性を追求する場合に、同様
に有効であることは発明の原理から明白である。また配
線金属はAu以外のCu g A gなど、選択メッキ
のマスクとしてホトレジスト以外のもの(例えば三層レ
ジストの下部層を用いる場合は単なるポリマで良い)を
任意に選択可能である。Although the embodiment of the present invention has been described as a GaAs IC, the present invention is applicable to InP and other types of compound semiconductor devices, or Si
It is clear from the principle of the invention that the present invention is similarly effective in pursuing ultra-high speed in semiconductor devices. Further, the wiring metal can be arbitrarily selected from a material other than photoresist (for example, when using the lower layer of a three-layer resist, a simple polymer may be used) as a mask for selective plating, such as Cu g A g other than Au.
本発明によれば、エアーブリッジ配線を二層間以上にわ
たって形成できるため、IC設計の自由度を増して、か
つ集積度の高いICをエアブリッジで実現できる効果が
ある。これによって素子性能を配線遅延によってそこな
うことなく超高速性かえられる。According to the present invention, since air bridge wiring can be formed across two or more layers, the degree of freedom in IC design can be increased, and a highly integrated IC can be realized using air bridges. This allows ultra-high speeds to be achieved without deteriorating device performance due to wiring delays.
第1図は本発明の一実施例のGaAsIC半導体装置の
断面図である。FIG. 1 is a sectional view of a GaAs IC semiconductor device according to an embodiment of the present invention.
Claims (1)
属配線層で配線してなる半導体装置において、層間絶縁
材の一部あるいは全部が少なくとも空隙(空気、N_2
など)を構成し、上記金属配線層は少なくとも二層以上
からなる半導体装置。 2、金属配線層が電解法の選択メッキで形成される工程
と、容易に除去可能な層間膜を用いた工程とを有するこ
とを特徴とする半導体装置の製造方法。 3、特許請求の範囲第2項記載の半導体装置の製造方法
において、全面に金属層と第一層配線層を形成した後に
、所定の工程で第二層配線層を形成し、その後に、全面
の金属層と層間膜層を取去ることによって空隙を形成す
る工程を含むことを特徴とする半導体装置の製造方法。[Claims] 1. In a semiconductor device in which elements on a semiconductor substrate on which semiconductor elements are formed are interconnected by a metal wiring layer, part or all of the interlayer insulating material has at least a void (air, N_2
etc.), and the metal wiring layer is composed of at least two or more layers. 2. A method for manufacturing a semiconductor device, comprising a step in which a metal wiring layer is formed by selective plating using an electrolytic method, and a step in which an easily removable interlayer film is used. 3. In the method for manufacturing a semiconductor device as set forth in claim 2, after forming a metal layer and a first wiring layer on the entire surface, a second wiring layer is formed in a predetermined step, and then a second wiring layer is formed on the entire surface. 1. A method of manufacturing a semiconductor device, comprising the step of forming a void by removing a metal layer and an interlayer film layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32712387A JPH01170031A (en) | 1987-12-25 | 1987-12-25 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32712387A JPH01170031A (en) | 1987-12-25 | 1987-12-25 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01170031A true JPH01170031A (en) | 1989-07-05 |
Family
ID=18195563
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32712387A Pending JPH01170031A (en) | 1987-12-25 | 1987-12-25 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01170031A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002084732A3 (en) * | 2001-04-13 | 2003-05-01 | Koninkl Philips Electronics Nv | Method of manufacturing an electronic device |
US9632013B2 (en) | 2007-05-18 | 2017-04-25 | Optiscan Biomedical Corporation | Fluid injection and safety system |
US9907504B2 (en) | 2001-11-08 | 2018-03-06 | Optiscan Biomedical Corporation | Analyte monitoring systems and methods |
-
1987
- 1987-12-25 JP JP32712387A patent/JPH01170031A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002084732A3 (en) * | 2001-04-13 | 2003-05-01 | Koninkl Philips Electronics Nv | Method of manufacturing an electronic device |
US9907504B2 (en) | 2001-11-08 | 2018-03-06 | Optiscan Biomedical Corporation | Analyte monitoring systems and methods |
US9632013B2 (en) | 2007-05-18 | 2017-04-25 | Optiscan Biomedical Corporation | Fluid injection and safety system |
US10677688B2 (en) | 2007-05-18 | 2020-06-09 | Optiscan Biomedical Corporation | Fluid injection and safety system |
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