JPH046838A - Formation method for t-shaped offset gate - Google Patents

Abstract

PURPOSE:To easily offset and form a submicron T-shaped gate pattern inside a recess without using an EB aligner or the like by a method wherein the pattern of an insulating film is formed in the central part inside the recess and a gate electrode is formed inside the recess on one side of the pattern. CONSTITUTION:A first insulating-film pattern 2 is formed on a semiconductor substrate 1; a second insulating-film pattern 5 is formed in the central part of a recessed part 4 formed at its end part; a gate electrode 9 is formed between the first and second insulating films 2, 5; the gate electrode 9 is formed in an offset position inside said recessed part 4. For example, a first insulating film 2 is patterned and formed on a GaAs substrate 1; a first recess 4 is formed while a first photoresist pattern 3 formed in a position away from its end part by about 0.3mum is used as a mask. Then, a second insulating film 5 is deposited; the photoresist 3 is removed; after that, a third insulating film 6 is deposited; a second photoresist 7 is patterned and formed; the insulating film 6 is left only on sidewall parts; a second recess 8 is formed; after that, a T-shaped metal 9 is vapor-deposited.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a T-type offset formed by offsetting the gate electrode toward the source electrode in a Schottky barrier type transistor such as GaAs MESFET. The present invention relates to a method of forming a gate.

[Conventional technology]

FIG. 2 is a cross-sectional view of a manufacturing process showing a conventional method of forming an offset gate. In the figure, (11 is a GaAs substrate for forming FETs, etc.), (3) is a photoresist pattern for performing the first layer etching, (4) is the first
(7) is a photoresist pattern for performing the second recess etching to form the gate metal; (8) is the second recess etching portion; (9)
) is the gate metal.

Next, the manufacturing process will be explained.

First, first recess etching (4) is performed using a first photoresist (3) to roughly adjust the operating current value of the FET. This recessed portion (4) is either not shown in the figure or the first photoresist (3) is positioned so as to be centrally located between the source electrode and the train electrode. Next, the gate metal (9) is offset toward the source electrode, and a second resist (7) is positioned and patterned to be formed within the first recessed portion (4).

At this time, the gate length is about 0.5 μm in normal optical exposure, which is the resolution limit of the photoresist, and
．． In order to form a pattern of 25 μm or less, it is necessary to use means such as EB exposure. After forming the second resist (7), in order to finely adjust the operating current value of the FET, a second resist (7) is formed.
Recess etching (8) is performed, and gate metal (9) is deposited and lifted off.

[Invention or problem to be solved]

Conventional offset gates were formed as described above, so in order to offset the gate electrode to the source electrode side, high alignment accuracy was required, and in order to realize a fine gate length of 0.5 μm or less. There is a problem in that it is difficult to use normal optical exposure.

This invention was made to solve the above-mentioned problems, and the alignment accuracy (
(about 0.3 μm) resolution limit (about 0.5 μm).
An object of the present invention is to obtain a method for forming a T-type offset gate that can be formed by offsetting the gate length by 5 μm or less.

[Means to solve the problem]

The method for forming a T-shaped offset gate according to the present invention makes it possible to form a gate electrode with a gate length of 0.5 μm or less and offset toward the source electrode with alignment accuracy and resolution that are possible with normal optical exposure. It is something that
The structure is such that a dummy insulating film pattern is formed inside the recess, and a gate electrode is formed on a portion sandwiched between the side surfaces of the pattern and one side of the recess.

[For production]

The gate length in this invention is basically determined by the alignment accuracy of the optical exposure apparatus used, and the actual gate length is the value obtained by subtracting twice the thickness of an insulating film called a sidewall from this alignment accuracy. In addition, the offset position is uniquely determined by the sidewall on one side of the dummy pattern of the insulating film inside the recess and the recess edge, and if the alignment accuracy is within 1 μm at most, it is possible to obtain a T-shaped gate electrode. be.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, (1) is a GaAs substrate, (2) is a first insulating film that determines one of the gate ends, (3) is a first photoresist, and (4) is a first photoresist (3). ) is the first recess formed as a mask, (5) is the second insulating film patterned with the first photoresist, (5) is the second insulating film patterned with the first photoresist;
51) is the second photoresist that is removed simultaneously with the first photoresist.
(6) is the third insulating film, (7) is the second photoresist forming the gate metal, (8) is the second photoresist and the first, second, and third insulating films. The second recess (9) formed using the mask is a T-type gate metal formed by the second photoresist.

Next, the manufacturing process will be explained.

First, as shown in Figure 1(a), a GaAs substrate (1
) A first insulating film (2) is deposited by plasma CVD and etched by RIE.

Next, as shown in FIG. 1(b), a first photoresist pattern (3) is formed at a position approximately 0.3 μm away from the end of the first insulating film (2). FIG. 1(C) is a cross-sectional view of the first stitching (4) performed using this pattern (3) as a mask. In addition, in FIG. 1(d), a second insulating film (5) which becomes a dummy pattern is deposited by vapor deposition or ECRCV.
FIG. FIG. 1(e) shows that the first photoresist (3) is removed using a solvent such as acetone, and at the same time the second insulating film on the first photoresist (3) is removed (this process, method (This is called lift-off.) Figure 1) is plasma CVD or optical CV
It is a diagram in which a third insulating film (6) is deposited on the entire surface by the D method or the like. FIG. 1(g) further shows the first insulating film (2) and the second insulating film (2).
A second photoresist (7) is patterned on the insulating film (5), and a third insulating film is formed only on the sidewalls (the remaining film excluding BL is called a sidewall), and a second recess (
8) is a cross-sectional view after performing step 8). The second recess (8) may not be provided if the operating current value of the FET is finely adjusted by the first recess (4). FIG. 1 (Corporation) is a cross-sectional view of the T-type gate metal (9) which is lifted off after being deposited with the second photoresist (7). As shown in the figure, the gate length is the length between the first insulating film (2) and the second insulating film (5) minus the sidewall of the third insulating film (6). , the sidewall thickness is 0.1
If μm, 0.31ttn -2Xo, 1 μm
In this case, a gate length of =0.1 μm can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, an insulating film pattern is formed in the center of the recess, and a gate electrode is formed in the recess on one side of the pattern. Since it can be formed by exposure method, E
This has the advantage that a submicron T-shaped gate pattern can be easily offset and formed within a recess without using a device capable of forming fine patterns such as a B exposure device.

[Brief explanation of drawings]

FIGS. 1A to 1C are cross-sectional views showing the manufacturing process of a T-type offset gate according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the manufacturing process of a conventional offset gate. In the figure, (1) is a GaAs substrate, (2) is a first insulating film, (3) is a first photoresist, (4) is a first recess etching, (5) is a second insulating film, (6) shows the third insulating film, (7) the second photoresist, (8) the second recess etching, and (9) the T-type gate metal. In addition, it is shown. In the figure, the same symbols are the same.

Claims (1)

[Claims] A first insulating film pattern is formed on a semiconductor substrate, a second insulating film pattern is formed in the center of a recess provided at an end of the first insulating film pattern, and a gate electrode is formed between the first and second insulating films. A method for forming a T-shaped offset gate, comprising forming a gate electrode at an offset position within the recess.