JPS62131584A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a minute electrode pattern simply by using a single resist layer, by coating a dielectric film on a substrate having stepped structure, and selectively performing anisotropic etching of a region including a step part. CONSTITUTION:In a GaAs crystal substrate 1, recess etching is performed. An SiO2 dielectric film 2 is applied on the substrate by a chemical vapor deposition method. Resist 3 is applied on the substrate. A hole is provided in the resist including a step part of the dielectric film 2. With the resist pattern as a mask, the dielectric thin film 2 undergoes reactive ion etching, and a metal electrode 4 is formed by a lift-off method. Thus a recess structure is provided, the length of a gate can be shortened and the distance between a source and a drain can be also shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor device having fine electrodes.

[Background of the invention]

The device performance of compound semiconductor field-effect transistors, mainly made of GaAs, can be significantly improved by (1) shortening the gate length (2), shortening the gate-source distance (3), and adopting a recessed structure. It has been known.

In order to satisfy the above requirements (1) and (2), electron beam lithography, which has excellent microfabrication performance and alignment accuracy, is extremely useful. However, a resist with sufficient properties has not yet been developed, and efforts are being made to actually process devices, such as using a multilayer resist method.

In addition, in order to form fine electrodes using the current phosphorography technology, for example, as shown in Figure 1, at the 1981 Electronic Communication and Id Society, Semiconductor and Materials Division National Conference, Yohashi Collection p4, Imai et al. The pedestal mentioned by
There are attempts to shorten the effective gate length by using 14. However, the process is complicated, such as performing oblique vapor deposition twice and then ion milling, and there is a problem that dimensional control and in-plane uniformity are poor. Further, as can be seen from the shape of the electrode 11, there remains a problem in characteristics such as increased capacitance between the substrate and the gate.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that does not involve the above-mentioned complicated steps, but easily forms a fine electrode pattern using a single-layer resist.

[Summary of the invention]

The gist of the present invention is to cover a substrate with a step structure with a dielectric film and selectively etch the region including the step portions by anisotropic etching.

The dielectric film coated on the stepped portion is vertically wider than that coated on the flat portion. Therefore, when anisotropic etching is used, the dielectric film in the flat portion can be etched quickly, making it possible to form fine grooves. Note that the four-part formation formed on the substrate is usually called a recess shape.

[Embodiments of the invention]

The present invention will now be described in detail.

[Example 1] An example in which the present invention is applied to the formation of a gate electrode of a compound semiconductor field effect transistor will be shown with reference to FIG.

(2) Perform recess etching on the GaAs crystal substrate 1.

[Figure (a)] InGaAs is used as the semiconductor crystal substrate 1.
, InP, etc. can also be used.

(2) Cover the dielectric film 5iO22 by chemical vapor deposition. [Figure (b)] Note that as the dielectric film 2, 5iaNa
, SOG, etc. can also be used.

■Novolac-based electron beam positive resist with dry etching resistance RE 5000P (Hitachi Chemical product name) 3
is applied onto the substrate. Openings are provided in the resist on the region of the dielectric film 2 including the step portion using electron beam phosphorography. [Figure (C)] Here, pattern resist 3
It is also possible to use a dry etching resistant negative type resist such as R8200ON (trade name, Hitachi Chemical).

■ Using the resist pattern as a mask, dielectric M film 5iO
z 2 was subjected to reactive ion etching (Reactive Ion 1EtchinH) using CHF s gas.
)do. [Figure (d)] CF4 is used as the etching gas.
etc. can also be used.

(2) Metal electrode 4 is formed by lift-off method.

[Figure (e)] Aluminum was used here, but WSi
It is also possible to use the following.

As shown in FIG. 3, the field effect transistor manufactured using this process has a recessed structure and can have a short gate length (1/4 .mu.m or less), as well as a short source-drain distance.

[Example, 2] In Example 1, form the mask pattern (2).

It is performed using optical (including X-ray) phosphorography technology.

[Example 3] In Example 1, the entire 1 g electrode (2) was formed by coating the entire surface with metal, and then patterning the resist and etching the metal.

[Example 4] In Example 1, a multilayer resist method is used to form the mask pattern (2).

〔Effect of the invention〕

According to the present invention, the electrode 17 with an effective length of 1/4 μm or less can be produced using the current laminating technology and in a simple process.
was formed.

In addition, the source-to-gate distance Qsz16, which is desired to be shortened in a field-effect transistor, could be shortened and controlled accurately by changing the thickness of the dielectric film coated.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a semiconductor device according to the prior art;
The figure is a cross-sectional view for explaining a process of an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a semiconductor device constructed according to an embodiment of the present invention. 1... Semiconductor substrate, 2... Dielectric film (S1021
SOG +5iaNa, etc.), 3... Resist with good dry etch resistance (NPR, MR8, etc. or multilayer resist) 4... Metal for electrode, 5... Semiconductor substrate, 6
... Active layer (for example, n-type GaAs layer) 7 ... Dielectric film (SiOz, SOG r 5iaN4, etc.)
, 8... gate electrode, 9... drain electrode, 10.
... Source electrode, 11... Gate electrode, 12... Source electrode, 13... Drain electrode, 14... 5iO
115... Semiconductor substrate, 16... Gate-source distance Qs□, 17... Effective gate length Qg. 1st item 32nd

Claims (1)

[Claims] forming a concave shape in a semiconductor substrate; coating the semiconductor substrate with a dielectric thin film; and including a part of the stepped portion of the dielectric thin film coated on the edge portion of the concave shape in the opening. A step of forming a resist pattern as shown in FIG. A method of manufacturing a semiconductor device, comprising: