JPS61280673A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To form a gate with a narrow width by a method wherein an aperture is drilled in a photoresist film at the position corresponding to the gate electrode and an insulation film is etched with a taper. CONSTITUTION:Source and drain electrodes 2 and 3 are separately formed on a GaAs substrate 1 and an aperture 7 is drilled in a photoresist film 6 above the position where a gate electrode 9 is to be formed and an insulation film 4 is etched by using the photoresist film 6 as a mask so as to have a taper. At that time, a predetermined inclination is given to the GaAs substrate 1 against the direction of the electrode of a dry etching apparatus. Therefore, for instance, if the width of the aperture of the film 6 is 1.5mum and the thickness of the insulation film 4 is 0.5mum, the exposed part of the GaAs substrate 1 is shifted to the source electrode 2 side by 0.5mum and shortened on the drain electrode 3 side by the length corresponding to the thickness of the photoresist film 6 so that the gate electrode 9 with the width less than 1mum can be formed by evaporation. Then gate electrode material 8 is evaporated on a gate region 7 and the photoresist film 6 and the gate electrode 9 is formed by lifting off the gate electrode material 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a compound semiconductor device, particularly a GaAs-FET.

(b) Conventional Technology In order to improve the performance of GaAs-FETs and GaAs-ICs, it is necessary to form gate polarization with an extremely short gate length, and processing technology in the submicron region is required.

FIG. 2 shows a cross-sectional view of a GaAs-FET. A source electrode (2z) and a drain electrode (c) are provided separately on the surface of the GaAs substrate crystal Qυ, and a gate electrode (2z) is provided between them. There is a region of the N layer (total) and the active layer □□□ that performs FET operation.To improve performance, it is necessary to shorten the width of the gate electrode (241) and reduce the capacitance. As a prior art of FET, for example, Japanese Patent Application Laid-Open No. 59-23565 (HOIL
29/80).

In such a GaAs-FET, the gate electrode C! The shaft is formed by a lift-off method as shown in FIG. That is, as shown in FIG. 3A, after forming a source electrode and a drain electrode on a GaAs substrate (21), a photoresist layer (1) having an open hole is coated in a portion that will become the intended gate region. The opening (5) in the photoresist layer ■ is the gate electrode Q.
The gate width of 4 has been determined. Next, as shown in Figure 3, the gate electrode c! 41 electrode materials are deposited. Aluminum is used as the electrode material. Thereafter, as shown in FIG. 3, a desired gate electrode e41 is formed by a lift-off method in which the photoresist layer is removed by etching.

(/→ Problems to be Solved by the Invention) However, in the above-mentioned GaAs-FET, the holes in the photoresist film are opened so as to correspond to the holes in the gate electrode CI! (5) determines the gate width of the gate electrode C)41. Therefore, there is a limit to the gate width.

B) Means for Solving the Problems The present invention has been made in view of the discontinuity, and the photoresist film (6) is opened so as to correspond to the gate electrode (9), and the photoresist film (6) is masked. The insulating film (4
) by taper etching, a method for manufacturing compound semiconductor devices is realized which greatly improves the drawbacks of the conventional method.

(e) Function According to the present invention, when the insulating film (4) is Taber-etched using the photoresist film (6) as a mask, one of the exposed portions (7) of the GaAs substrate (1) is etched as shown in FIG. Since the part is formed under the insulating film (4), the gate electrode material (8) cannot be deposited on the exposed part (part of the sword), and the gate width of the gate electrode (9) can be formed small. .

(F) Embodiments Below, embodiments of the present invention will be described in detail with reference to FIGS. 1A to 1G.

The first step of the present invention is to form source and drain electrodes (21+31) spaced apart on a GaAs substrate (1) (see FIGS. 1A to 1D).

The GaAs substrate (1) is formed by double epitaxially growing a semi-insulating layer and an N-type buffer layer and an N-type active layer thereon. On the surface of the substrate (1), as shown in FIG. 4) Cover the top with a photoresist layer (5).Subsequently, this photoresist layer (5)
) is used as a mask to etch the insulating film (4) to expose the portion of the substrate (1) where the intended source and drain electrodes (2)+3) will be formed. Thereafter, gold-germanium (Au-Ge) is deposited on the entire surface, and source and drain electrodes (2+
Attach +3+. Furthermore, the gold-germanium on the photoresist layer (5) is removed by a lift-off method of etching the photoresist layer (5), thereby forming source and drain electrodes (2) f31 as shown in FIG. 1C.

In this step, the surface of the substrate tl) between the source and drain electrodes +2) (3) is covered with an insulating film (4). After 7, the insulating film (4) and the source and drain electrodes (21F
3) Cover the top with a photoresist film (6) as shown in Figure 1.

The second step of the present invention is to open a hole in the photoresist film (6) so as to correspond to the gate electrode (9), and to taber-etch the insulating film (4) using the photoresist film (6) as a mask. (See Figure 1, E).

This step is a feature of the present invention, in which an opening (force) for forming the gate electrode (9) is provided in the photoresist layer (6). After that, the insulating film (4) is taper-etched. For example, carbon tetrachloride The insulating substrate (4) is etched by anisotropic dry etching using (CC14) and hydrogen (H2).At this time, a predetermined inclination is given to the GaAs substrate (1) with respect to the electrode direction of the dry etching apparatus.First 45 in figure H
°. Therefore, for example, if the opening of the photoresist film (6) is 1.5 μm and the thickness of the insulating film is 0.5 μm, then
The exposed part (7) of the GaAs substrate (1) has a thickness of 0.5 μm and is closer to the source electrode (2) side, and the resist thickness is shorter on the drain side.
9) can be formed.

The third step of the invention consists in depositing a gate electrode material (8) on the gate area (see FIG. 1) and on the photoresist film (6).

This process involves gate electrode materials such as titanium, platinum, and gold (
By vapor depositing 8), a small gate electrode (9) can be formed as explained in the previous step. Also gate electrode material (8)
When depositing the gate electrode (9), the gate electrode (9) can be formed even smaller if the deposition is performed in a direction opposite to the taper angle when the insulating film (4) is taper-encircled in the previous step.

The fourth step of the invention consists in lifting off the gate electrode material (8) to form a gate electrode (9).

In this step, a desired gate electrode (9) is left and other electrode materials (8) are removed by a lift-off method in which the photoresist layer (6) is removed by etching.

(G) Effects of the Invention According to the present invention, as explained in the second step, the gate of the gate electrode (9) is etched by taper-etching the insulating film (4) using the photoresist film (6) as a mask. Since the width can be formed small, the capacitance can be reduced and the performance can be improved.

[Brief explanation of the drawing]

1A to 1G are cross-sectional views explaining the method for manufacturing a compound semiconductor device of the present invention, and FIG. 2 is a cross-sectional view of a conventional GaAs-F
3A to 3C are cross-sectional views explaining the structure of an ET, and FIGS. 3A to 3C are cross-sectional views explaining a conventional method of manufacturing a GaAs-FET. Explanation of main drawing numbers: (1) is GaAs substrate, +2) +33 is source and drain electrode, (4) is insulating film, (5) (6) is photoresist film, (7) is hole, (8) is Gate electrode material (9) is the gate electrode. Applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Shizuka Sano Mistake 1 Figure A Figure 1 C Figure 1 ≦ Figure 1 E Go to Figure 1 Figure 1 G Figure 310 Figure 3 C

Claims (1)

[Claims] (1) In a method for manufacturing a compound semiconductor device in which a gate electrode with a minute gate length is formed after forming source and drain electrodes on a predetermined compound semiconductor substrate, a step of coating an insulating film and a source/drain electrode with a photoresist film; a step of opening a hole in the photoresist film so as to correspond to the gate electrode, and taper etching the insulating film using the photoresist film as a mask; A method for manufacturing a compound semiconductor device, comprising the steps of: depositing a gate electrode material on the gate region and the photoresist film; and forming a gate electrode by lifting off the gate electrode material.