JPS6246577A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6246577A
JPS6246577A JP18566685A JP18566685A JPS6246577A JP S6246577 A JPS6246577 A JP S6246577A JP 18566685 A JP18566685 A JP 18566685A JP 18566685 A JP18566685 A JP 18566685A JP S6246577 A JPS6246577 A JP S6246577A
Authority
JP
Japan
Prior art keywords
film
opening
side wall
resist film
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18566685A
Other languages
Japanese (ja)
Inventor
Hidemi Takakuwa
高桑 秀美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP18566685A priority Critical patent/JPS6246577A/en
Publication of JPS6246577A publication Critical patent/JPS6246577A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain an electrode having short gate length by forming a side wall to the side wall section of an opening section, narrowing the opening section and shaping the electrode. CONSTITUTION:An SiN film 2 is grown on the surface of an N-GaAs substrate 1, a photo-resist film3 is applied on the surface of the SiN film 2, and a window is bored to the resist film 3 in width through which a comparatively stable opening is acquired. When a film 4 by the quality of a material of etching characteristics (a selection ratio) different from the SiN film 2 is shaped, the SiO2 film 4 is etched in an anisotropic manner and only SiO2 formed on the side wall section of the opening section for the resist film 3 is left and the left SiO2 is used as a side wall 4', the width of the opening is narrowed only by the thickness of the side wall 4'. The SiN film 2 is etched in an isotropic manner through the opening section, and a Schottky metal is evaporated. Lastly, resist 3 is removed, and an unnecessary metal evaporated film 5 is removed through a lift-off.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に、半導体装
置の微細な電極形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming fine electrodes in a semiconductor device.

〔発明の概要〕[Summary of the invention]

本発明は、レジスト膜の開口部を通して電極を形成する
半導体装置の製造方法において、前記開口部側壁部にサ
イドウオールを形成して該開口部を狭めてから電極を形
成することにより、短ゲート長の電極を得るものである
The present invention provides a method for manufacturing a semiconductor device in which an electrode is formed through an opening in a resist film. This is to obtain an electrode.

r従来の技術〕 従来の半導体装置の電極形成方法は、例えば特開昭52
−47372号公報に記載のように、先ず、基板上にス
ペーサとする被エツチング材を成長させ、この上にレジ
ストを塗布して該レジスト膜に所要の開口部を設けてい
る0次に、このレジスト膜の開口部を通して被エツチン
グ材を等方性エツチングし、被エツチング材をレジスト
膜開口部より横方向にもエツチングしてレジスト膜開口
端部が被エツチング材端部より張り出す構造とする。そ
して、レジスト膜開口部を通してメタルを蒸着し基板上
にケ゛−ト電極を形成し、その後リフトオフ技術により
レジスト膜を溶かして該レジスト膜上に付着している不
用のメタル蒸若膜を除去している。
rPrior art] A conventional method for forming electrodes of a semiconductor device is described, for example, in JP-A-52
As described in Japanese Patent No. 47372, first, a material to be etched as a spacer is grown on a substrate, and a resist is applied thereon to form the required openings in the resist film. The material to be etched is isotropically etched through the opening of the resist film, and the material to be etched is also etched laterally from the opening of the resist film, so that the opening end of the resist film protrudes from the end of the material to be etched. Then, a gate electrode is formed on the substrate by vapor depositing metal through the opening of the resist film, and then the resist film is melted using a lift-off technique and the unnecessary metal vapor deposition film adhering to the resist film is removed. There is.

従って、従来の電極形成方法では、ゲート電極の幅はレ
ジスト膜の開口幅のみに依存している。
Therefore, in the conventional electrode forming method, the width of the gate electrode depends only on the opening width of the resist film.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

近年、半導体装置の高速化が図られ、QaAsFETや
HEMT等の新しい半導体装置が開発されてきている。
In recent years, the speed of semiconductor devices has been increased, and new semiconductor devices such as QaAsFETs and HEMTs have been developed.

かかる高速の半導体装置では、直流コンダクタンス(g
rn)、高周波特性、ノイズゲイン等の性能を向上させ
る為、短ゲート長1例えば1/2μm〜1/4μmの短
ゲート長の電極を実現する必要がある。
In such high-speed semiconductor devices, the DC conductance (g
rn), high frequency characteristics, noise gain, etc., it is necessary to realize an electrode with a short gate length, for example, 1/2 μm to 1/4 μm.

しかるに、前述した従来技術では、レジスト膜の開口幅
を0.7μm〜1.0μtn程度にすることは容易にで
きるが、これを0.7μfT1以下にすることは再現性
の点で困難である。このため、ゲート電極は0.7μm
程度の幅にするのが限界である。従って、電子ビームを
使った直接露光方式により短ゲート長の電極を形成しな
ければならないが、この方式は量産に向かず不経済であ
る。
However, in the conventional technique described above, although it is possible to easily reduce the opening width of the resist film to approximately 0.7 μm to 1.0 μtn, it is difficult to reduce the opening width to 0.7 μfT1 or less in terms of reproducibility. Therefore, the gate electrode is 0.7 μm thick.
The limit is to keep it within a certain range. Therefore, electrodes with short gate lengths must be formed by a direct exposure method using an electron beam, but this method is not suitable for mass production and is uneconomical.

本発明は上記事情に鑑みてなされたもので、その目的は
、短ゲート長の電極ををする半導体装置を容易にかつ再
現性、四産性良く形成できる技術を提供することにある
The present invention has been made in view of the above circumstances, and an object thereof is to provide a technology that can easily form a semiconductor device having an electrode with a short gate length with good reproducibility and high productivity.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的を達成する為、本発明の半導体装置の製造方法
では、レジスト膜の開口部側壁部にサイドウオールを形
成する工程を設&Jる。
In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes a step of forming a sidewall on the sidewall of the opening of the resist film.

〔作  用〕[For production]

レジスト膜の開口部側壁部にサイドウオールが形成され
ることにより、該サイドウオールにより開口幅が狭めら
れる。この狭められた開口部を通して電極材を蒸着して
ゲート電極を形成すると、短ゲート長の電極が得られる
By forming a sidewall on the side wall of the opening of the resist film, the width of the opening is narrowed by the sidewall. When a gate electrode is formed by depositing an electrode material through this narrowed opening, an electrode with a short gate length can be obtained.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を図面を参照して説明する。こ
の実施例は、本発明をGaAs  FETの製造に適用
したものである。
Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In this example, the present invention is applied to manufacturing a GaAs FET.

第1図は本実施例のゲート電極形成工程説明図である。FIG. 1 is an explanatory diagram of the gate electrode forming process of this embodiment.

以下、各工程を順に説明する。Each step will be explained in order below.

第1工程: ゲートを形成しようとするN−GaAS基板1の表面に
被エツチング材としての絶縁膜、本・実施例ではSiN
膜2を成長させる。このSiN膜2は、最終的にゲート
メタルリフトオフ用としてのスペーサの役割を果すもの
であり、他の絶縁膜例えばGaAsでも良い。また、絶
縁膜2を設けず、基板1自体を被エツチング材としても
よい。
First step: An insulating film as a material to be etched is formed on the surface of the N-GaAS substrate 1 on which a gate is to be formed.
Grow film 2. This SiN film 2 ultimately serves as a spacer for gate metal lift-off, and may be any other insulating film, such as GaAs. Alternatively, the insulating film 2 may not be provided, and the substrate 1 itself may be used as the material to be etched.

第2工程: SiN膜2の表面にフォトレジスト(P、R,)膜3を
塗布し、比較的安定な開口が得られる幅で、レジスト膜
3に窓開けを行なう0本実施例では、レジスト膜3の開
口幅を0.8μmとする。
Second step: A photoresist (P, R,) film 3 is applied to the surface of the SiN film 2, and a window is opened in the resist film 3 with a width that allows a relatively stable opening. The opening width of the membrane 3 is 0.8 μm.

第3工程: SiN膜2とエツチング特性(選択比)が異なる材質に
よる膜4を形成する。本実施例では、Sin!膜4を低
温プラズマCVDで成長させる。
Third step: A film 4 made of a material having different etching characteristics (selectivity) from the SiN film 2 is formed. In this example, Sin! Film 4 is grown by low temperature plasma CVD.

この様にSin!膜4を低温で形成すると、レジスト膜
3の開口部のエツジが形成しないため好都合である。
Like this, Sin! Forming the film 4 at a low temperature is advantageous because edges at the openings of the resist film 3 are not formed.

第4工程: Sin、膜4を異方性エツチングしてレジスト膜3の開
口部側壁部に形成されたSingのみを残し、これをサ
イドウオール4′とする。この結果、開口幅はサイドウ
オール4.′の厚さだけ狭められる。例えばサイドウオ
ール4′の幅を0.25μmに調整した場合、開口幅は
0.3μmとなる。
Fourth step: The Sine film 4 is anisotropically etched to leave only the Sing formed on the side wall of the opening of the resist film 3, and this is used as a sidewall 4'. As a result, the opening width is 4. ′ thickness. For example, if the width of the sidewall 4' is adjusted to 0.25 μm, the opening width will be 0.3 μm.

第5工程: 次に、上述の開口幅0.3μmの開口部を通してSiN
膜2の等方性エツチングを行なう、この際、エツジとし
て用いられるSin、のサイドウオール4′は、スペー
サとなるSiN膜2をエツチングするときに、選択比を
十分に大きくとることが可能であるため、サイドウオー
ル間の開口部(0,3μm)を拡げることなくエツチン
グを進めることができ、狭くなった形をそのまま維持す
ることができる。
Fifth step: Next, SiN is passed through the opening with an opening width of 0.3 μm.
When performing isotropic etching of the film 2, the Si sidewall 4' used as an edge can have a sufficiently large selectivity when etching the SiN film 2, which will serve as a spacer. Therefore, etching can proceed without widening the opening (0.3 μm) between the sidewalls, and the narrowed shape can be maintained as it is.

第6エ程ニ ショットキーメタルの蒸着を行なう。この蒸着により、
ショットキーメタルの蒸着膜5の一部はサイドウオール
4′間の開口部を通り、幅が0.3μmのゲート電極5
′が基板l上に形成される。
In the sixth step, Schottky metal is deposited. With this vapor deposition,
A part of the Schottky metal vapor deposition film 5 passes through the opening between the sidewalls 4' and forms a gate electrode 5 with a width of 0.3 μm.
' is formed on the substrate l.

蒸着膜5を形成するとき、斜め蒸着を行なえば、更に微
細な電極パターンを形成することができる。
When forming the vapor deposited film 5, if oblique vapor deposition is performed, a finer electrode pattern can be formed.

第7エ程: 最後にレジスト膜3を除去し、リフトオフにより不用の
メタル蒸着膜5を除去する。これは、例えばアセトンを
用いてSIN膜2側のレジスト膜3の露出した部分から
レジスト膜3を溶かして行なう。
Seventh step: Finally, the resist film 3 is removed, and the unnecessary metal deposited film 5 is removed by lift-off. This is done by dissolving the resist film 3 from the exposed portion of the resist film 3 on the SIN film 2 side using, for example, acetone.

以後、通常のFET工程を進めることにより短ゲートa
のゲート電極を有するショットキーF’ E′Fが得ら
れる。尚、GaAs  FETにって説明したが、HE
MTでも同様に短ゲート長の電極が得られる(第1図参
照)、また、上述した実施例では、0.3μm幅のゲー
ト電極を形成する方法について述べたが、このゲート幅
はレジストに形成する開口幅とサイドウオールの厚さと
を調整することにより任意の幅に設定できる。
After that, by proceeding with the normal FET process, the short gate a
A Schottky F'E'F is obtained having a gate electrode of . Although the explanation was given using GaAs FET, HE
In MT, an electrode with a short gate length can be obtained in the same way (see Figure 1).Also, in the above example, a method of forming a gate electrode with a width of 0.3 μm was described, but this gate width can be obtained by forming a gate electrode on a resist. An arbitrary width can be set by adjusting the opening width and the side wall thickness.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、サイドウオール技術、リフトオフ技術
、低温プラズマ技術等従来の技術を応用するだけで、再
現性、量産性の良い短ゲート長の電極を形成することが
できる。
According to the present invention, an electrode with a short gate length can be formed with good reproducibility and mass production by simply applying conventional techniques such as sidewall technology, lift-off technology, and low-temperature plasma technology.

工程説明図である。It is a process explanatory diagram.

Claims (1)

【特許請求の範囲】 1 被エッチング材の上に開口部を有するレジスト膜を
形成する工程と、 該レジスト膜の開口部側壁部に前記被エッチング材とエ
ッチング特性の異なる材料でサイドウォールを形成して
前記開口部を狭める工程と、該サイドウォールを形成し
たレジスト膜をマスクにして前記被エッチング材を等方
性エッチング工程と、 前記レジスト膜上から導電材を蒸着し前記サイドウォー
ルにより狭められた開口部を通して電極を形成する工程
と、 前記レジスト膜を除去して該レジスト膜上に付着してい
る不要の導電材蒸着膜を除去する工程とを有する半導体
装置の製造方法。 2 前記被エッチング材は、基板上に形成した絶縁膜あ
るいは基板自体であることを特徴とする特許請求の範囲
第1項記載の半導体装置の製造方法。
[Claims] 1. A step of forming a resist film having an opening on a material to be etched, and forming a sidewall on a side wall of the opening of the resist film using a material having etching characteristics different from that of the material to be etched. isotropically etching the material to be etched using the resist film on which the sidewalls are formed as a mask; and depositing a conductive material on the resist film to narrow the openings by the sidewalls. A method for manufacturing a semiconductor device, comprising: forming an electrode through an opening; and removing the resist film and removing an unnecessary conductive material deposited film adhering to the resist film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the material to be etched is an insulating film formed on a substrate or the substrate itself.
JP18566685A 1985-08-26 1985-08-26 Manufacture of semiconductor device Pending JPS6246577A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18566685A JPS6246577A (en) 1985-08-26 1985-08-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18566685A JPS6246577A (en) 1985-08-26 1985-08-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6246577A true JPS6246577A (en) 1987-02-28

Family

ID=16174742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18566685A Pending JPS6246577A (en) 1985-08-26 1985-08-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6246577A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6444068A (en) * 1987-08-11 1989-02-16 Nippon Mining Co Manufacture of semiconductor device
US6170147B1 (en) 1987-03-13 2001-01-09 Kabushiki Kaisha Toshiba Superconducting wire and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6170147B1 (en) 1987-03-13 2001-01-09 Kabushiki Kaisha Toshiba Superconducting wire and method of manufacturing the same
JPS6444068A (en) * 1987-08-11 1989-02-16 Nippon Mining Co Manufacture of semiconductor device

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