KR100261167B1 - Method for fabricating gate of semiconductor device - Google Patents
Method for fabricating gate of semiconductor device Download PDFInfo
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- KR100261167B1 KR100261167B1 KR1019980013271A KR19980013271A KR100261167B1 KR 100261167 B1 KR100261167 B1 KR 100261167B1 KR 1019980013271 A KR1019980013271 A KR 1019980013271A KR 19980013271 A KR19980013271 A KR 19980013271A KR 100261167 B1 KR100261167 B1 KR 100261167B1
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- Prior art keywords
- insulating film
- gate
- conductive layer
- sidewall
- semiconductor substrate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 239000003795 chemical substances by application Substances 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000011248 coating agent Substances 0.000 abstract 2
- 238000000576 coating method Methods 0.000 abstract 2
- 239000000463 material Substances 0.000 abstract 2
- 150000004767 nitrides Chemical class 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조공정에 관한 것으로, 특히 공정 마진을 향상시키는데 적당한 반도체 소자의 게이트 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a semiconductor device, and more particularly to a method for manufacturing a gate of a semiconductor device suitable for improving process margins.
이하, 첨부된 도면을 참고하여 종래 기술의 반도체 소자의 게이트 제조방법을 설명하면 다음과 같다.Hereinafter, a gate manufacturing method of a semiconductor device of the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래 기술의 반도체 소자의 게이트 제조방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a gate of a semiconductor device of the prior art.
도 1a에 도시한 바와 같이, 반도체 기판(11)상에 게이트 산화막(12)과 게이트 전극용 폴리 실리콘(13)을 차례로 형성한다.As shown in FIG. 1A, a gate oxide film 12 and a polysilicon 13 for a gate electrode are sequentially formed on the semiconductor substrate 11.
이어, 도 1b에 도시한 바와 같이, 상기 폴리 실리콘(13)상에 포토레지스트(14)를 도포한 후, 노광 및 현상공정으로 포토레지스트(14)를 패터닝하여 게이트 영역을 정의한다.Subsequently, as shown in FIG. 1B, after the photoresist 14 is applied onto the polysilicon 13, the photoresist 14 is patterned by an exposure and development process to define a gate region.
이어서, 도 1c에 도시한 바와 같이, 상기 패터닝된 포토레지스트(14)를 마스크로 이용하여 상기 폴리 실리콘(13)을 선택적으로 제거하여 게이트 전극(13a)을 형성한다.Subsequently, as shown in FIG. 1C, the polysilicon 13 is selectively removed using the patterned photoresist 14 as a mask to form a gate electrode 13a.
그리고 도 1d에 도시한 바와 같이, 상기 포토레지스트(14)를 제거하여 종래의 게이트 형성공정을 완료한다.As shown in FIG. 1D, the photoresist 14 is removed to complete the conventional gate forming process.
그러나 상기와 같은 종래 기술의 반도체 소자의 게이트 제조방법에 있어서 다음과 같은 문제점이 있었다.However, there is a problem in the gate manufacturing method of the semiconductor device of the prior art as described above.
첫째, 초소형 게이트 형성시(0.4㎛ 이하) 스텝의 차이에 따라 초점이 흐려지는 디포커싱에 의해 포커스를 맞추기가 어렵다.First, it is difficult to focus by defocusing when the micro gate is formed (0.4 μm or less) due to the difference in steps.
둘째, 게이트가 작아짐에 따라 마스크와 포토 에칭공정이 어려워지고 임계치수(CD ; Critical Dimension)의 스텝 차이를 측정하여 조절하기가 어렵다.Second, as the gate becomes smaller, the mask and the photo etching process become difficult, and it is difficult to measure and adjust the step difference of the critical dimension (CD).
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 극미세(Ultra-fine) 게이트를 형성하는데 있어 공정을 마진을 향상시킬 수 있도록 한 반도체 소자의 게이트 제조방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a gate of a semiconductor device, which can improve a margin in forming an ultra-fine gate.
도 1a 내지 도 1d는 종래 기술의 반도체 소자의 게이트 제조방법을 나타낸 공정단면도1A to 1D are cross-sectional views illustrating a method of manufacturing a gate of a semiconductor device of the related art.
도 2a 내지 도 2h는 본 발명에 의한 반도체 소자의 게이트 제조방법을 나타낸 공정단면도2A to 2H are cross-sectional views illustrating a method of manufacturing a gate of a semiconductor device according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
21 : 반도체 기판 22 : 게이트 절연막21 semiconductor substrate 22 gate insulating film
23 : 전도층 24 : 제 1 산화막23 conductive layer 24 first oxide film
25 : 제 1 포토레지스트 26 : 질화막 측벽25 first photoresist 26 nitride film sidewall
27 : 제 2 포토레지스트 28 : 제 2 산화막 측벽27: second photoresist 28: second oxide film sidewall
29 : 제 3 포토레지스트29: third photoresist
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 게이트 제조방법은 반도체 기판상에 게이트 절연막 및 전도층을 차례로 형성하는 단계와, 상기 전도층상에 일정한 간격을 갖는 복수개의 제 1 절연막 패턴을 형성하는 단계와, 상기 제 1 절연막 패턴의 양측면에 제 2 절연막 측벽을 형성하는 단계와, 상기 제 1 절연막 패턴 및 제 2 절연막 측벽을 마스크로 이용하여 상기 전도층을 선택적으로 제거하여 전도층 패턴을 형성하는 단계와, 상기 반도체 기판의 전면에 제 1 감광제를 도포한 후 상기 제 1 절연막 패턴의 표면을 노출시키는 단계와, 상기 제 1 절연막 패턴을 제거하고 상기 제 2 절연막 측벽의 일측면에 제 3 절연막 측벽을 형성하는 단계와, 상기 반도체 기판의 전면에 제 2 감광제를 도포한 후 상기 제 3 절연막 측벽의 표면을 노출시키는 단계와, 그리고 상기 제 3 절연막 측벽을 제거하고 상기 제 2 감광제 및 제 2 절연막 측벽을 마스크로 이용하여 상기 전도층 패턴을 선택적으로 제거하여 복수개의 게이트 전극을 형성하는 단계를 포함하여 형성함을 특징으로 한다.In order to achieve the above object, a method of manufacturing a gate of a semiconductor device according to the present invention includes sequentially forming a gate insulating film and a conductive layer on a semiconductor substrate, and forming a plurality of first insulating film patterns having a predetermined interval on the conductive layer. Forming a second insulating film sidewall on both sides of the first insulating film pattern, and selectively removing the conductive layer using the first insulating film pattern and the second insulating film sidewall as a mask to form a conductive layer pattern. Forming a surface, applying a first photosensitive agent to the entire surface of the semiconductor substrate, exposing a surface of the first insulating film pattern, removing the first insulating film pattern, and removing a third insulating film on one side of the sidewall of the second insulating film. Forming an insulating film sidewall, and applying a second photosensitive agent to the entire surface of the semiconductor substrate and then exposing the surface of the third insulating film sidewall. Forming a plurality of gate electrodes by removing the sidewalls of the third insulating film and selectively removing the conductive layer pattern using the second photoresist and the second insulating film sidewalls as masks. It is characterized by.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 게이트 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a gate of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2h는 본 발명에 의한 반도체 소자의 게이트 제조방법을 나타낸 공정단면도이다.2A to 2H are cross-sectional views illustrating a method of manufacturing a gate of a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 반도체 기판(21)을 활성영역과 필드영역으로 정의한 후, 필드영역에 소자 격리막(도면에 도시하지 않음)을 형성하고, 상기 반도체 기판(21)의 활성영역에 채널이온을 주입한다.As shown in FIG. 2A, after the semiconductor substrate 21 is defined as an active region and a field region, an element isolation film (not shown) is formed in the field region, and a channel is formed in the active region of the semiconductor substrate 21. Implant ions.
이어, 상기 반도체 기판(21)을 열산화하여 상기 반도체 기판(21)의 표면에 게이트 절연막(22)을 형성하고, 상기 게이트 절연막(22)상에 게이트 전극용 전도층(예를 들면 폴리 실리콘 등)(23)을 증착한다.Subsequently, the semiconductor substrate 21 is thermally oxidized to form a gate insulating film 22 on the surface of the semiconductor substrate 21, and a conductive layer for a gate electrode (for example, polysilicon or the like) is formed on the gate insulating film 22. 23).
그리고 상기 전도층(23)상에 제 1 산화막(24)을 형성한다.A first oxide film 24 is formed on the conductive layer 23.
도 2b에 도시한 바와 같이, 상기 제 1 산화막(24)상에 제 1 포토레지스트(25)를 도포한 후, 노광 및 현상공정으로 제 1 포토레지스트(25)를 패터닝한다.As shown in FIG. 2B, the first photoresist 25 is coated on the first oxide film 24, and then the first photoresist 25 is patterned by an exposure and development process.
이어, 상기 패터닝된 제 1 포토레지스트(25)를 마스크로 이용하여 상기 제 1 산화막(24)을 선택적으로 제거하여 복수개의 제 1 산화막 패턴(24a)을 형성한다.Subsequently, the first oxide layer 24 is selectively removed using the patterned first photoresist 25 as a mask to form a plurality of first oxide layer patterns 24a.
도 2c에 도시한 바와 같이, 상기 제 1 포토레지스트(25)를 제거하고, 상기 제 1 산화막 패턴(24a)을 포함한 반도체 기판(21)의 전면에 질화막을 증착한 후, 전면에 에치백 공정을 실시하여 상기 제 1 산화막 패턴(24a)의 양측면에 질화막 측벽(26)을 형성한다.As shown in FIG. 2C, the first photoresist 25 is removed, a nitride film is deposited on the entire surface of the semiconductor substrate 21 including the first oxide film pattern 24a, and then an etch back process is performed on the entire surface. The nitride film sidewalls 26 are formed on both sides of the first oxide film pattern 24a.
도 2d에 도시한 바와 같이, 상기 질화막 측벽(26) 및 제 1 산화막 패턴(24a)을 마스크로 이용하여 상기 게이트 절연막(22)의 표면이 노출되도록 상기 전도층(23)을 선택적으로 제거하여 전도층 패턴(23a)을 형성한다.As shown in FIG. 2D, the conductive layer 23 is selectively removed so that the surface of the gate insulating film 22 is exposed using the nitride film sidewall 26 and the first oxide film pattern 24a as a mask. The layer pattern 23a is formed.
이어, 상기 반도체 기판(21)의 전면에 제 2 포토레지스트(27)를 도포한 후, 상기 제 2 포토레지스트(27)의 전면에 노광빔(Exposure Beam)을 주사 및 현상공정을 실시하여 상기 제 1 산화막 패턴(24a)의 표면을 노출시킨다.Subsequently, the second photoresist 27 is coated on the entire surface of the semiconductor substrate 21, and then an exposure beam is scanned and developed on the entire surface of the second photoresist 27. 1 The surface of the oxide film pattern 24a is exposed.
도 2e에 도시한 바와 같이, 상기 제 1 산화막 패턴(24a)을 습식식각으로 제거하고, 상기 반도체 기판(21)의 전면에 제 2 산화막을 증착한 후, 전면에 에치백 공정을 실시하여 상기 질화막 측벽(26)의 양측면에 제 2 산화막 측벽(28)을 형성한다.As shown in FIG. 2E, the first oxide layer pattern 24a is removed by wet etching, a second oxide layer is deposited on the entire surface of the semiconductor substrate 21, and then an etch back process is performed on the entire surface of the nitride layer. Second oxide film sidewalls 28 are formed on both side surfaces of the sidewalls 26.
여기서 상기 제 2 산화막은 200℃미만의 온도로 증착된 PECVD(Plasma Enhanced Chemical Vapor Deposition) 산화막이다.Here, the second oxide film is a PECVD (Plasma Enhanced Chemical Vapor Deposition) oxide film deposited at a temperature of less than 200 ℃.
도 2f에 도시한 바와 같이, 상기 반도체 기판(21)의 전면에 제 3 포토레지스트(29)를 도포한 후, 상기 제 3 포토레지스트(29)의 전면에 노광빔의 주사 및 현상공정을 실시하여 상기 제 2 산화막 측벽(28)의 표면을 노출시킨다.As shown in FIG. 2F, after the third photoresist 29 is coated on the entire surface of the semiconductor substrate 21, an exposure beam is scanned and developed on the entire surface of the third photoresist 29. The surface of the second oxide film sidewall 28 is exposed.
도 2g에 도시한 바와 같이, 상기 제 2 산화막 측벽(28)을 습식식각으로 제거하고, 상기 제 3 포토레지스트(29) 및 질화막 측벽(26)을 마스크로 이용하여 상기 전도층 패턴(23a)을 선택적으로 제거하여 복수개의 게이트 전극(23b)을 형성한다.As shown in FIG. 2G, the second oxide film sidewall 28 is removed by wet etching, and the conductive layer pattern 23a is formed using the third photoresist 29 and the nitride film sidewall 26 as a mask. It is selectively removed to form a plurality of gate electrodes 23b.
도 2h에 도시한 바와 같이, 상기 제 3 포토레지스트(29) 및 제 2 포토레지스트(27) 그리고 질화막 측벽(26)을 제거함으로써 본 발명에 의한 게이트 형성공정을 완료한다.As shown in FIG. 2H, the gate forming process according to the present invention is completed by removing the third photoresist 29, the second photoresist 27, and the nitride film sidewall 26.
여기서 상기 질화막 측벽(26)은 핫(Hot) 인산을 이용하여 제거한다.In this case, the nitride film sidewall 26 is removed using hot phosphoric acid.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 게이트 제조방법에 있어서 다음과 같은 효과가 있다.As described above, the gate manufacturing method of the semiconductor device according to the present invention has the following effects.
첫째, 셀프얼라인 구조와 측벽의 두께를 조절함으로써 게이트의 임계 치수 조절이 가능하므로 극미세 게이트(0.4㎛ 이하)를 용이하게 형성할 수 있다.First, since the critical dimension of the gate can be adjusted by adjusting the thickness of the self-aligned structure and the sidewalls, an extremely fine gate (0.4 μm or less) can be easily formed.
둘째, 기판에 균일성 및 재현성이 우수한 게이트를 형성할 수 있어 공정마진을 향상시킬 수 있다.Second, it is possible to form a gate having excellent uniformity and reproducibility on the substrate can improve the process margin.
Claims (4)
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| KR1019980013271A KR100261167B1 (en) | 1998-04-14 | 1998-04-14 | Method for fabricating gate of semiconductor device |
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| KR1019980013271A KR100261167B1 (en) | 1998-04-14 | 1998-04-14 | Method for fabricating gate of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7968467B2 (en) | 2007-10-26 | 2011-06-28 | Hynix Semiconductor Inc. | Method for forming patterns in semiconductor memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7968467B2 (en) | 2007-10-26 | 2011-06-28 | Hynix Semiconductor Inc. | Method for forming patterns in semiconductor memory device |
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