KR100370159B1 - Method for Fabricating Semiconductor Device - Google Patents
Method for Fabricating Semiconductor Device Download PDFInfo
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- KR100370159B1 KR100370159B1 KR10-2000-0059829A KR20000059829A KR100370159B1 KR 100370159 B1 KR100370159 B1 KR 100370159B1 KR 20000059829 A KR20000059829 A KR 20000059829A KR 100370159 B1 KR100370159 B1 KR 100370159B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Abstract
본 발명은 공정 마진 및 집적도를 향상시키기 위한 반도체 소자의 제조방법에 관한 것으로서, 반도체층상에 도전 물질을 증착하고 이를 선택적으로 제거하여 도전막을 형성하는 단계와, 상기 반도체 기판상에 제 1 절연막, 스탑퍼 질화막, 제 2 절연막을 차례로 형성하는 단계와, 상기 스탑퍼 질화막에 폴리머가 많이 발생되는 조건을 갖는 플라즈마 건식각 장비를 이용하여 상기 제 2 절연막과 스탑퍼 질화막과 제 1 절연막을 식각하여 콘택홀을 형성하는 단계를 포함하여 형성한다.The present invention relates to a method of manufacturing a semiconductor device for improving process margins and integration degree, comprising depositing a conductive material on a semiconductor layer and selectively removing the conductive material to form a conductive film, and forming a first insulating film and a stop on the semiconductor substrate. Forming a per nitride film and a second insulating film in sequence, and etching the second insulating film, the stopper nitride film, and the first insulating film by using a plasma dry etching apparatus having a condition in which a large amount of polymer is generated in the stopper nitride film. Forming comprising the step of forming.
Description
본 발명은 반도체 소자에 관한 것으로 특히, 공정 마진을 확보하고 집적도를 향상시키기 위한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for securing process margins and improving integration.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1은 종래 반도체 소자의 단면도이고, 도 2는 종래 반도체 소자의 평면 SEM 사진이다.1 is a cross-sectional view of a conventional semiconductor device, Figure 2 is a planar SEM photograph of a conventional semiconductor device.
종래의 반도체 소자는 도 1에 도시된 바와 같이, 반도체층(11)상의 일영역에 형성되는 도전막(12)과, 상기 도전막(12)을 포함한 반도체층(11)의 전면에 형성되는 TEOS막(13)과, 상기 도전막(12)의 표면이 노출되도록 상기 TEOS막(13)의 일영역을 제거하여 형성되는 콘택홀(15)로 구성된다.As shown in FIG. 1, the conventional semiconductor device includes a conductive film 12 formed in one region on the semiconductor layer 11 and a TEOS formed on the entire surface of the semiconductor layer 11 including the conductive film 12. The film 13 and the contact hole 15 formed by removing one region of the TEOS film 13 so that the surface of the conductive film 12 is exposed.
그리고, 도면에서 A는 콘택홀(15)을 형성하기 위하여 패터닝된 포토레지스트(14)의 홀 사이즈이고, B는 콘택홀(15) 깊이이고, C는 콘택홀(15)과 그 하부 도전막(12)의 얼라인(Align) 여유를 나타낸다.In the drawing, A is the hole size of the photoresist 14 patterned to form the contact hole 15, B is the depth of the contact hole 15, C is the contact hole 15 and the lower conductive film ( The alignment margin of 12) is shown.
그리고, 도 2의 사진에서 가운데 짙게 나타난 영역이 상기 콘택홀(15)에 의하여 노출되는 도전막(12)이고, 가장자리에 밝게 나타난 부분의 콘택홀(15) 내부의 상기 TEOS막(13)의 측면 부분이다.In the photograph of FIG. 2, a thicker area is a conductive film 12 exposed by the contact hole 15, and a side surface of the TEOS film 13 inside the contact hole 15 in a portion that appears bright at the edge. Part.
상기와 같이 구성되는 종래 반도체 소자의 제조방법은 우선, 반도체층(11)상에 텅스텐(W)과 같은 도전성 물질을 증착한다.In the conventional method for manufacturing a semiconductor device configured as described above, first, a conductive material such as tungsten (W) is deposited on the semiconductor layer 11.
그리고, 포토 및 식각 공정으로 상기 반도체층(11)상의 일영역에만 남도록 상기 도전성 물질을 선택적으로 제거하여 도전막(12)을 형성한다.In addition, the conductive material 12 is selectively removed to form only the region on the semiconductor layer 11 by photo and etching, thereby forming the conductive layer 12.
이어, 전면에 2∼5㎛의 두께로 TEOS(Tetra Ethyl Ortho Silicate)막(13)을 증착하고, 상기 TEOS막(13)상에 0.7∼0.9㎛의 두께로 포토레지스트(14)를 도포한다.Next, a TEOS (Tetra Ethyl Ortho Silicate) film 13 is deposited on the entire surface, and a photoresist 14 is applied on the TEOS film 13 at a thickness of 0.7 to 0.9 μm.
그리고, 노광 및 현상 공정으로 상기 도전막(12) 상부의 상기 TEOS막(13)의 일영역이 노출되도록 상기 포토레지스트(14)를 패터닝한다.The photoresist 14 is patterned to expose one region of the TEOS film 13 on the conductive film 12 by an exposure and development process.
이때, 상기 패터닝된 포토레지스트(14)의 홀 사이즈(A)는 0.25∼0.27㎛이다.At this time, the hole size A of the patterned photoresist 14 is 0.25 ~ 0.27㎛.
이어, 패터닝된 포토레지스트(14)를 마스크로 이용하여 상기 도전막(12)이 노출되도록 상기 TEOS막(13)을 선택적으로 제거하여 콘택홀(15)을 형성한다.Subsequently, the contact hole 15 is formed by selectively removing the TEOS layer 13 so that the conductive layer 12 is exposed using the patterned photoresist 14 as a mask.
상기한 종래 반도체 소자는 도 1에 도시된 바와 같이, 콘택홀과 그 하부의 도전막은 C 길이만큼 얼라인(Align) 여유가 있다.In the conventional semiconductor device, as shown in FIG. 1, the contact hole and the conductive layer below the substrate have an alignment margin by C length.
그러나, 상기와 같은 종래의 반도체 소자의 제조방법은 다음과 같은 문제점이 있다.However, the conventional method of manufacturing a semiconductor device as described above has the following problems.
첫째, 콘택홀이 C라는 얼라인 여유를 벗어나면 차후에 콘택홀을 매립하여 형성되는 플러그와 도전막이 서로 연결되지 않는 불량이 발생된다.First, when the contact hole deviates from the alignment margin of C, a defect occurs in which the plug formed by filling the contact hole later and the conductive film are not connected to each other.
둘째, 집적도가 증가할수록 얼라인 여유는 감소하므로 집적도를 향상시킬 수 없다.Second, as the degree of integration increases, the alignment margin decreases, and thus the degree of integration cannot be improved.
셋째, 상기 콘택홀과 도전막의 얼라인 마진이 작기 때문에 불량 발생률이 높고 공정이 상당히 까다롭다Third, since the alignment margin of the contact hole and the conductive film is small, the defect occurrence rate is high and the process is quite difficult.
넷째, 포토레지스트의 홀 사이즈에 따라 콘택홀의 사이즈가 결정되므로 미세한 콘택홀을 형성하기 위해서는 그 만큼 미세한 포토레지스트 패턴이 요구되므로 집적도를 향상시키기 어렵다.Fourth, since the size of the contact hole is determined according to the hole size of the photoresist, it is difficult to improve the degree of integration because a fine photoresist pattern is required to form a fine contact hole.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 단일 마스크를 이용하여 초미세 콘택홀을 형성하여 공정 마진을 확보하고 소자의 집적도를 향상시키는데 적합한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device suitable for securing process margins and improving device integration by forming an ultra-fine contact hole using a single mask. .
도 1은 종래 반도체 소자의 단면도1 is a cross-sectional view of a conventional semiconductor device
도 2는 종래 반도체 소자의 평면 SEM 사진2 is a planar SEM photograph of a conventional semiconductor device
도 3은 본 발명의 실시예에 따른 반도체 소자의 단면도3 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
도 4는 본 발명의 실시예에 따른 반도체 소자의 평면 SEM 사진4 is a planar SEM photograph of a semiconductor device according to an embodiment of the present invention.
도 5는 본 발명의 실시예에 따른 반도체 소자의 단면 SEM 사진5 is a cross-sectional SEM photograph of a semiconductor device according to an embodiment of the present invention.
도면의 주요 부분에 대한 부호설명Explanation of Signs of Major Parts of Drawings
31 : 반도체층 32 : 도전막31 semiconductor layer 32 conductive film
33 : 제 1 TEOS막 34 : 질화막33: first TEOS film 34: nitride film
35 : 제 2 TEOS막 36 : 포토레지스트35 second TEOS film 36 photoresist
37 : 콘택홀37: contact hole
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 반도체층상에 도전 물질을 증착하고 이를 선택적으로 제거하여 도전막을 형성하는 단계와, 상기 반도체 기판상에 제 1 절연막, 스탑퍼 질화막, 제 2 절연막을 차례로 형성하는 단계와, 상기 스탑퍼 질화막에 폴리머가 많이 발생되는 조건을 갖는 플라즈마 건식각 장비를 이용하여 상기 제 2 절연막과 스탑퍼 질화막과 제 1 절연막을 식각하여 콘택홀을 형성하는 단계를 포함하여 형성함을 특징으로 한다.Method of manufacturing a semiconductor device of the present invention for achieving the above object is to form a conductive film by depositing a conductive material on the semiconductor layer and selectively removing it, a first insulating film, a stopper nitride film, Forming a contact hole by etching the second insulating film, the stopper nitride film, and the first insulating film by using a plasma dry etching apparatus having a step of sequentially forming a second insulating film and a condition in which a large amount of polymer is generated in the stopper nitride film. Characterized in that it comprises a step.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 3은 본 발명의 실시예에 따른 반도체 소자의 단면도이고, 도 4는 본 발명의 실시예에 따른 반도체 소자의 평면 SEM 사진이고, 도 5는 본 발명의 실시예에따른 반도체 소자의 단면 SEM 사진이다.3 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 4 is a planar SEM photograph of a semiconductor device according to an embodiment of the present invention, and FIG. 5 is a cross-sectional SEM photograph of a semiconductor device according to an embodiment of the present invention. to be.
본 발명에 따른 반도체 소자는 도 3에 도시된 바와 같이, 반도체층(31)상의 일영역에 형성되는 도전막(32)과, 상기 도전막(32)을 포함한 전면에 형성되는 제 1 TEOS막(33)과, 상기 제 1 TEOS막(33)의 표면상에 형성되는 질화막(34)과, 상기 질화막(34)상에 소정 두께로 형성되는 제 2 TEOS막(35)과, 상기 제 2 TEOS막(35)과 질화막(34)과 제 1 TEOS막(33)을 제거하여 상기 도전막(32)이 노출되도록 형성되며 상기 제 2 TEOS막(35)에서는 제 1 크기의 홀 사이즈를 가지며 상기 질화막(34)과 상기 제 1 TEOS막(33)에서는 상기 제 1 크기보다 작은 제 2 크기의 홀 사이즈를 갖는 콘택홀(37)로 구성된다.As shown in FIG. 3, the semiconductor device according to the present invention includes a conductive film 32 formed in one region on the semiconductor layer 31 and a first TEOS film formed on the entire surface including the conductive film 32. 33), a nitride film 34 formed on the surface of the first TEOS film 33, a second TEOS film 35 formed on the nitride film 34 with a predetermined thickness, and the second TEOS film And the nitride film 34 and the first TEOS film 33 are removed to expose the conductive film 32. The second TEOS film 35 has a hole size of a first size and the nitride film ( 34) and the first TEOS film 33 are formed of a contact hole 37 having a hole size of a second size smaller than the first size.
그리고, 상기 제 1 TEOS막(33)과 질화막(34)에 형성되는 콘택홀(37)의 홀 사이즈는 작고 상기 제 2 TEOS막(35)에 형성되는 콘택홀(37)의 홀 사이즈는 크기 때문에 그 평면 사진은 도 4에 나타난 바와 같이, 가운데 가장 짙게 나타난 도전막(32)과, 그 다음으로 짙게 나타난 영역인 콘택홀 내부의 질화막(34)과, 가장 밝게 나타난 영역인 콘택홀(37) 내부의 상기 제 2 TEOS막(35)의 측면 영역으로 나타난다.Since the hole size of the contact hole 37 formed in the first TEOS film 33 and the nitride film 34 is small, the hole size of the contact hole 37 formed in the second TEOS film 35 is large. As shown in FIG. 4, the planar photo shows a conductive film 32 that is darkest in the middle, a nitride film 34 inside the contact hole, which is the next darkest region, and a contact hole 37, which is the brightest region. It is shown in the side region of the second TEOS film 35 of.
그리고, 도 5 는 본 발명의 실시예에 따른 반도체 소자를 직접 촬영한 단면으로, 도전막(32)과 접하는 콘택홀 하부의 사이즈가 상부보다 월등히 작음을 나타낸다.5 is a cross-sectional view directly photographing a semiconductor device according to an exemplary embodiment of the present invention, and shows that the size of the lower portion of the contact hole in contact with the conductive layer 32 is much smaller than the upper portion.
상기와 같이 구성되는 본 발명에 따른 반도체 소자의 제조방법은 반도체층(31)상에 텅스텐(W) 등의 금속막을 증착한 후, 포토 및 식각 공정으로 상기 반도체층(31)상의 일영역에 남도록 상기 금속막을 선택적으로 제거하여 도전막(32)을 형성한다.In the method of manufacturing a semiconductor device according to the present invention configured as described above, a metal film such as tungsten (W) is deposited on the semiconductor layer 31, and then remains in one region on the semiconductor layer 31 by photo and etching processes. The metal film is selectively removed to form a conductive film 32.
그리고, 전면에 1.4∼1.6㎛ 두께로 제 1 TEOS막(33)을 증착하고, 상기 제 1 TEOS막(33)의 표면상에 0.19∼0.21㎛ 두께로 질화막(34)을 증착한다.Then, the first TEOS film 33 is deposited on the entire surface with a thickness of 1.4 to 1.6 mu m, and the nitride film 34 is deposited on the surface of the first TEOS film 33 with a thickness of 0.19 to 0.21 mu m.
그리고, 상기 질화막(34)상에 0.9∼1.1㎛의 제 2 TEOS막(35)을 증착한다.Then, a second TEOS film 35 of 0.9 to 1.1 mu m is deposited on the nitride film 34.
이어, 전면에 포토레지스트(36)를 도포하고 노광 및 현상 공정으로 상기 도전막(32) 상부의 상기 제 2 TEOS막(35)의 일영역이 노출되도록 상기 포토레지스트(36)를 패터닝한다.Subsequently, the photoresist 36 is coated on the entire surface, and the photoresist 36 is patterned to expose one region of the second TEOS layer 35 on the conductive layer 32 by an exposure and development process.
이때, 상기 포토레지스트(36)의 두께는 0.7∼0.9㎛이고, 상기 패터닝된 포토레지스트(36)의 홀의 크기는 0.25∼0.27㎛이다.At this time, the thickness of the photoresist 36 is 0.7 ~ 0.9㎛, the size of the hole of the patterned photoresist 36 is 0.25 ~ 0.27㎛.
그리고, 상기 패터닝된 포토레지스트(36)를 마스크로 이용하여 상기 제 2 TEOS막(35)과 질화막(34)과 제 1 TOES막(33)을 차례로 제거하여 콘택홀(37)을 형성한다.In addition, the contact hole 37 is formed by sequentially removing the second TEOS layer 35, the nitride layer 34, and the first TOES layer 33 using the patterned photoresist 36 as a mask.
여기서 상기 공정은 A-IEM 플라즈마 건식각기(Plasma Dry Etcher)를 이용하여 실시한다.In this case, the process is performed by using an A-IEM plasma dry etcher.
그리고, 상기 식각 공정은 15∼30sccm의 C5F8과, 20∼40sccm의 CH2F2와, 25∼40sccm의 O2와, 200∼400sccm의 Ar 가스 분위기에서 소오스 전력을 1000∼2000W, 바이어스 전력을 1000∼1800W를 인가하며, 5∼50Tm의 압력하에서 실시한다.In the etching process, the source power is 1000 to 2000 W, biased at 15 to 30 sccm C 5 F 8 , 20 to 40 sccm CH 2 F 2 , 25 to 40 sccm O 2 , and 200 to 400 sccm Ar gas atmosphere. The power is applied from 1000 to 1800 W, and is carried out under a pressure of 5 to 50 Tm.
이와 같은 조건은 상기 질화막(34)에 폴리머(Polymer)가 많이 발생되는 조건으로, 이러한 조건하에서 식각 공정을 실시하면 상기 질화막(24)에 발생되는 폴리머에 의하여 콘택홀의 사이즈가 감소되어 상기 질화막(24)의 하부에는 미세 콘택홀이 형성되게 된다.Such a condition is a condition in which a large amount of polymer is generated in the nitride film 34. When the etching process is performed under such conditions, the size of the contact hole is reduced by the polymer generated in the nitride film 24, and thus the nitride film 24 is formed. The bottom of the) is to form a fine contact hole.
즉, 상기 질화막(24)은 홀의 중심부분이 먼저 식각이 진행되며 상기 질화막(24)에서 발생되는 폴리머에 의하여 상기 홀의 크기가 증가되지 않으므로 하부의 제 1 TEOS막(33)에 미세한 콘택홀을 형성할 수 있다.That is, in the nitride film 24, the center portion of the hole is etched first, and the size of the hole is not increased by the polymer generated in the nitride film 24, thereby forming a fine contact hole in the lower first TEOS film 33. can do.
또한, 상기 질화막(34)의 증착 위치에 따라서 미세 콘택홀의 길이가 달라지므로 상기 질화막(34)의 증착 위치는 미세 콘택홀이 필요한 부분에 따라 달라져야 하며 그 두께와 재질 역시 다르게 증착하여야 한다.In addition, since the length of the fine contact hole varies depending on the deposition position of the nitride film 34, the deposition position of the nitride film 34 should be varied depending on the portion of the fine contact hole, and the thickness and material of the nitride film 34 should be deposited differently.
상기와 같은 본 발명의 반도체 소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing a semiconductor device of the present invention as described above has the following effects.
첫째, 하부의 콘택홀을 충분히 미세하게 형성할 수 있으므로 도전막과의 얼라인 마진을 확보할 수 있어 반도체 소자의 불량을 줄일 수 있다.First, since the lower contact hole can be formed sufficiently finely, an alignment margin with the conductive film can be secured, thereby reducing defects of the semiconductor device.
둘째, 하나의 포토 마스크만을 사용하여 2회의 마스크 사용한 것과 같은 효과를 얻을 수 있으므로 공정이 간단하고 공정 마진이 향상된다.Second, since the same effect as using two masks can be obtained using only one photo mask, the process is simple and the process margin is improved.
셋째, 미세한 패턴의 포토 마스크를 사용하지 않고서도 초미세 콘택홀을 형성할 수 있으므로 반도체 소자의 집적도를 향상시킬 수 있다.Third, since the ultra-fine contact holes can be formed without using the photo mask of the fine pattern, the integration degree of the semiconductor device can be improved.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08186111A (en) * | 1994-12-28 | 1996-07-16 | Sony Corp | Forming method for connecting hole |
| KR19980057105A (en) * | 1996-12-30 | 1998-09-25 | 김영환 | Contact hole formation method of semiconductor device |
| KR19990059092A (en) * | 1997-12-30 | 1999-07-26 | 김영환 | Contact hole formation method of semiconductor device |
| KR20000019607A (en) * | 1998-09-14 | 2000-04-15 | 김영환 | Method for forming multi-layered line of semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08186111A (en) * | 1994-12-28 | 1996-07-16 | Sony Corp | Forming method for connecting hole |
| KR19980057105A (en) * | 1996-12-30 | 1998-09-25 | 김영환 | Contact hole formation method of semiconductor device |
| KR19990059092A (en) * | 1997-12-30 | 1999-07-26 | 김영환 | Contact hole formation method of semiconductor device |
| KR20000019607A (en) * | 1998-09-14 | 2000-04-15 | 김영환 | Method for forming multi-layered line of semiconductor device |
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