KR20000019607A - Method for forming multi-layered line of semiconductor device - Google Patents
Method for forming multi-layered line of semiconductor device Download PDFInfo
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- KR20000019607A KR20000019607A KR1019980037794A KR19980037794A KR20000019607A KR 20000019607 A KR20000019607 A KR 20000019607A KR 1019980037794 A KR1019980037794 A KR 1019980037794A KR 19980037794 A KR19980037794 A KR 19980037794A KR 20000019607 A KR20000019607 A KR 20000019607A
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 58
- 239000011229 interlayer Substances 0.000 claims abstract description 44
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000009413 insulation Methods 0.000 claims abstract description 8
- 230000035945 sensitivity Effects 0.000 claims description 6
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 abstract 1
- 230000036211 photosensitivity Effects 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히, 다층의 금속 배선을 자기 정합적으로 용이하게 형성할 수 있는 반도체장치의 다층배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a multilayer wiring of a semiconductor device capable of easily forming a multilayer metal wiring in a self-aligned manner.
일반적으로, 반도체장치의 집적도가 증가됨에 따라 셀의 크기가 감소되며, 이에 의해, 금속배선의 폭이 미세화 및 다층화된다. 금속 배선의 다층화는 소자의 집적도를 향상시킬 수 있으나 공정이 복잡해질 뿐만 아니라 평탄도가 저하되는 문제점이 있었다.In general, as the degree of integration of a semiconductor device is increased, the size of the cell is reduced, whereby the width of the metal wiring is miniaturized and multilayered. Multilayering of the metal wires can improve the degree of integration of the device, but there is a problem that the flatness is reduced as well as the complexity of the process.
그러므로, 공정이 간단하고 평탄도를 향상시키면서 다층 배선을 형성할 수 있는 '듀얼 다마스컨스(dual damascene)' 공정이 개발되었다. 듀얼 다마스컨스 공정은 하부의 배선은 노출시키는 접속 홀과 상부의 배선을 형성하기 위한 트렌치를 자기 정합적으로 형성하여 트렌치 내에 상부 배선 형성시 접속 홀을 통해 하부 배선과 연결되어 다층 배선을 형성한다.Therefore, a 'dual damascene' process has been developed that can form a multilayer wiring while simplifying the process and improving flatness. In the dual damascene process, a junction hole for exposing the lower wiring and a trench for forming the upper wiring are self-aligned to form a multi-layered wiring by being connected with the lower wiring through the connection hole when forming the upper wiring in the trench.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 다층배선 형성방법을 도시하는 공정도이다.1A to 1D are process diagrams showing a method for forming a multilayer wiring of a semiconductor device according to the prior art.
도 1a를 참조하면, 기판(11) 상의 소정 부분에 제 1 배선(13)을 긴띠 형상(도시되지 않음)으로 형성한다. 상기에서 기판(11)은 반도체기판 상에 절연막이 형성된 것이다. 기판(11) 상에 제 1 배선(13)을 덮도록 제 1 층간절연층(15), 식각정지층(17) 및 제 2 층간절연층(19)를 순차적으로 형성한다. 상기에서 제 1 및 제 2 층간절연층(15)(19)을 산화실리콘을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착하여 형성하고, 식각정지층(17)을 제 1 및 제 2 층간절연층(15)(19)을 형성하는 산화실리콘과 식각 선택비가 다른 질화실리콘을 CVD 방법으로 증착하여 형성한다. 또한, 제 1 층간절연층(15)을 식각정지층(17)을 증착하기 전에 화학-기계적연마(Chemical Mechanical Polishing : 이하, CMP라 칭함) 방법으로 에치백(etchback)하여 표면을 평탄화한다.Referring to FIG. 1A, the first wiring 13 is formed in a long band shape (not shown) on a predetermined portion on the substrate 11. The substrate 11 is an insulating film formed on a semiconductor substrate. The first interlayer insulating layer 15, the etch stop layer 17, and the second interlayer insulating layer 19 are sequentially formed on the substrate 11 to cover the first wiring 13. The first and second interlayer insulating layers 15 and 19 are formed by depositing silicon oxide by chemical vapor deposition (hereinafter, referred to as CVD), and the etch stop layer 17 is formed by the first and second interlayer insulating layers 15 and 19. And silicon nitride having a different etching selectivity from silicon oxide forming the second interlayer insulating layers 15 and 19 by CVD. In addition, the surface of the first interlayer insulating layer 15 is etched back by chemical mechanical polishing (hereinafter referred to as CMP) method before depositing the etch stop layer 17.
도 1b를 참조하면, 제 2 층간절연층(19) 상에 제 1 감광막(21)을 증착한 후 노광 및 현상하여 제 2 층간절연층(19)의 제 1 배선(13)과 대응하는 소정 부분을 노출시킨다.Referring to FIG. 1B, a predetermined portion corresponding to the first wiring 13 of the second interlayer insulating layer 19 is formed by depositing the first photosensitive film 21 on the second interlayer insulating layer 19, and then exposing and developing the first photosensitive film 21. Expose
제 1 감광막(21)을 마스크로 사용하여 제 2 층간절연층(19) 및 식각정지층(17)을 이방성 식각하여 제 1 층간절연층(15)을 노출시키는 제 1 접촉홀(23)을 형성한다.The first contact hole 23 exposing the first interlayer insulating layer 15 is formed by anisotropically etching the second interlayer insulating layer 19 and the etch stop layer 17 using the first photoresist film 21 as a mask. do.
도 1c를 참조하면, 제 1 감광막(21)을 제거한다. 그리고, 제 2 층간절연층(19) 상에 제 1 접촉홀(23)을 포함하는 소정 부분이 긴띠 형상(도시되지 않음)으로 노출되게 패터닝된 제 2 감광막(25)을 형성한다.Referring to FIG. 1C, the first photosensitive film 21 is removed. A second photosensitive film 25 is formed on the second interlayer insulating layer 19 so that a predetermined portion including the first contact hole 23 is exposed in a long band shape (not shown).
제 2 감광막(25)을 마스크로 사용하여 식각정지층(17)이 노출되도록 제 2 층간절연층(19)의 제 1 접촉홀(27)을 포함하는 부분을 이방성 식각하여 긴띠 형상(도시되지 않음)의 트렌치(28)를 형성한다. 이 때, 제 1 층간절연층(15)은 노출된 부분이 식각되나 식각정지층(17)이 형성된 나머지 부분은 이 식각정지층(17)이 제 2 층간절연층(19)과 높은 식각 선택비를 가지므로 식각되지 않아 제 1 층간절연층(15)이 식각되는 것을 방지한다. 그러므로, 제 2 층간절연층(19) 내에 형성된 제 1 접촉홀(23)은 제거되면서 그 형상이 제 1 층간절연층(15)으로 전사되는 데, 연속해서, 제 1 층간절연층(15)을 과도 식각하여 제 1 배선(13)을 노출시키는 제 2 접촉홀(27)을 형성한다.Using the second photosensitive film 25 as a mask, a portion including the first contact hole 27 of the second interlayer insulating layer 19 is anisotropically etched to expose the etch stop layer 17 (not shown). Trenches 28 are formed. In this case, the exposed portion of the first interlayer insulating layer 15 is etched, but the remaining portion where the etch stop layer 17 is formed is the etch stop layer 17 having a high etching selectivity with the second interlayer insulating layer 19. Since it is not etched to prevent the first interlayer insulating layer 15 is etched. Therefore, while the first contact hole 23 formed in the second interlayer insulating layer 19 is removed, its shape is transferred to the first interlayer insulating layer 15, and subsequently, the first interlayer insulating layer 15 is removed. The second contact hole 27 exposing the first wiring 13 is formed by excessive etching.
도 1d를 참조하면, 제 2 감광막(25)을 제거한다. 그리고, 제 2 층간절연층(19) 상에 도전성 금속을 트렌치(28) 및 제 2 접촉홀(27)을 채워 제 1 배선(13)과 접촉되도록 증착한다. 그리고, 도전성 금속을 제 2 층간절연층(19)이 노출되도록 CMP 방법등으로 에치백하여 제 2 배선(29)을 형성한다.Referring to FIG. 1D, the second photosensitive film 25 is removed. Then, a conductive metal is deposited on the second interlayer insulating layer 19 to fill the trench 28 and the second contact hole 27 to be in contact with the first wiring 13. Then, the conductive metal is etched back using the CMP method or the like so as to expose the second interlayer insulating layer 19 to form the second wiring 29.
그러나, 종래 기술에 따른 반도체장치의 다층배선 형성방법은 제 1 배선을 노출시키는 제 1 접촉홀을 형성하기 위해 유전율이 큰 질화실리콘으로 이루어진 정지층을 형성하므로 공정이 복잡할 뿐만 아니라 소자의 동작 속도가 늦어지는 문제점이 있었다. 또한, 제 2 감광막을 노광 및 현상할 때 제 1 접촉홀 내부에 채워진 감광물질의 제거가 쉽지 않으므로 제 2 접촉홀을 형성하기 어려워 문제점이 있었다.However, the method for forming a multilayer wiring of a semiconductor device according to the prior art forms a stop layer made of silicon nitride having a high dielectric constant to form the first contact hole exposing the first wiring, which not only makes the process complicated but also the operation speed of the device. There was a problem of being delayed. In addition, there is a problem in that it is difficult to form the second contact hole because it is not easy to remove the photosensitive material filled in the first contact hole when exposing and developing the second photoresist film.
따라서, 본 발명의 목적은 공정이 간단하고 소자의 동작 속도를 향상시킬 수 있는 반도체장치의 다층배선 형성방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for forming a multilayer wiring of a semiconductor device which can simplify the process and improve the operation speed of the device.
본 발명의 다른 목적은 제 2 접촉홀을 원하는 형상으로 용이하게 형성할 수 있는 반도체장치의 다층배선 형성방법을 제공함에 있다.Another object of the present invention is to provide a method for forming a multilayer wiring of a semiconductor device which can easily form a second contact hole in a desired shape.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 다층배선 형성방법은 기판 상에 제 1 배선을 긴띠 형상으로 형성하고 상기 기판 상에 제 1 배선을 덮는 층간절연층을 형성하는 공정과, 상기 층간절연층 상에 상기 제 1 배선의 소정 부분과 대응하여 접촉홀이 형성될 부분을 노출시키는 제 1 감광막과 상기 층간절연층의 노출된 부분을 포함하여 상기 제 1 감광막을 긴띠 형상으로 노출시키는 제 2 감광막을 형성하되 상기 제 2 감광막이 상기 제 1 감광막 보다 감응 특성이 저하되도록 형성하는 공정과, 상기 제 2 감광막의 형상이 상기 제 1 감광막으로 전사되도록 상기 제 2 및 제 1 감광막을 제거하면서 상기 절연층의 노출된 부분을 식각하여 제 1 접촉홀을 형성하는 공정과, 상기 잔류하는 제 1 감광막을 마스크로 사용하여 상기 층간절연층의 노출된 부분을 이방성 식각하여 상기 제 1 배선을 노출하는 제 2 접촉홀과 긴띠 형상의 트렌치를 형성하는 공정과, 상기 제 2 접촉홀 및 트렌치를 채우는 제 2 배선을 형성하는 공정을 구비한다.According to an aspect of the present invention, there is provided a method for forming a multilayer wiring of a semiconductor device, the method including forming a first wiring in a long band shape on a substrate and forming an interlayer insulating layer covering the first wiring on the substrate; A second photosensitive film including a first photosensitive film exposing a portion where a contact hole is to be formed corresponding to a predetermined portion of the first wiring on the insulating layer and an exposed portion of the interlayer insulating layer, and exposing the first photosensitive film in a long band shape. Forming a photoresist film such that the second photoresist film is lowered in sensitivity than the first photoresist film, and removing the second and first photoresist films so that the shape of the second photoresist film is transferred to the first photoresist film. Etching the exposed portion of the layer to form a first contact hole, and using the remaining first photoresist as a mask; By anisotropic etching a portion and a second step of forming a trench in the contact holes and gintti shape that exposes the first wiring, and a step of forming a second wiring for filling the second contact hole and a trench.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 다층배선 형성방법을 도시하는 공정도1A to 1D are process diagrams illustrating a method for forming a multilayer wiring of a semiconductor device according to the prior art.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 다층배선 형성방법을 도시하는 공정도2A to 2D are process diagrams illustrating a method for forming a multilayer wiring of a semiconductor device according to the present invention.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 다층배선 형성방법을 도시하는 공정도이다.2A to 2D are process drawings showing a method for forming a multilayer wiring of a semiconductor device according to the present invention.
도 2a를 참조하면, 기판(31) 상에 도전성 금속을 증착한 후 포토리쏘그래피 방법에 의해 패터닝하여 제 1 배선(33)을 긴띠 형상(도시되지 않음)으로 형성한다. 상기에서 기판(31)은 반도체기판 상에 절연막이 형성된 것이다.Referring to FIG. 2A, the conductive metal is deposited on the substrate 31 and then patterned by a photolithography method to form the first wiring 33 in a long band shape (not shown). The substrate 31 is an insulating film formed on a semiconductor substrate.
기판(31) 상에 제 1 배선(33)을 덮도록 산화실리콘을 CVD 방법으로 증착하여 층간절연층(35)을 형성하고 CMP 방법으로 에치백하여 표면을 평탄화시킨다. 그리고, 층간절연층(35) 상에 감응 특성이 좋은 감광물질, 예를 들면, 원자외선(deep UV)에 감응되는 감광물질을 도포하여 제 1 감광막(37)을 형성한 후 사진 공정으로 층간절연층(35)의 제 1 배선(33)과 대응하는 접촉홀을 형성할 소정 부분을 노출시킨다.Silicon oxide is deposited on the substrate 31 to cover the first wiring 33 by CVD to form an interlayer insulating layer 35 and etched back by CMP to planarize the surface. The first photosensitive film 37 is formed by applying a photosensitive material having good sensitivity, for example, deep UV, on the interlayer insulating layer 35 to form a first photosensitive film 37, and then performing interlayer insulation by a photographic process. The predetermined portion to form a contact hole corresponding to the first wiring 33 of the layer 35 is exposed.
제 1 감광막(37) 상에 층간절연층(35)의 노출된 부분을 덮도록 감응 특성이 제 1 감광막(37) 보다 저하되는 감광물질, 예를 들면, i-선(i-line)에 감응되는 감광물질을 도포하여 제 2 감광막(39)을 형성한다. 그리고, 제 2 감광막(39)을 층간절연층(35)의 노출된 부분을 포함하는 제 1 감광막(37)의 소정 부분이 긴띠 형상(도시되지 않음)으로 노출되게 패터닝한다. 이 때, 제 1 감광막(37) 사이의 제 2 감광막(39)이 두껍게 형성되지 않으므로 노광 및 현상시 감광물질의 제거가 용이하다. 또한, 제 2 감광막(39)은 제 1 감광막(37) 보다 넓은 폭을 갖도록 형성되어야 한다.Responding to a photosensitive material, for example, i-line, whose sensitivity is lower than that of the first photosensitive film 37 so as to cover the exposed portion of the interlayer insulating layer 35 on the first photosensitive film 37. The second photosensitive film 39 is formed by applying a photosensitive material. The second photoresist film 39 is patterned so that a predetermined portion of the first photoresist film 37 including the exposed portion of the interlayer insulating layer 35 is exposed in a long band shape (not shown). At this time, since the second photoresist film 39 between the first photoresist film 37 is not formed thick, it is easy to remove the photosensitive material during exposure and development. In addition, the second photosensitive film 39 should be formed to have a wider width than the first photosensitive film 37.
도 2b를 참조하면, 층간절연막(35)의 노출된 부분을 CF4, C2F6또는 CHF3등과 같이 불소(F)를 포함하는 가스와 O2가 혼합된 가스로 반응성이온에칭(Reactive Ion Etching : 이하, RIE라 칭함) 등의 이방성 식각 방법으로 식각하여 제 1 접촉홀(41)를 형성한다. 이 때, 제 1 접촉홀(41)은 제 1 감광막(37)의 패터닝된 형태가 전사되어 형성된다. 또한, 제 1 접촉홀(41) 형성시 제 2 감광막(39)과 제 1 감광막(37)의 노출된 부분도 식각되어 제 1 감광막(37) 및 층간절연층(35)을 노출시키는 데, 제 1 감광막(37)은 제 2 감광막(37)의 패터닝된 형태가 전사되어 긴띠 형상(도시되지 않음)으로 형성된다.Referring to FIG. 2B, reactive ion etching is performed by exposing the exposed portion of the interlayer insulating layer 35 to a gas containing fluorine (F) and O 2 , such as CF 4 , C 2 F 6, or CHF 3 . Etching: Hereinafter, the first contact hole 41 is formed by etching by an anisotropic etching method such as RIE). At this time, the first contact hole 41 is formed by transferring the patterned form of the first photosensitive film 37. In addition, when the first contact hole 41 is formed, exposed portions of the second photoresist film 39 and the first photoresist film 37 are also etched to expose the first photoresist film 37 and the interlayer insulating layer 35. The first photosensitive film 37 is formed into a long band shape (not shown) by transferring the patterned form of the second photosensitive film 37.
도 2c를 참조하면, 제 1 감광막(37)을 마스크로 사용하여 층간절연층(35)의 노출된 부분을 이방성 식각하여 제 1 배선(33)을 노출하는 제 2 접촉홀(43)과 긴띠 형상(도시되지 않음)의 트렌치(45)를 형성한다. 상기에서, 제 2 접촉홀(43)은 제 1 접촉홀(41)이 전사되어 형성되며, 제 1 접촉홀(41)은 트렌치(45)가 이 제 1 접촉홀(41) 보다 넓게 형성됨에 따라 제거되어진다.Referring to FIG. 2C, an exposed portion of the interlayer insulating layer 35 is anisotropically etched using the first photoresist film 37 as a mask to form a second contact hole 43 and an elongated band shape to expose the first wiring 33. A trench 45 (not shown) is formed. In the above, the second contact hole 43 is formed by transferring the first contact hole 41, and the first contact hole 41 is formed as the trench 45 is wider than the first contact hole 41. Removed.
도 2d를 참조하면, 제 1 감광막(37)을 제거한다.Referring to FIG. 2D, the first photosensitive film 37 is removed.
층간절연층(35) 상에 알루미늄, 구리, 금, 은, 백금 또는 이들의 합금으로 이루어진 도전성 금속을 스퍼터링(suppering) 또는 CVD 등의 방법으로 제 1 접촉홀(41)은 트렌치(45)를 채우도록 증착한다. 그리고, 도전성 금속을 층간절연층(35)이 노출되도록 CMP 방법등으로 에치백하여 제 2 배선(47)을 형성한다.The first contact hole 41 fills the trench 45 by, for example, sputtering or CVD of a conductive metal made of aluminum, copper, gold, silver, platinum, or an alloy thereof on the interlayer insulating layer 35. To be deposited. Then, the conductive metal is etched back using the CMP method or the like to expose the interlayer insulating layer 35 to form the second wiring 47.
상술한 바와 같이 본 발명에 따른 반도체장치의 다층배선 형성방법은 단일의 층간절연막 상의 제 1 배선과 대응하는 접촉홀을 형성할 소정 부분을 노출시키는 감응 특성이 제 1 감광막과, 이 제 1 감광막 보다 감응 특성이 저하되는 제 2 감광막을 층간절연층의 노출된 부분을 포함하는 제 1 감광막의 소정 부분이 긴띠 형상(도시되지 않음)으로 노출되게 형성한다. 그리고, 제 2 및 제 1 감광막과 함께 층간절연막의 노출된 부분을 CF4, C2F6또는 CHF3등과 같이 불소(F)를 포함하는 가스와 O2가 혼합된 가스로 이방성 식각하여 제 1 접촉홀을 형성하고, 제 1 감광막을 마스크로 사옹하여 층간절연층을 식각하여 제 2 접촉홀과 트렌치를 형성한 후 제 1 접촉홀 및 트렌치를 채우는 제 2 배선을 형성한다.As described above, in the method for forming a multilayer wiring of the semiconductor device according to the present invention, the sensitivity of exposing a predetermined portion to form a contact hole corresponding to the first wiring on a single interlayer insulating film is higher than that of the first photosensitive film and the first photosensitive film. A second photoresist film whose sensitivity is deteriorated is formed such that a predetermined portion of the first photoresist film including an exposed portion of the interlayer insulating layer is exposed in a long band shape (not shown). The exposed portion of the interlayer insulating layer together with the second and first photoresist layers is anisotropically etched with a gas containing fluorine (F) and O 2 , such as CF 4 , C 2 F 6, or CHF 3 . A contact hole is formed, the first photoresist film is used as a mask, the interlayer insulating layer is etched to form a second contact hole and a trench, and a second wiring filling the first contact hole and the trench is formed.
따라서, 본 발명은 식각정지층을 형성하지 않으므로 공정이 간단할 뿐만 아니라 소자의 동작 속도를 향상시킬 수 있으며, 또한, 제 2 감광막을 패터닝할 때 감광물질을 쉽게 제거할 수 있어 접촉홀을 원하는 형상으로 용이하게 형성할 수 있는 잇점이 있다.Therefore, the present invention does not form an etch stop layer, so that the process is not only simple, and the operation speed of the device can be improved, and the photosensitive material can be easily removed when patterning the second photoresist film so that a contact hole is desired. There is an advantage that can be easily formed.
Claims (3)
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| KR1019980037794A KR20000019607A (en) | 1998-09-14 | 1998-09-14 | Method for forming multi-layered line of semiconductor device |
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| KR1019980037794A KR20000019607A (en) | 1998-09-14 | 1998-09-14 | Method for forming multi-layered line of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100370159B1 (en) * | 2000-10-11 | 2003-01-30 | 주식회사 하이닉스반도체 | Method for Fabricating Semiconductor Device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100370159B1 (en) * | 2000-10-11 | 2003-01-30 | 주식회사 하이닉스반도체 | Method for Fabricating Semiconductor Device |
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