KR20020058429A - A wire in semiconductor device and method for fabricating the same - Google Patents
A wire in semiconductor device and method for fabricating the same Download PDFInfo
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- KR20020058429A KR20020058429A KR1020000086534A KR20000086534A KR20020058429A KR 20020058429 A KR20020058429 A KR 20020058429A KR 1020000086534 A KR1020000086534 A KR 1020000086534A KR 20000086534 A KR20000086534 A KR 20000086534A KR 20020058429 A KR20020058429 A KR 20020058429A
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 89
- 239000011229 interlayer Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract 2
- 238000000059 patterning Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자에 대한 것으로, 특히 반도체소자의 배선 및 그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a wiring of a semiconductor device and a method of forming the same.
첨부 도면을 참조하여 종래 반도체소자의 배선 형성방법에 대하여 설명하면다음과 같다.Referring to the accompanying drawings, a wiring forming method of a conventional semiconductor device will be described.
도 1a 내지 도 1e는 종래 반도체소자의 배선 형성방법을 나타낸 공정단면도 이다.1A to 1E are cross-sectional views illustrating a method of forming a wiring of a conventional semiconductor device.
종래 반도체소자의 배선 형성방법은 듀얼 다머신(Dual Damascene)공정으로써 실리콘기판(도면에는 도시되지 않음)에 도 1a에 도시한 바와 같이 제 1 층간절연막(1)의 일영역에 하부배선층(2)을 형성하고, 하부배선층(2)과 제 1 층간절연막(1)상에 제 1 식각스톱층(3)과 제 2 층간절연막(4)과 제 2 식각스톱층(5)과 제 3 층간절연막(6)과 제 1 감광막(7)을 차례로 형성한다.A conventional method for forming a wiring of a semiconductor device is a dual damascene process using a silicon substrate (not shown) as shown in FIG. 1A, as shown in FIG. 1A, a lower wiring layer 2 in one region of the first interlayer insulating film 1. And a first etch stop layer 3, a second interlayer dielectric film 4, a second etch stop layer 5, and a third interlayer dielectric layer on the lower wiring layer 2 and the first interlayer dielectric layer 1 6) and the first photosensitive film 7 are sequentially formed.
이후에 일정폭으로 제 3 층간절연막(6)이 드러나도록 제 1 감광막(7)을 패터닝한다.Thereafter, the first photosensitive film 7 is patterned to expose the third interlayer insulating film 6 at a predetermined width.
그리고 도 1b에 도시한 바와 같이 패터닝된 제 1 감광막(7)을 마스크로 제 3 층간절연막(6)과 제 2 식각스톱층(5)과 제 2 층간절연막(4)을 차례로 식각해서 제 1 홀을 형성한다.1B, the third interlayer insulating film 6, the second etch stop layer 5, and the second interlayer insulating film 4 are sequentially etched using the patterned first photosensitive film 7 as a mask. To form.
그리고 도 1c에 도시한 바와 같이 전면에 제 2 감광막(9)을 도포한 후에 제 1 홀보다 넓은 폭을 갖도록 제 2 감광막(9)을 패터닝한다.As shown in FIG. 1C, after applying the second photosensitive film 9 to the entire surface, the second photosensitive film 9 is patterned to have a wider width than the first hole.
이후에 패터닝된 제 2 감광막(9)을 마스크로 제 3 층간절연막(6)을 식각해서 제 2 홀을 형성한다.Thereafter, the third interlayer insulating film 6 is etched using the patterned second photosensitive film 9 to form second holes.
다음에 도 1e에 도시한 바와 같이 전면에 전도층을 증착한 후에 제 1, 제 2 홀내에만 남도록 전도층을 식각해서 2중의 폭을 갖는 콘택플러그(10)를 형성한다.Next, as shown in FIG. 1E, after the conductive layer is deposited on the entire surface, the conductive layer is etched to remain only in the first and second holes, thereby forming a contact plug 10 having a double width.
이와 같은 종래 배선 형성방법은 도면에는 도시되지 않았지만 비아홀 형성공정과 금속라인 배선의 형성을 구분하여 형성해야 한다.Although not shown in the drawings, such a conventional wiring forming method should be formed by separating the via hole forming process and the formation of the metal line wiring.
상기와 같은 종래 반도체소자의 배선 형성방법은 다음과 같은 문제가 있다.The wiring formation method of the conventional semiconductor device as described above has the following problems.
비아홀 형성공정과 금속라인 배선의 형성을 별도로 형성하므로 공정이 복잡하고, 금속라인 배선폭이 축소되면 금속배선의 저항력이 저하되고 일레이트 마이그레이션과 스트레스 마이그레이션 특성이 열화되는등 배선의 신뢰성이 낮아지는 문제가 발생한다.As the via hole forming process and the metal line wiring are formed separately, the process is complicated, and when the width of the metal line wiring is reduced, the reliability of the wiring is lowered, such as the resistance of the metal wiring is lowered, and the yield rate and stress migration characteristics are deteriorated. Occurs.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 공정을 단순화하면 배선의 신뢰성을 향상시키기에 알맞은 반도체소자의 배선 및 그 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in particular, it is an object of the present invention to provide a semiconductor device wiring and a method of forming the semiconductor device suitable for improving the reliability of the wiring by simplifying the process.
도 1a 내지 도 1e는 종래 반도체소자의 배선 형성방법을 나타낸 공정단면도1A through 1E are cross-sectional views illustrating a method of forming a wiring of a conventional semiconductor device.
도 2a 내지 도 2f는 본 발명 실시예에 따른 반도체소자의 배선 형성방법을 나타낸 공정단면도2A through 2F are cross-sectional views illustrating a method of forming wirings in a semiconductor device in accordance with an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 하부배선층 22 : 제 1 층간절연막21: lower wiring layer 22: first interlayer insulating film
23 : 식각스톱층 24 : 제 1 감광막23: etching stop layer 24: first photosensitive film
25 : 제 1 전도층 25a : 콘택플러그25: first conductive layer 25a: contact plug
25b : 전도층 측벽 26 : 제 2 층간절연막25b: sidewall of conductive layer 26: second interlayer insulating film
27 : 제 2 감광막 28a,28b : 금속배선27: second photosensitive film 28a, 28b: metal wiring
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 배선은 콘택플러그 형성을 위한 제 1 영역과 금속라인 형성을 위한 제 2 영역이 정의된 기판에 있어서, 상기 기판의 제 1 영역에 형성된 하부배선층, 상기 하부배선층을 포함한 상기 기판에 차례로 형성된 제 1 층간절연막과 식각스톱층, 상기 제 1,제 2 영역의 상기 하부배선층과 상기 기판의 일영역이 드러나게 동시에 형성된 비아홀과 콘택홀, 상기 비아홀에 형성된 콘택플러그와 상기 콘택홀의 측면에 형성된 전도층 측벽, 상기 제 1, 제 2 영역의 상기 콘택플러그와 상기 기판과 전도층 측면이 드러나게 홀을 갖는 제 2 층간절연막, 상기 제 1, 제 2 영역의 홀내에 각각 형성된 금속라인을 포함함을 특징으로 한다.In the semiconductor device wiring for achieving the above object, the wiring includes: a lower wiring layer formed in the first region of the substrate, the substrate defining a first region for forming a contact plug and a second region for forming a metal line; A first interlayer insulating layer and an etch stop layer sequentially formed on the substrate including the lower wiring layer, a via hole and a contact hole simultaneously formed to expose the lower wiring layer of the first and second regions and a region of the substrate, and a contact formed in the via hole. A second interlayer insulating film having a plug and a conductive layer sidewall formed on side surfaces of the contact hole, the contact plugs of the first and second regions, and a hole in which the side surfaces of the substrate and the conductive layer are exposed, and within the holes of the first and second regions It characterized in that it comprises a metal line each formed.
상기의 구성을 갖는 본 발명 반도체소자의 배선 형성방법은 콘택플러그 형성을 위한 제 1 영역과 금속라인 형성을 위한 제 2 영역이 정의된 기판에 있어서, 상기 기판의 제 1 영역에 하부배선층을 형성하는 공정, 상기 하부배선층을 포함한 상기 기판에 제 1 층간절연막과 식각스톱층을 차례로 형성하는 공정, 상기 제 1, 제 2 영역의 상기 하부배선층과 상기 기판의 일영역이 드러나게 비아홀과 콘택홀을 동시에 형성하는 공정, 상기 비아홀에 콘택플러그를 형성함과 동시에 상기 콘택홀의 측면에 전도층 측벽을 형성하는 공정, 상기 제 1, 제 2 영역의 상기 콘택플러그와 상기 기판과 전도층 측면이 드러나는 홀을 갖는 제 2 층간절연막을 형성하는 공정, 상기 제 1, 제 2 영역의 홀내에 금속라인을 형성하는 공정을 포함함을 특징으로 한다.In the method for forming a wiring of the semiconductor device of the present invention having the above structure, in a substrate in which a first region for forming a contact plug and a second region for forming a metal line are defined, a lower wiring layer is formed in the first region of the substrate. Forming a first interlayer insulating film and an etch stop layer on the substrate including the lower wiring layer, and simultaneously forming a via hole and a contact hole to expose the lower wiring layer of the first and second regions and a region of the substrate. Forming a contact plug in the via hole and simultaneously forming a sidewall of the conductive layer on the side of the contact hole; and forming a contact plug in the first and second regions and a hole in which the side surface of the substrate and the conductive layer are exposed. Forming a second interlayer insulating film; and forming a metal line in the holes of the first and second regions.
첨부 도면을 참조하여 본 발명 반도체소자의 배선 및 그 형성방법에 대하여 설명하면 다음과 같다.A wiring and a method of forming the semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명 실시예에 따른 반도체소자의 배선 형성방법을 나타낸 공정단면도 이다.2A through 2F are cross-sectional views illustrating a method of forming wirings in a semiconductor device in accordance with an embodiment of the present invention.
본 발명은 다층 배선 형성 방법중 다머신(Damascene) 공정방법을 변형시킨 것으로써 비아홀 형성공정과 금속라인 배선 형성공정을 동시에 진행할 수 있는 방법에 관한 것이다.The present invention relates to a method in which the via hole forming process and the metal line wiring forming process can be simultaneously performed by modifying the damascene process method among the multilayer wiring forming methods.
먼저 본 발명 실시예에 따른 반도체소자의 배선은 도 2f에 도시한 바와 같이 콘택플러그(25a) 형성을 위한 제 1 영역과 금속배선(28b) 형성을 위한 제 2 영역이 정의된 실리콘기판에 있어서, 상기 실리콘기판의 제 1 영역에 하부배선층(21)이 형성되었고, 상기 하부배선층(21)을 포함한 상기 실리콘기판에 차례로 제 1 층간절연막(22)과 식각스톱층(23)이 형성되었고, 상기 제 1,제 2 영역의 상기 하부배선층(21)과 상기 실리콘기판의 일영역이 드러나게 동시에 비아홀과 콘택홀이 형성되어 있다.First, as shown in FIG. 2F, a semiconductor device wiring according to an embodiment of the present invention has a silicon substrate in which a first region for forming a contact plug 25a and a second region for forming a metal wiring 28b are defined. A lower interconnection layer 21 is formed in the first region of the silicon substrate, and a first interlayer dielectric layer 22 and an etch stop layer 23 are sequentially formed on the silicon substrate including the lower interconnection layer 21. Via holes and contact holes are simultaneously formed to expose the lower wiring layer 21 and the silicon substrate in the first and second regions.
그리고 상기 비아홀에 콘택플러그(25a)와 상기 콘택홀의 측면에 전도층 측벽(25b)가 형성되었고, 상기 제 1, 제 2 영역의 상기 콘택플러그(25a)와 상기 실리콘기판과 전도층 측면(25b)이 드러나게 홀을 갖는 제 2 층간절연막(26)이 있고, 상기 제 1, 제 2 영역의 홀내에 각각 금속배선(28a,28b)가 형성되어 있다.In addition, a contact plug 25a and a conductive layer sidewall 25b are formed on the sidewalls of the contact hole, and the contact plug 25a and the silicon substrate and the sidewall 25b of the first and second regions are formed in the via hole. There is a second interlayer insulating film 26 having such a hole, and metal wirings 28a and 28b are formed in the holes of the first and second regions, respectively.
다음에 본 발명 반도체소자의 배선 형성방법은 도 2a에 도시한 바와 같이 실리콘기판의 일영역상에 하부배선층(21)을 형성하고, 하부배선층(21)을 포함한 실리콘기판상에 제 1 층간절연막(22)을 형성한다.Next, in the method of forming a wiring of the semiconductor device according to the present invention, as shown in FIG. 2A, the lower wiring layer 21 is formed on one region of the silicon substrate, and the first interlayer insulating film is formed on the silicon substrate including the lower wiring layer 21. 22).
이때 제 1 층간절연막(22)은 BPSG, PSG, BSG, TEOS, HDP 산화막이나 유전상수가 낮은 PTFE, SILK, HOSP나 FLARE와 같은 재료를 사용한다.At this time, the first interlayer insulating film 22 uses a material such as BPSG, PSG, BSG, TEOS, HDP oxide film or PTFE, SILK, HOSP or FLARE having a low dielectric constant.
그리고 제 1 층간절연막(22)상에 식각스톱층(23)을 증착하고 식각스톱층(23)상에 제 1 감광막(24)을 도포한다.The etch stop layer 23 is deposited on the first interlayer insulating film 22, and the first photosensitive film 24 is coated on the etch stop layer 23.
그리고 노광 및 현상공정으로 제 1 감광막(24)을 선택적으로 패터닝한다.The first photosensitive film 24 is selectively patterned by exposure and development.
이때 하부배선층(21)이 형성된 실리콘기판의 왼쪽은 차후에 비아홀과 콘택플러그 및 배선층이 적층 형성될 제 1 영역이고, 하부배선층(21)이 형성되지 않은 오른쪽은 금속 배선층만 형성될 제 2 영역이다.In this case, the left side of the silicon substrate on which the lower wiring layer 21 is formed is a first region in which via holes, contact plugs, and wiring layers are to be subsequently stacked, and the right side of the silicon substrate on which the lower wiring layer 21 is not formed is a second region in which only a metal wiring layer is to be formed.
그리고 제 1 감광막(24)은 제 1, 제 2 영역의 식각스톱층(23)만 드러나도록패터닝하는 것이다.In addition, the first photoresist layer 24 is patterned so that only the etch stop layer 23 of the first and second regions is exposed.
상기에서 식각스톱층(23)은 SiON이나 PE 나이트라이드를 대략 1000Å정도의 두께를 갖도록 형성한다.The etch stop layer 23 is formed to have a thickness of about 1000 kPa of SiON or PE nitride.
이후에 도 2b에 도시한 바와 같이 패터닝된 제 1 감광막(24)을 마스크로 제 1 층간절연막(22)을 플라즈마식각해서 제 1 영역에 비아홀과 제 2 영역에 콘택홀을 동시에 형성한다.Subsequently, as shown in FIG. 2B, the first interlayer insulating layer 22 is plasma-etched using the patterned first photoresist layer 24 to form a via hole in the first region and a contact hole in the second region.
이때 비아홀은 0.1~0.5㎛, 콘택홀은 0.3~2.0㎛의 크기를 갖도록 형성한다.At this time, the via hole is formed to have a size of 0.1 ~ 0.5㎛, contact hole 0.3 ~ 2.0㎛.
그리고 비아홀과 콘택홀을 포함한 식각스톱층(23)상에 제 1 전도층(25)을 증착한다. 이때 제 1 전도층(25)은 비아홀 형성영역은 완벽하게 매립되도록 형성하고 콘택홀영역은 그 표면을 따라서 형성되도록 한다. 그리고 제 1 전도층(25)은 텅스텐과 티타늄 나이트라이드막을 화학기상 증착법으로 형성한다.The first conductive layer 25 is deposited on the etch stop layer 23 including the via hole and the contact hole. In this case, the first conductive layer 25 is formed so that the via hole forming region is completely filled and the contact hole region is formed along the surface thereof. The first conductive layer 25 forms a tungsten and titanium nitride film by chemical vapor deposition.
그리고 도 2c에 도시한 바와 같이 제 1 전도층(25)을 에치백하여 비아홀내에 콘택플러그(25a)를 형성하고, 콘택홀의 측면에 전도층 측벽(25b)을 형성한다.As illustrated in FIG. 2C, the first conductive layer 25 is etched back to form a contact plug 25a in the via hole, and the sidewall 25b of the conductive layer is formed on the side of the contact hole.
그리고 도 2d에 도시한 바와 같이 콘택플러그(25a)와 전도층 측벽(25b)을 포함한 전면에 제 2 층간절연막(26)을 증착하고, 전면에 제 2 감광막(27)을 도포한다.As shown in FIG. 2D, the second interlayer insulating film 26 is deposited on the entire surface including the contact plug 25a and the conductive layer sidewall 25b, and the second photosensitive film 27 is coated on the entire surface.
이어서 노광 및 현상공정으로 제 1, 제 2 영역상의 제 2 층간절연막(26)만 드러나도록 제 2 감광막(27)을 선택적으로 패터닝한다.Subsequently, the second photosensitive film 27 is selectively patterned so that only the second interlayer insulating film 26 on the first and second regions is exposed by the exposure and development processes.
이후에 패터닝된 제 2 감광막(27)을 마스크로 제 2 층간절연막(26)을 식각해서 콘택플러그(25a) 및 그에 연장된 식각스톱층(23)과 제 2 영역의 콘택홀과 전도층 측벽(25b)이 드러나도록 각각 홀을 한다.Subsequently, the second interlayer insulating layer 26 is etched using the patterned second photosensitive layer 27 as a mask to etch the contact plug 25a, the etch stop layer 23 extending therefrom, and the contact hole and conductive layer sidewalls of the second region ( Make holes each to reveal 25b).
다음에 도 2f에 도시한 바와 같이 상기 제 1, 제 2 영역의 홀을 포함한 전면에 제 2 전도층을 증착한 후에 에치백이나 평탄화공정이나 플라즈마 시각을 이용해서 제 1 영역의 홀과 제 2 영역의 홀에 각각 금속배선(28)을 형성한다.Next, as illustrated in FIG. 2F, after the second conductive layer is deposited on the entire surface including the holes of the first and second regions, the holes and the second regions of the first region are etched, planarized, or plasma-viewed. Metal wiring 28 is formed in each of the holes of.
그리고 제 2 전도층은 알루미늄이나 구리나 텅스텐으로 형성한다.The second conductive layer is made of aluminum, copper or tungsten.
상기와 같은 본 발명 반도체소자의 배선 및 그 형성방법은 다음과 같은 효과가 있다.As described above, the wiring and the method of forming the semiconductor device of the present invention have the following effects.
첫째, 콘택플러그 형성용 비아홀과 금속배선 형성용 콘택홀을 하나의 마스크를 이용해서 동시에 형성하므로 다층 배선을 위한 공정을 간단히 할 수 있다.First, since the contact plug forming via hole and the metal wiring forming contact hole are simultaneously formed using one mask, the process for the multilayer wiring can be simplified.
둘째, 금속배선의 폭이 줄어들어도 금속라인 형성을 용이하게 실시할 수 있으므로 저항력을 개선하고 일렉트로 마이그레이션과 스트레스 마이그레이션 특성을 개선하여 배선의 신뢰성을 향상시킬 수 있다.Second, even if the width of the metal wiring is reduced, the metal line can be easily formed, thereby improving the resistance and improving the reliability of the wiring by improving the electromigration and stress migration characteristics.
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| KR101051950B1 (en) * | 2003-12-15 | 2011-07-26 | 매그나칩 반도체 유한회사 | Manufacturing method of semiconductor device |
| KR101064284B1 (en) * | 2004-01-09 | 2011-09-14 | 매그나칩 반도체 유한회사 | Methode of forming a contact hole in semiconductor device |
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| KR960010055B1 (en) * | 1992-12-10 | 1996-07-25 | Hyundai Electronics Ind | Tungsten plug manufacturing method |
| KR960004078B1 (en) * | 1992-12-17 | 1996-03-26 | 현대전자산업주식회사 | Contact forming method by stacked thin layer structure |
| KR100267808B1 (en) * | 1998-07-10 | 2000-11-01 | 김영환 | Method for forming multilayer wiring of semiconductor device using superconductor material |
| KR100280288B1 (en) * | 1999-02-04 | 2001-01-15 | 윤종용 | Method for fabricating capacitor of semiconcuctor integrated circuit |
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| KR101051950B1 (en) * | 2003-12-15 | 2011-07-26 | 매그나칩 반도체 유한회사 | Manufacturing method of semiconductor device |
| KR101064284B1 (en) * | 2004-01-09 | 2011-09-14 | 매그나칩 반도체 유한회사 | Methode of forming a contact hole in semiconductor device |
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