KR20070054892A - Method for fabrication a semiconductor device - Google Patents

Method for fabrication a semiconductor device Download PDF

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KR20070054892A
KR20070054892A KR1020050112985A KR20050112985A KR20070054892A KR 20070054892 A KR20070054892 A KR 20070054892A KR 1020050112985 A KR1020050112985 A KR 1020050112985A KR 20050112985 A KR20050112985 A KR 20050112985A KR 20070054892 A KR20070054892 A KR 20070054892A
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insulating film
trench
semiconductor substrate
depth
film
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KR1020050112985A
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Korean (ko)
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KR100807074B1 (en
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노치형
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Abstract

본 발명은 반도체기판 상부에 패드산화막 및 제 1 절연막을 순차적으로 형성하는 단계; 상기 제 1 절연막이 소정의 폭을 갖도록 식각하여 반도체 기판의 소정영역을 노출시키는 단계; 전체구조상부에 제 2 절연막을 형성한 후, 제 1 전면식각 공정을 실시하여 상기 제 1 절연막 측벽에 제 2 절연막을 잔류시키는 단계; 상기 제 1 절연막 및 제 2 절연막을 마스크로, 노출된 반도체 기판을 식각하여 제 1 깊이의 제 1 트랜치를 형성하는 단계; 상기 제 1 절연막을 제거하여 반도체 기판을 노출시키는 단계; 상기 잔류된 제 2 절연막을 마스크로 제 2 전면식각 공정을 실시하여 상기 제 1 트렌치가 제 2 깊이가 되도록 하고, 상기 반도체 기판의 소정 영역에 제 1 트렌치 보다 얕은 깊이의 제 2 트렌치를 형성하는 단계; 및 상기 잔류된 제 2 절연막을 제거하는 단계를 포함하는 반도체 소자의 제조 방법을 개시한다.The present invention includes sequentially forming a pad oxide film and a first insulating film on an upper surface of a semiconductor substrate; Etching the first insulating layer to have a predetermined width to expose a predetermined region of the semiconductor substrate; Forming a second insulating film on the entire structure, and then performing a first front etching process to leave a second insulating film on the sidewalls of the first insulating film; Etching the exposed semiconductor substrate using the first insulating film and the second insulating film as a mask to form a first trench having a first depth; Removing the first insulating film to expose the semiconductor substrate; Performing a second front surface etching process using the remaining second insulating layer as a mask so that the first trench has a second depth, and forming a second trench having a depth smaller than the first trench in a predetermined region of the semiconductor substrate; ; And removing the remaining second insulating film.

에스오지(Silicon On Glass ;SOG), 고밀도 플라즈마(High Density Plasma ;HDP), 어닐공정, 챔버 Silicon On Glass (SOG), High Density Plasma (HDP), Annealing Process, Chamber

Description

반도체 소자의 제조 방법{Method for fabrication a semiconductor device}Method for fabrication a semiconductor device

도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 제조 공정을 나타낸 단면도 이다.1A to 1E are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

100 : 반도체 기판 102 : 패드 산화막           100 semiconductor substrate 102 pad oxide film

104 : 제 1 절연막 106 : 포토 마스크           104: first insulating film 106: photo mask

108 : 제 2 절연막 108a : 일부 제 2 절연막           108: second insulating film 108a: partial second insulating film

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 단한번의 마스크 공정으로 깊이가 서로 다르거나 같은 소자분리막(Differential Shallow Trench Isolation)을 형성함으로써, 후속공정시 각 층의 중첩도(OverLayer)를 정밀하게 제어할 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, by forming a different shallow trench isolation with a different depth or the same depth in a single mask process, the overlayer of each layer is precisely determined in a subsequent process. It relates to a method for manufacturing a semiconductor device that can be controlled easily.

일반적인 반도체의 소자분리막 형성 공정에서는 셀(Cell) 영역과 주변회로 영역의 단차가 동일하게 적용되어 왔으나, 플래시 메모리 디바이스에서는 반도체의 특성을 향상시키기 위해 셀 영역과 주변회로 영역의 단차가 각기 다른 소자분리막 형성 공정이 요구되며, 이는 포토마스크 공정과 식각 공정의 비중이 높아지는 문제점이 있다.Although the steps of the cell region and the peripheral circuit region have been equally applied in the process of forming a device isolation layer of a semiconductor, in a flash memory device, the device isolation layer having different steps between the cell region and the peripheral circuit region is used to improve semiconductor characteristics. Forming process is required, which has a problem that the ratio of the photomask process and the etching process is increased.

통상적으로, 깊이가 서로 다른 소자분리막 형성을 위해서는 반도체기판 상부에 패드산화막 및 질화막을 순차적으로 형성한 후, 질화막 상부에 제 1 하드 마스크를 형성한다. 상기 제 1 하드 마스크 상부에 감광막을 도포한 후 노광 및 현상하여 제 1 감광막 패턴을 형성한다.In general, in order to form device isolation films having different depths, a pad oxide film and a nitride film are sequentially formed on the semiconductor substrate, and then a first hard mask is formed on the nitride film. After the photoresist is coated on the first hard mask, the photoresist is exposed and developed to form a first photoresist pattern.

제 1 감광막 패턴에 의해 노출된 질화막, 패드 산화막 및 반도체기판의 일부를 식각하여 제 1 깊이의 소자분리막을 형성한 후, 제 1 감광막 패턴을 제거한다.A portion of the nitride film, the pad oxide film and the semiconductor substrate exposed by the first photoresist pattern is etched to form an isolation layer having a first depth, and then the first photoresist pattern is removed.

다음, 제 2 하드 마스크를 제거되지 않고 남아있는 질화막 상부에 형성한 후, 제 2 하드 마스크 상부에 제 2 감광막을 도포한 다음 노광 및 현상하여 제 2 감광막 패턴을 형성한다.Next, after the second hard mask is formed on the nitride film remaining without being removed, the second photoresist film is coated on the second hard mask, followed by exposure and development to form a second photoresist pattern.

제 2 감광막 패턴에 의해 노출된 질화막, 패드 산화막 및 반도체기판의 일부를 식각하여 제 2 깊이의 소자분리막을 형성한 후, 제 2 감광막 패턴을 제거한다.A portion of the nitride film, the pad oxide film and the semiconductor substrate exposed by the second photoresist pattern is etched to form an isolation layer having a second depth, and then the second photoresist pattern is removed.

즉, 깊이가 서로 다른 소자분리막 형성을 위해서는 두 번의 마스크 공정이 필요하게 되어 공정의 난이도가 높아지며, 공정 진행 원가도 많이 들게되는 문제점이 있다.That is, two mask processes are required to form device isolation layers having different depths, which increases the difficulty of the process and increases the cost of the process.

본 발명은 단한번의 마스크 공정으로, 깊이가 서로 다르거나 같은 소자분리막(Differential Shallow Trench Isolation)을 형성함으로써, 후속공정시 각 층(Layer)의 중첩도(OverLayer)를 정밀하게 제어할 수 있어, 미세패턴의 형성에 용이 하고 공정 난이도를 감소시키며 공정 진행 원가 절감 등의 부대 이익을 얻을 수 있는 반도체 소자의 제조 방법을 제공함에 그 목적이 있다.According to the present invention, by forming a single isolation process (Differential Shallow Trench Isolation) having a different depth or the same depth, the OverLayer of each layer can be precisely controlled in a subsequent process. It is an object of the present invention to provide a method for manufacturing a semiconductor device which is easy to form a fine pattern, reduces process difficulty, and obtains additional benefits such as cost reduction in process progress.

본 발명의 실시예에 따른 반도체 소자의 제조방법은, 반도체기판 상부에 패드산화막 및 제 1 절연막을 순차적으로 형성하는 단계; 상기 제 1 절연막이 소정의 폭을 갖도록 식각하여 반도체 기판의 소정영역을 노출시키는 단계; 전체구조상부에 제 2 절연막을 형성한 후, 제 1 전면식각 공정을 실시하여 상기 제 1 절연막 측벽에 제 2 절연막을 잔류시키는 단계; 상기 제 1 절연막 및 제 2 절연막을 마스크로, 노출된 반도체 기판을 식각하여 제 1 깊이의 제 1 트랜치를 형성하는 단계; 상기 제 1 절연막을 제거하여 반도체 기판을 노출시키는 단계; 상기 잔류된 제 2 절연막을 마스크로 제 2 전면식각 공정을 실시하여 상기 제 1 트렌치가 제 2 깊이가 되도록 하고, 상기 반도체 기판의 소정 영역에 제 1 트렌치 보다 얕은 깊이의 제 2 트렌치를 형성하는 단계; 및 상기 잔류된 제 2 절연막을 제거하는 단계를 포함한다.A method of manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of sequentially forming a pad oxide film and a first insulating film on the semiconductor substrate; Etching the first insulating layer to have a predetermined width to expose a predetermined region of the semiconductor substrate; Forming a second insulating film on the entire structure, and then performing a first front etching process to leave a second insulating film on the sidewalls of the first insulating film; Etching the exposed semiconductor substrate using the first insulating film and the second insulating film as a mask to form a first trench having a first depth; Removing the first insulating film to expose the semiconductor substrate; Performing a second front surface etching process using the remaining second insulating layer as a mask so that the first trench has a second depth, and forming a second trench having a depth smaller than the first trench in a predetermined region of the semiconductor substrate; ; And removing the remaining second insulating film.

상기 제 1 절연막은 나이트라이드로 형성하며, 상기 제 2 절연막을 산화막 또는 아모포스카본으로 형성하는 것을 특징으로 한다.The first insulating film is formed of nitride, and the second insulating film is formed of an oxide film or amorphous carbon.

상기 제 1 절연막은 100 내지 8000 Å 의 두께로 형성하는 것을 특징으로 한다. 상기 제 1 절연막 폭은 상기 제 2 트랜치의 폭이 되도록 한다.The first insulating film is characterized in that it is formed to a thickness of 100 to 8000 kPa. The width of the first insulating layer may be the width of the second trench.

상기 제 2 절연막의 증착 두께 및 제 1 전면식각 공정은 제 1 트랜치의 폭이 확보 되도록 한다.The deposition thickness of the second insulating layer and the first front surface etching process may ensure the width of the first trench.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 제조 공정을 나타낸 단면도 이다.1A to 1E are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하면, 반도체기판(100) 상부에 소정두께를 갖는 패드산화막(PAD Oxide)(102)을 성장시킨 후, 상기 패드 산화막(102)의 상부에 제 1 절연막(104)을 형성한다.Referring to FIG. 1A, after a pad oxide film 102 having a predetermined thickness is grown on a semiconductor substrate 100, a first insulating film 104 is formed on the pad oxide film 102.

이때, 제 1 절연막은 나이트라이드(Nitride)로 형성하여, 100 내지 8000 Å 정도로 두텁게 형성한다.At this time, the first insulating film is formed of nitride, and is thickly formed to about 100 to 8000 Å.

제 1 절연막(104) 상부에 마스크 공정(Non-Critical Mask)을 실시하기 위한 포토 마스크(106)를 형성하고, 포토 마스크(106)에 의해 노출된 제 1 절연막(104) 및 패드 산화막(102)을 광원으로 식각한다. 광원은 KrF 를 포함하여 일반적인 반도체 물질의 노광에 사용되는 광원을 이용하여 실시한다.A photomask 106 is formed on the first insulating film 104 to perform a non-critical mask, and the first insulating film 104 and the pad oxide film 102 exposed by the photomask 106 are formed. Is etched with a light source. The light source is implemented using a light source used for exposure of a general semiconductor material, including KrF.

이때, 식각되지 않고 남아있는 패드 산화막(102) 및 제 1 절연막(104)의 적층구조 간의 간격은 일정하되 조밀하지 않으며, 제 1 절연막(104) 폭은 후공정에서 제 2 트랜치의 폭이 된다.At this time, the gap between the stack structure of the pad oxide film 102 and the first insulating film 104 remaining unetched is constant but not dense, and the width of the first insulating film 104 becomes the width of the second trench in a later process.

도 1b는 도 1a의 다음 공정을 진행한 반도체 소자의 단면도 이다. 도 1b를 참조하면, 전체구조상부에 아모포스카본(a-C)을 증착하면 요철형태의 제 2 절연막(108)이 형성된다. 상기 제 2 절연막(108)의 폭은 후공정에서 제 1 트랜치의 폭이 되며, 제 2 절연막(108)의 증착두께를 조절하여 상기 제 1 트랜치 폭을 조절할 수 있다.FIG. 1B is a cross-sectional view of a semiconductor device having undergone the following process of FIG. 1A. Referring to FIG. 1B, when the amorphous carbon (a-C) is deposited on the entire structure, a second insulating layer 108 having a concave-convex shape is formed. The width of the second insulating layer 108 becomes the width of the first trench in a later process, and the width of the first trench may be adjusted by adjusting the deposition thickness of the second insulating layer 108.

본 발명에서는 일실시예로 제 1 절연막(104)의 물질을 나이트라이드, 제 2 절연막(106)의 물질을 산화막 또는 아모포스카본으로 설명하고 있을 뿐, 상기 제 1 절연막(104)과 제 2 절연막(106)의 구성물질은 서로 바뀔 수 있다.In the present invention, only the material of the first insulating film 104 is described as nitride, and the material of the second insulating film 106 is described as an oxide film or amorphous carbon, and the first insulating film 104 and the second insulating film are described. The components of 106 may be interchanged.

도 1c는 도 1b의 다음 공정을 진행한 반도체 소자의 단면도 이다. 도 1c를 참조하면, 제 1 절연막(104)을 식각타겟으로 제 1 전면식각공정을 실시한다. 그로인해, 제 1 절연막(104)의 상부가 노출되는 동시에 제 1 절연막(104) 및 패드산화막(102) 적층구조 사이의 반도체 기판(100)이 노출되어, 일부 제 2 절연막(108a)이 남게 된다.FIG. 1C is a cross-sectional view of a semiconductor device having undergone the following process of FIG. 1B. Referring to FIG. 1C, a first front surface etching process is performed using the first insulating film 104 as an etching target. As a result, the upper portion of the first insulating film 104 is exposed, and at the same time, the semiconductor substrate 100 between the first insulating film 104 and the pad oxide film 102 stacked structure is exposed, thereby leaving some second insulating films 108a. .

다음, 상기 반도체 기판(100)이 노출된 영역에 다시 식각공정을 실시하여 A' 깊이의 제 1 트랜치를 형성한다. Next, an etching process is performed again on the exposed region of the semiconductor substrate 100 to form a first trench of A 'depth.

도 1d는 도 1c의 다음 공정을 진행한 반도체 소자의 단면도 이다. 도 1d를 참조하면, 식각되지 않고 남아있는 제 1 절연막(104) 및 패드 산화막(102) 적층구조를 제거한 후, 일부 제 2 절연막(108a)을 베리어(Barrier)로 제 2 전면식각 공정을 실시한다.FIG. 1D is a cross-sectional view of a semiconductor device having undergone the following process of FIG. 1C. Referring to FIG. 1D, after the first structure of the first insulating film 104 and the pad oxide film 102 that are not etched are removed, a second front surface etching process is performed on the second insulating film 108a with a barrier. .

따라서, A' 깊이의 제 1 트랜치는 더욱 식각되어 A 깊이로 식각되는 동시에 B 깊이의 제 2 트랜치가 형성되어, 단한번의 마스크 공정으로, 깊이가 서로 다른 소자분리막(Differential Shallow Trench Isolation)을 형성할 수 있게 된다.Therefore, the first trench of depth A 'is further etched to be etched to depth A and at the same time a second trench of depth B is formed to form a differential shallow trench isolation with different depths in a single mask process. You can do it.

도 1e는 도 1d의 다음 공정을 진행한 반도체 소자의 단면도 이다. 도 1e를 참조하면, 제 2 전면식각 공정시 베리어로 사용된 일부 제 2 절연막(108a)을 제거한다.FIG. 1E is a cross-sectional view of a semiconductor device having undergone the following process of FIG. 1D. Referring to FIG. 1E, a portion of the second insulating layer 108a used as a barrier during the second front surface etching process is removed.

본 발명은 도면에 도시된 실시 예를 참고로 설명되었으나, 이는 예시적인 것에 불과하며, 본 기술분야의 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시 예가 가능하다는 점을 이해할 것이다.Although the present invention has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible.

따라서, 본 발명의 진정한 기술적 보호 범위는 첨부된 특허청구범위의 기술적 사상에 의해 정해져야 할 것이다.Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

본 발명은 단한번의 마스크 공정으로, 깊이가 서로 다르거나 같은 소자분리막(Differential Shallow Trench Isolation)을 형성함으로써, 후속공정시 각 층(Layer)의 중첩도(OverLayer)를 정밀하게 제어할 수 있어, 미세패턴의 형성에 용이하고 공정 난이도를 감소시키며 공정 진행 원가 절감 등의 부대 이익을 얻을 수 있다.According to the present invention, by forming a single isolation process (Differential Shallow Trench Isolation) having a different depth or the same depth, the OverLayer of each layer can be precisely controlled in a subsequent process. It is easy to form fine patterns, reduce process difficulty, and reduce side costs such as process progress.

Claims (5)

반도체기판 상부에 패드산화막 및 제 1 절연막을 순차적으로 형성하는 단계;Sequentially forming a pad oxide film and a first insulating film on the semiconductor substrate; 상기 제 1 절연막이 소정의 폭을 갖도록 식각하여 반도체 기판의 소정영역을 노출시키는 단계;Etching the first insulating layer to have a predetermined width to expose a predetermined region of the semiconductor substrate; 전체구조상부에 제 2 절연막을 형성한 후, 제 1 전면식각 공정을 실시하여 상기 제 1 절연막 측벽에 제 2 절연막을 잔류시키는 단계;Forming a second insulating film on the entire structure, and then performing a first front etching process to leave a second insulating film on the sidewalls of the first insulating film; 상기 제 1 절연막 및 제 2 절연막을 마스크로, 노출된 반도체 기판을 식각하여 제 1 깊이의 제 1 트랜치를 형성하는 단계;Etching the exposed semiconductor substrate using the first insulating film and the second insulating film as a mask to form a first trench having a first depth; 상기 제 1 절연막을 제거하여 반도체 기판을 노출시키는 단계;Removing the first insulating film to expose the semiconductor substrate; 상기 잔류된 제 2 절연막을 마스크로 제 2 전면식각 공정을 실시하여 상기 제 1 트렌치가 제 2 깊이가 되도록 하고, 상기 반도체 기판의 소정 영역에 제 1 트렌치 보다 얕은 깊이의 제 2 트렌치를 형성하는 단계; 및Performing a second front surface etching process using the remaining second insulating layer as a mask so that the first trench has a second depth, and forming a second trench having a depth smaller than the first trench in a predetermined region of the semiconductor substrate; ; And 상기 잔류된 제 2 절연막을 제거하는 단계;Removing the remaining second insulating film; 를 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제 1 절연막은 나이트라이드로 형성하며, 상기 제 2 절연막을 산화막 또는 아모포스카본으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.And the first insulating film is formed of nitride, and the second insulating film is formed of an oxide film or amorphous carbon. 제 1 항에 있어서,The method of claim 1, 상기 제 1 절연막은 100 내지 8000 Å 의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The first insulating film is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 100 to 8000 Å. 제 1 항에 있어서,The method of claim 1, 상기 제 1 절연막 폭은 상기 제 2 트랜치의 폭이 되도록 하는 반도체 소자의 제조 방법.And the first insulating film width is the width of the second trench. 제 1 항에 있어서,The method of claim 1, 상기 제 2 절연막의 증착 두께 및 제 1 전면식각 공정은 제 1 트랜치의 폭이 확보 되도록 하는 반도체 소자의 제조 방법.The deposition thickness of the second insulating layer and the first front surface etching process may allow the width of the first trench to be secured.
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