KR20110119896A - Method for fabricating nonvolatile memory device - Google Patents

Abstract

PURPOSE: A non-volatile memory apparatus manufacturing method is provided to arrange a polymer layer on the upper surface of a photosensitive pattern, thereby preventing a height loss of a photosensitive film during etching and sliming processes. CONSTITUTION: Stacks(N1-Nn) are repeatedly laminated on a substrate(10). A conductive film(11) and insulating film(12) are laminated on the stack. A photosensitive pattern(13) is arranged on the laminated stack. A capping layer is arranged on the upper part of the photosensitive pattern. The uppermost part of the stack is etched with the capping layer and photosensitive pattern as an etching barrier wall.

Description

Non-volatile memory device manufacturing method {METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a nonvolatile memory device having a vertical structure.

As a method of increasing device density when reducing design rules in flash memory, there is a method of using a 3D structure instead of a conventional floating gate.

On the other hand, a photo process used to manufacture a semiconductor device such as a flash memory device inevitably requires a photomask to form a pattern. Such photomasks are manufactured to selectively transmit light by forming various types of patterns of an integrated circuit to be made of a light blocking material that blocks light on a light transmissive substrate surface.

Thus, during the alignment exposure of the photo process, the desired pattern is accurately transferred to the photoresist. Such a mask fabrication method has a disadvantage in that the circuit line width of the semiconductor device is narrowed and thus the wavelength of the light source for exposure is shortened, so that the patterns formed on the photomasks interfere with each other to actually form a desired line width.

In other words, the linear pattern having a relatively fine line width is affected by the pattern density of the surroundings. Even if the pattern has a normal line width on the mask, when the pattern is formed on the photoresist by exposure in the actual photo process, diffraction or the like is performed. The size of the pattern is different due to the influence of. In particular, when the optical proximity effect of the mask pattern is not properly considered, pattern linewidth distortion occurs unlike lithography's original exposure intention, resulting in distortion of linewidth linearity, which adversely affects semiconductor device characteristics. Given.

In particular, in the prior art, since the slimming of the photoresist is not properly performed during the slimming etching after the mask process, it is difficult to form a pattern in a step shape and the LER (Line Edge Roughness) is not good.

That is, in the case of a pattern formed by a fine pattern forming method by a current lithography process, LER is generated due to the structure of a resist to be applied and the influence of mask error generated during mask drawing.

The LER affects subsequent processes, such as etching, which in turn negatively affects the electrical properties of the semiconductor device, in particular the threshold voltage. Therefore, a lot of research and process development is in progress to minimize the occurrence of such LER in the pattern formation.

Generally known LER occurs mainly in the chemically amplified resist type applied to KrF, ArF, 157nm, EUV or E-beam, which is caused by acid unevenness during exposure. It is mainly caused by the diffusion and chemical reaction of the resist with the matrix resin, and also by the non-uniform developing mechanism with the developer used.

In addition, the LER is generated by the selection of a light source and a mask material on a mask fabricated for forming a gradually smaller pattern, and the LER is transferred to the pattern during patterning using these masks. Therefore, it is important to select a photoacid generator to induce uniform diffusion of acid when using a chemically amplified resist, and to apply an acid which can minimize the effects on exposure and post exposure baking. Process conditions are required.

However, despite much research and process conditions improvement, the generation of LER is still indispensable in the process of applying chemically amplified resist, and how much LER can be minimized by using a later process It is a matter of interest. The occurrence of LER during such a fine pattern causes a big problem in the characteristics of the semiconductor device, so that stabilization of the process cannot be expected.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a nonvolatile memory device capable of resolving a shortage of photoresist during patterning.

According to an aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, the method comprising: repeatedly stacking a stack of conductive films and insulating films on a substrate; Forming a photoresist pattern on the stacked stack; Forming a capping layer on the photoresist pattern; Etching the top of the stack using the capping layer and the photoresist pattern as an etch barrier; A first step of reducing the line width of the photoresist pattern; A second step of forming a capping layer on the photoresist pattern having a reduced line width; And a third step of etching the uppermost stack using the capping layer and the photosensitive film pattern having reduced line width, and simultaneously etching the lower stack exposed by the immediately preceding step.

In particular, the first, second and third steps are repeated in one cycle until the substrate is exposed, and the stack is repeatedly stacked at least twice.

In addition, etching the top of the stack may include etching the insulating film; And etching the conductive film, wherein the etching of the insulating film includes any one gas selected from the group consisting of CF ₄ , CHF ₃ and CH ₂ F ₂ , or two or more mixed gases as an etching gas, Using He or Ar gas as an additive gas, and etching the conductive film may include using any single gas selected from the group of HBr, Cl ₂ and O ₂ or a mixed gas of HBr and Cl ₂ as an etching gas. It features.

In addition, the capping layer is formed of a polymer layer, and the forming of the capping layer may be performed by a plasma process using a C ₂ H ₄ or C ₂ H ₆ gas, and the capping layer may be a material having poor step coverage. It is characterized by forming.

The method may further include densifying the capping layer after forming the capping layer.

In addition, in the step of reducing the line width of the photoresist pattern, the capping layer is removed at the same time, the step of reducing the line width of the photoresist pattern is performed by applying a pressure of 30mTorr ~ 80mTorr and source power of 1200 ~ 1800Ｗ, It is characterized by advancing using a mixed gas of He and O ₂ or a mixed gas of He, O ₂ and N ₂ .

The method of manufacturing a nonvolatile memory device according to the embodiment of the present invention described above has an effect of preventing the height loss of the photoresist layer during the etching and slimming process by forming a polymer layer on the upper surface of the photoresist pattern.

Therefore, the photoresist layer may be formed to a minimum height when the photoresist pattern is formed, thereby securing stability of the photoresist pattern and preventing roughness of the line edge portion during patterning.

1A to 1G are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

1A to 1G are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

As shown in FIG. 1A, a stack N ₁ on which the conductive film 11 and the insulating film 12 are stacked is formed on the substrate 10. The conductive film 11 is for forming a memory cell, and is preferably formed of polysilicon. The insulating film 12 is for interlayer insulation of each memory cell, and is preferably formed of an oxide film.

Subsequently, the stack N ₁ on which the conductive film 11 and the insulating film 12 are stacked is repeatedly stacked to the desired layer Nn. The stack is repeatedly laminated with at least two layers, preferably eight layers.

Next, the photosensitive film pattern 13 is formed on the uppermost stack N _n . The photoresist pattern 13 is formed by coating a photoresist on the uppermost stack N _n and patterning the pattern region to be defined by exposure and development. At this time, it is preferable to form the photosensitive film by the photosensitive film pattern 13 using the I-Line exposure source. In addition, the thickness of the photoresist pattern 13 may be adjusted in consideration of a margin during multi-stack etching and slimming etching in which the conductive film and the insulating film are stacked. For example, a stack of 8 or more layers may be used. When laminated, it is desirable to form at least 50000 GPa.

As shown in FIG. 1B, a capping layer P ₁ is formed on the upper surface of the photoresist pattern 13. Since the capping layer P ₁ secures an etching margin of the photoresist pattern 13 during the subsequent etching process and protects the photoresist pattern 13 in the etching and slimming process, it prevents height loss of the photoresist pattern 13. In the photoresist pattern 13 is formed at a minimum height can be formed. The capping layer P ₁ is formed of a polymer layer, and for convenience of description, the capping layer P ₁ is hereinafter referred to as a 'polymer layer P ₁ '.

That is, the photoresist pattern 13 is formed to a minimum height in consideration of the polymer layer P ₁ to secure the stability of the photoresist pattern 13, and thus, the line edge roughness of the line edge portion becomes poor during patterning. Can be prevented.

The polymer layer P ₁ may be formed of a material having extremely poor step coverage so as to be formed only on the upper surface of the photoresist pattern 13. In order to form the polymer layer P ₁ , a plasma process using a C ₂ H ₄ or C ₂ H ₆ gas is performed. At this time, a small substrate bias is applied to the upper surface of the photoresist pattern 13 without etching the lower layer. It is desirable to create an environment in which the polymer layer P ₁ is deposited. In particular, it is possible to prevent the polymer layer P ₁ from being formed on the side surface of the photosensitive film pattern 13 due to the linearity of ions by applying only a substrate bias without applying source power.

Next, the polymer layer P ₁ is densified. At this time, the densification may proceed through etching gas treatment such as HBr gas.

The polymer layer P ₁ formed on the upper surface of the photoresist pattern 13 includes a polymer component having better etching resistance compared to the photoresist pattern 13, and thus, the height loss of the photoresist pattern 13 is reduced in subsequent etching and slimming processes. It can prevent.

As shown in FIG. 1C, the uppermost stack N _n is etched using the polymer layer P ₁ and the photoresist pattern 13 as an etch barrier. At this time, the etching of the stack is preferably divided into the etching of the insulating film 12 and the etching of the conductive film 11, respectively.

When the insulating film 12 is an oxide film, it is preferable to etch using an oxide film etching gas, and any single gas or two or more mixed gases selected from the group of CF ₄ , CHF _3, and CH ₂ F ₂ may be used as the oxide film etching gas. It is preferable to use. In addition, He or Ar gas is used as an insert gas.

In addition, when the conductive film 11 is polysilicon, it is preferable to etch using a silicon etching gas, and any single gas selected from the group of HBr, Cl ₂ and O ₂ or HBr and Cl ₂ as the silicon etching gas. It is preferable to use a mixed gas of.

As described above, the insulating film 11 and the conductive film 11 are etched using different etching gases, and thus, the lower insulating film is etched when the conductive film 11 is etched in the process of etching the uppermost stack N _n . Since it is not etched by the selectivity, it is possible to selectively etch only the conductive film 11.

As shown in FIG. 1D, a slimming process is performed. The line width of the photosensitive film pattern 13 is reduced by the slimming process. In particular, the upper layer of the photoresist pattern 13 may be protected by forming a polymer layer (P ₁ , see FIG. 1C) on the photoresist pattern 13 in FIG. 1B to prevent the upper loss of the photoresist pattern 13.

The slimming process is preferably performed by applying a pressure of 30mTorr to 80mTorr and a source power of 1200W to 1800W. In addition, in order to minimize the loss of the photoresist pattern 13, it is preferable not to apply a bias power. The slimming process is preferably performed using a mixed gas of He and O ₂ or a mixed gas of He, O ₂ and N ₂ .

In particular, since the photosensitive film pattern 13 may freely change the slimming width of the photosensitive film pattern 13 according to the slimming process time, the desired width may be obtained by adjusting the time.

The polymer layer P ₁ (see FIG. 1C) is removed with a slimming process that reduces the line width of the photosensitive film pattern 13.

As shown in FIG. 1E, the polymer layer P ₂ is formed on the upper surface of the photoresist pattern 13 having the reduced line width. The polymer layer P ₂ secures an etching margin of the photoresist pattern 13 during the subsequent etching process, and protects the photoresist pattern 13 in the etching and slimming process, thereby preventing the height loss of the photoresist pattern 13.

The polymer layer P ₂ may be formed of a material having extremely poor step coverage so as to be formed only on the upper surface of the photoresist pattern 13. A plasma process using a C ₂ H ₄ or C ₂ H ₆ gas is performed to form the polymer layer P ₂ , wherein a small substrate bias is applied to the upper surface of the photoresist pattern 13 without etching the lower layer. It is desirable to create an environment in which the polymer layer P ₂ is deposited. In particular, it is possible to prevent the polymer layer P ₂ from being formed on the side surface of the photosensitive film pattern 13 due to the linearity of ions by applying only a substrate bias without applying source power.

Next, the polymer layer P ₂ is densified. At this time, the densification may proceed through etching gas treatment such as HBr gas.

The polymer layer P ₂ formed on the upper surface of the photoresist pattern 13 includes a polymer component having better etching resistance compared to the photoresist pattern 13, and thus, the height loss of the photoresist pattern 13 is reduced in subsequent etching and slimming processes. It can prevent.

As illustrated in FIG. 1F, the uppermost stack N _n is etched using the polymer layer P ₂ and the photoresist pattern 13 having the reduced line width as an etch barrier, and the lower stack N _{n −1} exposed at the same time. Etch).

That is, the lower insulating film 12 exposed during the etching of the uppermost insulating film 12 is etched, and the lower conductive film 11 exposed when etching the uppermost conductive film 11 is etched. This is because the stacked stack of the conductive material 11 and the insulating film 12, which are the same material, is repeatedly stacked, and the bottom stack N _{n -1} is the same as the top stack N _n etched in FIG. 1C. Etched to width

Therefore, the bottom stack N _{n -1} is etched with a wider width than the top stack N _n .

The etching of the insulating film 12 and the conductive film 11 may proceed in the same process as in FIG. 1C.

When the insulating film 12 is an oxide film, it is preferable to etch using an oxide film etching gas, and any single gas or two or more mixed gases selected from the group of CF ₄ , CHF _3, and CH ₂ F ₂ may be used as the oxide film etching gas. It is preferable to use. In addition, He or Ar gas is used as an insert gas.

In addition, when the conductive film 11 is polysilicon, it is preferable to etch using a silicon etching gas, and any single gas selected from the group of HBr, Cl ₂ and O ₂ or HBr and Cl ₂ as the silicon etching gas. It is preferable to use a mixed gas of.

As shown in FIG. 1G, the slimming of FIG. 1D, the polymer layer formation of FIG. 1E, and the etching of FIG. 1F are repeatedly performed until the substrate 10 is exposed in one cycle to form a stepped structure.

That is, the width gradually increases from the uppermost stack N _n to form a vertical nonvolatile memory device having a stepped structure.

Although the technical spirit of the present invention has been described in detail according to the above embodiments, it should be noted that the above embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

10 substrate 11 conductive film
12 insulating film 13 photosensitive film pattern
N ₁ , N ₂ , ..., N _n : stack
P ₁ , P ₂ , ..., P _n : polymer layer

Claims (13)

Repeatedly stacking a stack of conductive films and insulating films stacked on a substrate;
Forming a photoresist pattern on the stacked stack;
Forming a capping layer on the photoresist pattern;
Etching the top of the stack using the capping layer and the photoresist pattern as an etch barrier;
A first step of reducing the line width of the photoresist pattern;
A second step of forming a capping layer on the photoresist pattern having a reduced line width; And
A third step of etching the uppermost stack using the capping layer and the photosensitive film pattern having reduced line width, and simultaneously etching the lower stack exposed by the immediately preceding step
Nonvolatile memory device manufacturing method comprising a.
The method of claim 1,
And repeating the first, second, and third steps in a single cycle until the substrate is exposed.
The method of claim 1,
And the stack is repeatedly stacked at least twice.
The method of claim 1,
Etching the top of the stack,
Etching the insulating film; And
And etching the conductive layer.
The method of claim 1,
Etching the insulating film,
A method of manufacturing a nonvolatile memory device using any one gas selected from the group of CF ₄ , CHF ₃ and CH ₂ F ₂ as an etching gas, and using He or Ar as an additive gas.
The method of claim 1,
Etching the conductive film,
A method of manufacturing a nonvolatile memory device using any one gas selected from the group of HBr, Cl ₂ , O ₂ or a mixed gas of HBr and Cl ₂ as an etching gas.
The method of claim 1,
And the capping layer is formed of a polymer layer.
The method of claim 1,
Forming the capping layer,
A method of manufacturing a nonvolatile memory device in which a plasma process using C ₂ H ₄ or C ₂ H ₆ gas is performed.
The method of claim 1,
And the capping layer is formed of a material having poor step coverage.
The method of claim 1,
After forming the capping layer,
And densifying the capping layer.
The method of claim 1,
In the step of reducing the line width of the photosensitive film pattern,
And the capping layer is removed at the same time.
The method of claim 1,
Reducing the line width of the photosensitive film pattern,
A method of forming a nonvolatile memory device in which a pressure of 30 mTorr to 80 mTorr and a source power of 1200 kW to 1800 kW are applied.
The method of claim 1,
Reducing the line width of the photosensitive film pattern,
A method of forming a nonvolatile memory device using a mixed gas of He and O ₂ or a mixed gas of He, O ₂ and N ₂ .

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