JP2001358061A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method for manufacturing a semiconductor device capable of suppressing a dimensional shift amount differences (a difference between a dimensional shift amount on a rough region having a relatively wide space and a dimensional shift amount on a dense region having a relatively narrow space) at an etching time to a small value. SOLUTION: Ions 7 are implanted in a resist pattern 4a for forming a wiring pattern. Here, as an ion species, argon is used, and the ion is implanted at 50 keV with 1×1016/cm2. A film thickness of the pattern 4a is contracted to about 334 nm of about 75% of 445 nm of the thickness before the ion implantation. A composition change of the pattern 4a is conduced to thereby improve the etching resistance to an etching treatment for a silicon nitride film 3 and a polysilicon layer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a resist pattern used for manufacturing a semiconductor integrated circuit element, particularly, a line width of 0.20 μm.
The present invention relates to a method of forming a processed pattern including a resist pattern forming step effective for obtaining high dimensional accuracy and overlay accuracy of a wiring pattern of m or less.

[0002]

2. Description of the Related Art At present, when a semiconductor integrated circuit (semiconductor device) is manufactured, a base layer such as a semiconductor substrate is selectively processed by etching or ion implantation. At this time, for the purpose of selectively protecting the processed portion of the underlayer, a composition sensitive to actinic rays such as ultraviolet rays, X-rays, and electron beams, a so-called photosensitive resist film (hereinafter, simply referred to as “resist”). ) Is formed on an underlayer.

The most commonly used method for forming a resist pattern is a g-line (wavelength = 436 nm) of a mercury lamp.
m), i-line (wavelength = 365 nm), UV irradiation using a reduction projection exposure apparatus (stepper) using a KrF excimer laser (wavelength = 248 nm) or an ArF excimer laser (wavelength = 193 nm) as a light source.

A photomask is mounted on this stepper to perform exposure. This photomask is called a reticle in which a circuit pattern is formed on a glass substrate with a shielding film such as chromium (Cr). At the time of exposure, precise positioning (overlapping) must be performed so that the mutual positional relationship between the photomask and the circuit pattern on the already formed substrate is correctly determined.

[0005] The pattern drawn on the photomask is reduced and transferred via a lens to a resist film applied to a semiconductor substrate. After that, a resist pattern can be formed by performing a developing process on the resist film.

In order to manufacture a semiconductor integrated circuit device,
This resist pattern forming step is usually required about 20 to 30 times.

In recent years, the integration and performance of semiconductor integrated circuits have been more and more advanced, and accordingly, finer circuit patterns have been required. DRAM (Dynami
c Random Access Memory) For example, in a 64-Mbit DRAM currently mass-produced, 0.20 to 0.1
A resist pattern having a line width of 8 μm is drawn, and in the photolithography process, KrF excimer laser light (λ = 248 nm) is most often used among ultraviolet rays. In the future, dimensional accuracy,
There is a demand for improved overlay accuracy.

By the way, a processed pattern such as a wiring pattern is obtained by etching a base film using a resist pattern as a mask. However, when a processed pattern is formed, it occurs during dry etching according to the space width adjacent to the processed pattern. It has recently been found that there is space width dependence (pattern density dependence) in which the dimension shift amount (dimension deviation from the resist pattern) is different.

That is, it has been found that the amount of dimensional shift on a sparse region having a relatively large space width is different from the amount of dimensional shift on a dense region having a relatively narrow space width on a processing pattern. Hereinafter, the difference between the dimensional shift amount on a sparse region with a relatively large space width and the dimensional shift amount on a dense region with a relatively small space width is abbreviated as “dimensional shift amount coarse / dense difference”.

This means that the dimensional accuracy of the processed pattern is deteriorated at the time of etching due to the space width dependency. However, the difference in dimensional shift amount has become a level that cannot be ignored as the pattern becomes finer. .

In particular, it has also been found that a large difference in the amount of dimensional shift during etching of a silicon oxide film or a silicon nitride film is large. However, the pitch of wiring and the distance between contact holes for pattern miniaturization and high density are becoming narrower, and in many cases, a self-aligned contact hole structure is adopted. Also, a device structure in which an insulating film such as a silicon oxide film or a silicon nitride film is laminated on a metal wiring film is essential.

Therefore, there is a need for a method of suppressing the difference in the size and the amount of dimensional shift caused by the etching of the insulating film.

FIGS. 48 to 51 are sectional views showing an example of a conventional wiring pattern forming method. Hereinafter, FIGS.
A conventional wiring pattern forming method will be described with reference to FIG.

First, as shown in FIG. 48, a polysilicon layer 2 having a thickness of 50 nm (500 °) is formed on a silicon substrate 1 and a silicon nitride film 3 is formed to a thickness of 165 nm (1650 nm).
After the formation of the film thickness of Å), a photoresist film 4 was applied and prebaked at 100 ° C. for 90 seconds. At this time,
The thickness of the photoresist film 4 is 585 nm (5850 °)
The number of revolutions during coating was adjusted so that

Next, as shown in FIG. 49, a reticle (photomask) on which wiring patterns of various pitches are drawn.
5 through a KrF excimer laser (wavelength 248n
m) Exposure was performed using a stepper using 6 as a light source.
The illumination condition was NA (numerical aperture) = 0.55, and an off-axis method using a ／ annular illumination aperture was applied.

Subsequently, a bake at 110 ° C. for 90 seconds (PE
B (Post Exposure Bake), and then developing with a 2.38% by weight aqueous solution of tetramethylammonium hydroxide (TMAH) for 60 seconds,
As shown in FIG. 50, a resist pattern 4a corresponding to the reticle is obtained.

Next, as shown in FIG. 51, using the resist pattern 4a as a mask, trifluoromethane (CH
F ₃ ), tetrafluoromethane (CF ₄ ), argon (A
r), a parallel plate type reactive ion etcher (RIE (Reactive Ion Etchin) using a mixed gas of oxygen (O ₂ )
g)), an etching process is performed on the nitride film 3 and the polysilicon layer 2 to obtain a wiring pattern (polysilicon pattern 2a, silicon nitride pattern 3a).

FIG. 52 is a graph showing a comparison result of a pattern size between a resist pattern and a processed pattern (laminated structure of a polysilicon layer and a silicon nitride film) obtained after etching. In FIG. 52, the dimension (Line Width) is plotted against the space width (Space) of each of the resist pattern and the processed pattern after etching with respect to the line width of the mask dimension of 0.24 μm.

FIG. 53 is a graph showing the space width dependence based on FIG. The dimension shift amount at the time of etching at the line width of 0.24 μm shown in FIG. 52 (CD (Criti
calDimension) Shift) depends on the width of the adjacent space. In FIG. 53, the dimensional shift amount density difference ΔCD0, which is the difference in the dimensional shift amount indicated by the isolated line pattern region having a sufficiently large space from the densest pattern region, is about 0.141 μm.

[0020]

As shown in FIG. 53, the dimensional shift of a line pattern in a sparse environment is large, and in order to finish an isolated line pattern as designed, the mask size must be reduced to the original design size. It is necessary to reduce the sizing. However, the smaller the mask dimension and the resulting resist pattern dimension, the narrower the process latitude such as exposure latitude and focus latitude (DOF (Depth of Focus)), so that the difference in dimensional shift amount generated during etching is large. Is not desirable.

Therefore, it is important to suppress the dimensional shift during dry etching, and in particular, to suppress the space width dependence of the dimensional shift (pattern sparse / dense dependency), that is, the difference between the dimensional shift and the density difference.

Further, as the pattern becomes finer,
When a resist pattern is formed on a base film having a large grain on the surface such as tungsten or aluminum, pattern dimensional accuracy deteriorates due to the influence of halation from the grain. Further, regarding the superimposition at the time of exposure, similarly, there is a problem that the accuracy is deteriorated due to the influence of the grains.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing a difference in dimensional shift amount during etching without affecting etching. I do.

[0024]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: (a) forming an etching object on a semiconductor substrate; and (b) forming an etching object on the etching object. Forming one resist;
(c) patterning the first resist to obtain a first resist pattern; and (d) performing ion implantation on the first resist pattern, wherein the ion implantation of the step (d) is performed. By injection, the first
The film thickness of the resist pattern shrinks, (e) the step
(c) performing the predetermined etching process on the object to be etched using the first resist pattern after execution as a mask to obtain a processed pattern, wherein the step (d) The thickness of the first resist pattern after the execution is the difference in the amount of dimensional deviation of the processed pattern from the first resist pattern, which occurs between a dense pattern portion and a sparse pattern portion in the processed pattern. The film thickness is set to a value less than a predetermined standard and satisfying a condition that does not hinder the predetermined etching process.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the object to be etched includes an actual object to be etched and an ion-blocking film.
(a) includes (a-1) forming the actual etching target on the semiconductor substrate, and (a-2) forming the ion blocking film on the actual etching target,
The ion implantation of the step (d) includes ion implantation from above the first resist pattern, and the ion blocking film is configured such that the ions implanted in the step (d) are implanted into the actual etching target. To block.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, the ion blocking film includes a silicon nitride film or a silicon oxynitride film, and the step (a-2) includes the step of: Forming the ion-blocking film using a CVD method.

According to a fourth aspect of the present invention, in the method for manufacturing a semiconductor device according to the second aspect, the ion blocking film includes an organic antireflection film.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the step (a) comprises the step of: (a-3) ion-implanting the organic antireflection film, which is the ion-blocking film. Further comprising the step of:

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to fifth aspects, the object to be etched includes first and second processing regions. The first resist pattern includes a pattern for an etching mask in the first processing region, and (f) forming a second resist on at least the second processing region after the execution of the step (d). And (g) patterning the second resist to obtain a second resist pattern for an etching mask in the second processing region, wherein the step (e) comprises: And performing the predetermined etching process using the second resist pattern as a mask in addition to the resist pattern.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the step (f) is performed by forming the second resist pattern on the entire surface of the object to be etched including the first resist pattern. Forming a resist of
The first resist pattern is formed by the composition change caused by the ion implantation in the step (d).
(g) Not substantially removed at runtime.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the ion implantation in the step (d) is performed from an obliquely upper direction with respect to a perpendicular to a surface on which the first resist pattern is formed. Includes performing ion implantation.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the object to be etched has an uneven shape on the surface, and (h) the step (b) is performed before the step (b) is performed. The method further includes the step of implanting ions into the etching target.

According to a tenth aspect of the present invention, there is provided the method of manufacturing a semiconductor device according to the ninth aspect, wherein the step (b) is performed after exposing the first resist through a reticle having a predetermined pattern. , By executing the development process,
A step of obtaining the first resist pattern.

According to an eleventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the ninth aspect, the object to be etched has a mark for superimposing a mask on a surface.

According to a twelfth aspect of the present invention, in the method for manufacturing a semiconductor device according to the eleventh aspect, the step (h) comprises the step of (h-
1) forming a third resist on the object to be etched; and (h-2) patterning the third resist so that an opening is formed on a mark forming region including the mark. Performing a third resist pattern, and (h-3) implanting ions into the mark forming region of the etching target using the third resist pattern as a mask.

According to a thirteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the ion implantation in the step (d) includes a plurality of partial ion implantations having different implantation energies.

According to a fourteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: (a) forming an etching object on a semiconductor substrate; and (b) forming a first resist on the etching object. (C) patterning the first resist to obtain a first resist pattern; and (d) performing a chemical reaction accelerating process for accelerating a decomposition reaction on the first resist pattern. And (e) for the first resist pattern,
Performing a curing process including one of ion implantation, electron beam irradiation, and ultraviolet irradiation, and the curing process of the step (e) causes the film thickness of the first resist pattern to shrink, f) The steps (c) to
(e) performing a predetermined etching process on the etching target using the first resist pattern after execution as a mask to obtain a processed pattern.

According to a fifteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourteenth aspect, the object to be etched includes first and second processing regions, and the first resist pattern is the first resist pattern. (G) forming a second resist on at least the second processed area after the step (e), and (h) forming the second resist. Patterning,
Obtaining a second resist pattern for an etching mask of the second processing region, wherein the step (f) comprises using the second resist pattern as a mask in addition to the first resist pattern, And performing a predetermined etching process.

The invention according to claim 16 is the method for manufacturing a semiconductor device according to claim 15, wherein (i) the method is executed before the step (f) and after the step (h), and at least the second method Performing a chemical reaction accelerating process for accelerating a decomposition reaction on the resist pattern; and (j) executed before the step (f) and after the step (h), at least for the second resist pattern. Performing the curing process.

According to a seventeenth aspect of the present invention, in the method for manufacturing a semiconductor device according to any one of the fourteenth to sixteenth aspects, the chemical reaction accelerating process is performed by subjecting the object to exposure and heat treatment. At least one of them is included.

The invention of claim 18 is characterized in that (a) forming an etching object having the first and second processing regions on a semiconductor substrate; and (b) applying a first resist to the etching object. Forming; (c) patterning the first resist to obtain a first resist pattern on the first processing region; and (d) forming the first resist pattern.
Performing a curing process including one of ion implantation, electron beam irradiation, and ultraviolet irradiation on the resist pattern, and the curing process of the step (d), the first resist pattern The film thickness shrinks, (e) forming a second resist on at least the second processing area after the step (d), and (f) patterning the second resist, (G) obtaining a second resist pattern for an etching mask in a second processing region.
And performing a predetermined etching process on the etching target using the second resist pattern as a mask to obtain a processed pattern.

[0042]

BEST MODE FOR CARRYING OUT THE INVENTION << First Embodiment >><Principle> As a method of suppressing a difference in dimensional shift caused by etching of an insulating film, we have conducted intensive studies and found that the thickness of a resist pattern is large. It was found that the thinner the thickness, the smaller the difference in the dimensional shift amount of the insulating film. Therefore, it is desirable to form a resist pattern having a minimum thickness required as a mask for dry etching.

1 to 4 are cross-sectional views showing a wiring pattern forming method according to the principle of the present invention. Hereinafter, a method of forming a wiring pattern will be described with reference to these drawings.

First, as shown in FIG.
The polysilicon layer 2 has a thickness of 50 nm (500 °), and the silicon nitride film 3 has a thickness of 165 nm (1650 °).
After the formation of the film thickness of Å), a photoresist film 4 was applied on the silicon nitride film 3 and prebaked at 100 ° C. for 90 seconds. At this time, the thickness of the photoresist film 4 is 445.
The number of revolutions at the time of coating was adjusted to be nm (4450 °).

Next, as shown in FIG. 2, exposure was performed using a stepper having a KrF excimer laser 6 as a light source through a reticle 5 on which wiring patterns of various pitches were drawn. The illumination condition was NA = 0.55, and an off-axis method using a 2/3 annular illumination aperture was applied.

Subsequently, a bake at 110 ° C. for 90 seconds (PE
After performing B), development is performed for 60 seconds using a 2.38% by weight aqueous solution of tetramethylammonium hydroxide (TMAH) to obtain a resist pattern 4a corresponding to the reticle as shown in FIG.

Next, using the resist pattern 4a as a mask, C
Using a mixed gas of HF ₃ , CF ₄ , Ar, and O ₂ , an etching process is performed on the nitride film 3 and the polysilicon layer 2 which are the objects to be etched by parallel plate RIE. (Polysilicon pattern 2a, silicon nitride pattern 3a) are obtained.

The above-described method is the same as the conventional pattern forming method shown in FIGS. 48 to 51, except for the thickness of the photoresist film 4.

FIG. 5 shows the pattern dimensions of the resist pattern formed by the wiring pattern forming method shown in FIGS. 1 to 4 and the processed pattern after etching (wiring pattern (laminated structure of polysilicon layer and silicon nitride film)). 6 is a graph showing the comparison results of FIG. In FIG. 5, the mask dimension is 0.24 μm.
Space width (Space) of each resist pattern and processed pattern after etching for line pattern
Is plotted against the dimension (Line Width).

FIG. 6 is a graph showing the space width dependency based on FIG. In FIG. 6, a dimension shift amount (CD Shift) at the time of etching in a 0.24 μm line pattern is shown.
Shows the dependence on the adjacent space width.

In FIG. 6, L0 indicates the case where the thickness of the resist pattern is 585 nm, and L1 indicates the case where the thickness of the resist pattern is 445 nm. As shown in FIG. 6, the dimensional shift amount density difference ΔCD1 indicated by an isolated line pattern having a sufficiently large space from the densest pattern when the resist pattern film thickness is 445 nm is 0.079 μm.
The thickness of the resist pattern shown in the conventional example is 585n.
0.141μ of the dimensional shift amount ΔCD0 in the case of m
It can be seen that it is dramatically smaller than m.

Table 1 shows that after etching, 0.40 μm, 0.
A line width dimension (resist dimension) of a resist pattern for obtaining isolated lines having a line width of 35 μm and 0.30 μm, and respective resist dimensions (0.14, 0.04
8, 0.06, 0 (μm)) is shown.

[0053]

[Table 1]

For example, in order to obtain a processed pattern having a finished dimension of a line width of 0.30 μm after etching, in a process with a resist film thickness of 585 nm (dimension shift amount difference of about 0.14 μm), the resist dimension is 0.16 μm.
Is required, and a focus margin of 0.33 μm is required to obtain it.

Similarly, in order to obtain a processed pattern having a finished dimension with a line width of 0.30 μm after etching, in a process with a resist film thickness of 445 nm (the difference in dimensional shift amount is about 0.08), a resist of 0.22 μm is used. It is necessary to form a pattern, and in order to obtain it, the focus latitude is 0.
It is 62 μm, which indicates that it is advantageous to make the resist film thickness at which the etching dimension shift is small smaller.

Therefore, the finished dimension = 0.30 μm
When the required focus latitude is 0.60 or more, it is necessary to set the dimensional shift amount density difference to 0.08 μm or less from Table 1. When this “0.08 μm” is a predetermined reference, the film thickness Is 0.079 μm, which is less than a predetermined standard.

Further, although a resist pattern having a thickness of 370 nm was tested, it was found that the resist pattern fell off during dry etching, and the resist pattern was insufficient in thickness as an etching mask.

From these results, there is an optimum resist film thickness that minimizes the space width dependence of the dimensional shift amount during etching (difference in dimensional shift amount density difference), and the resist can be used as long as it does not interfere with the etching mask. It was found that thinning was effective.

<Method> FIGS. 7 to 11 are sectional views showing a wiring pattern forming method according to the first embodiment of the present invention. Hereinafter, the processing procedure of the first embodiment will be described with reference to these drawings.

The steps shown in FIGS. 7 to 9 are performed in the same manner as the steps shown in FIGS.

Then, as shown in FIG. 10, ions 7 were implanted into the resist pattern 4a. Here, argon is used as an ion species, and 1 × at 50 keV.
Ion implantation is performed at 10 ¹⁶ / cm ² . By this ion implantation, the film thickness of the resist pattern 4a becomes 7
By shrinking to about 334 nm of about 5% and changing the composition of the resist pattern 4a, the etching resistance to the etching process for the silicon nitride film 3 and the polysilicon layer 2 is improved.

Next, as shown in FIG. 11, using the resist pattern 4a as a mask, CHF ₃ , CF ₄ , Ar, O ₂
The nitride film 3 and the polysilicon layer 2 are subjected to an etching process by a parallel plate type RIE using the mixed gas described above to obtain a desired wiring pattern (polysilicon pattern 2a and silicon nitride pattern 3a).

At this time, since the etching resistance of the resist pattern 4a to the etching process for the silicon nitride film 3 and the polysilicon layer 2 is improved by ion implantation, even if the resist pattern 4a has a film thickness of about 334 nm, the etching mask is used. Function without any trouble.

As one of the conditions that do not hinder the etching, there is a condition that the vertical portion of the resist pattern (with respect to the surface on which the object to be etched is formed) is not lost during the etching, that is, the condition that the resist pattern does not drop off. is there.

FIGS. 54 to 56 are cross-sectional views for explaining the shoulder drop phenomenon of the resist pattern. As shown in FIG. 54, when the etching target 32 formed on the base substrate 31 is subjected to the etching process with the resist pattern 33 having the pattern width W1 having the insufficient film thickness, the etching process progresses, and as shown in FIG. As shown in FIG. 56, both shoulder portions (edge portions) of the resist pattern 33 are cut off, and thereafter, as shown in FIG. 56, the vertical portion disappears and shoulder drop occurs. When the etching process is performed in a state where the shoulder drop occurs, the resist pattern 33 having a pattern width W2 smaller than the pattern width W1 is formed.
Is used as a mask, and the finished dimensions of the etching target 32 by the etching process become unstable.

However, the ion-implanted resist pattern 4a has improved etching resistance, and does not drop off during the etching process even when the film thickness is 334 nm. Satisfies conditions that do not hinder the etching process.

FIG. 12 is a graph showing the space width dependency. FIG. 12 shows the dependence of the dimensional shift amount on the adjacent space width in the processed pattern (laminated structure of the polysilicon layer and the silicon nitride film) at the time of etching in the line pattern of 0.24 μm.

In FIG. 12, L0 indicates the case where the thickness of the resist pattern is 585 nm, L1 indicates the case where the thickness of the resist pattern is 445 nm, and L2 indicates the case where the thickness of the resist pattern is 3 nm.
Each shows a case where a resist pattern of 34 nm and ion-implanted is formed.

As shown in FIG. 12, the difference in the dimensional shift amount of the isolated line pattern having a sufficiently large space from the densest pattern when the resist pattern film thickness is 334 nm is 0.059 μm. It has been found that the difference is further reduced.

As described above, according to the wiring pattern forming method of the first embodiment, the ion implantation process shown in FIG.
The film thickness of the resist pattern 4a is set to a value which is not more than a predetermined reference which greatly improves the difference in dimensional shift amount between the density and the density, and which does not hinder the etching process for the polysilicon layer 2 and the silicon nitride film 3. Satisfactory film thickness (334n
m), the wiring pattern can be obtained with high dimensional accuracy by etching using the resist pattern 4a shown in FIG. 11 as a mask, even if the wiring pattern has a relatively large difference in density.

In Table 1, the finished dimension = 0.35 μm
If the required focus tolerance at m is 0.70 or more,
From Table 1, it is necessary that the dimensional shift amount density difference be 0.06 μm or less. When this “0.06 μm” is a predetermined reference, the dimensional shift amount density difference 0.059 μm of the resist pattern having a film thickness of 334 nm is obtained. It is below a predetermined standard.

<Another Effect of Ion Implantation> As shown in FIG.
Although roughness (concavity and convexity) is seen in e, when ion implantation is performed under the conditions of 50 keV and 1 × 10 ¹⁶ / cm ² using argon as an ion species, the roughness of the edge 4 e is reduced as shown in FIG. A resist pattern 4a having good linearity can be obtained.

As pattern miniaturization progresses more and more, edge roughness becomes a cause of deterioration of dimensional accuracy, and an effect of improving dimensional accuracy of resist pattern 4a can be obtained by ion implantation. Was.

<< Embodiment 2 >> FIGS. 15 to 20 are sectional views showing a wiring pattern forming method according to Embodiment 2 of the present invention. Hereinafter, the processing procedure of the second embodiment will be described with reference to these drawings.

First, as shown in FIG. 15, a polysilicon layer 2 is formed on a silicon substrate 1 to a thickness of 50 nm, a silicon nitride film 3 is formed to a thickness of 165 nm, and then a plasma CVD method is used. A silicon nitride oxide (SiON) film 8 having a thickness of 24.5 nm is formed. The silicon oxynitride film 8 is formed with a uniform thickness by the plasma CVD method without being affected by the step of the base.

Thereafter, a photoresist film 4 is applied on the silicon oxynitride film 8, and as shown in FIGS.
A resist pattern 4a in which ions are implanted is obtained in the same flow as the steps shown in FIGS. 7 to 10 of the first embodiment.

The silicon oxynitride film 8 is an antireflection film (BARC; Bottom Anti-Reflecti) at the time of exposure (step of FIG. 17).
ve Coating), and furthermore, protection for preventing injection into the actual etching target (polysilicon layer 2) existing below the silicon oxynitride film 8 at the time of ion implantation (step of FIG. 19). It also functions as a membrane (ion blocking membrane). Since the silicon nitride film 3 itself also functions as an ion blocking film, if the silicon nitride film 3 has a thickness sufficient to block ions, it acts as an ion blocking film. The silicon oxynitride film 8 becomes unnecessary.

Finally, as shown in FIG.
CHF using turn 4a as a mask _Three, CF_Four, Ar, O
_TwoFilm 3 by parallel plate RIE using a mixed gas of
And the polysilicon layer 2 are etched,
A desired wiring pattern (polysilicon pattern 2a, silicon pattern
Con nitride pattern 3a and silicon nitride oxide pattern 8
Obtain a).

Here, instead of the silicon oxynitride film 8 formed in the step of FIG.
After that, a resist film is applied,
20 to form a wiring pattern. Like the silicon oxynitride film 8, the organic BARC film also functions as a protective film (ion blocking film) against ion implantation into an actual etching target.

The organic BARC film has a characteristic that it is formed thin above the step and thicker below the step. For example,
Organic BAR so that the underlayer has a thickness of 80 nm in the flat part
When the C film is applied, only 20 nm is formed at the upper part of the step and 100 nm is formed at the lower part of the step, and a film thickness difference of 80 nm occurs between the upper part of the step and the lower part of the step.

When an organic BARC film is used, the film thickness of the organic BARC film shrinks during the ion implantation in the step of FIG. 19, but since the film thickness shrinks at a constant rate, for example, the film shrinks by 50%. Assuming that, in the above-described example, the thickness is 10 nm above the step and 50 nm below the step, and the film thickness difference is reduced to 40 nm.

Therefore, when a real device having a local step is formed on the silicon substrate 1, the difference in the thickness of the organic BARC film at the step becomes small, and the organic BAR is formed.
The effect of reducing the non-uniformity of the dimension shift amount during etching caused by the non-uniform thickness of the C film can be obtained by ion implantation.

<< Third Embodiment >> FIGS. 21 to 27 are sectional views showing a wiring pattern forming method according to a third embodiment of the present invention. Hereinafter, the processing procedure of the third embodiment will be described with reference to these drawings.

First, as shown in FIG. 21, a polysilicon layer 2 is formed on a silicon substrate 1 with a thickness of 50 nm, a silicon nitride film 3 is formed on a silicon nitride film 3 with a thickness of 165 nm. An organic BARC film 11 is formed with a thickness of 80 nm.

Next, as shown in FIG.
Ion implantation is performed from above the film 11. At this time, organic BA
The thickness of the RC film 11 shrinks, and the organic BARC film 1 at the step portion of the device built in the silicon substrate 1
Effectively, the non-uniformity of the film thickness of No. 1 is reduced.

Subsequently, as shown in FIGS. 23 to 27, the wiring patterns (polysilicon pattern 2a, silicon nitride pattern 3a and organic BARC) are passed through the same flow as the steps shown in FIGS. Pattern 11a)
Is formed. Here, as shown in FIG. 26, when the ion implantation is performed again on the formed resist pattern 4a, the dry etching resistance of the resist pattern 4a is improved and the thickness of the resist pattern 4a is reduced as in the first embodiment. Effectively functions to reduce the difference in the amount of dimensional shift during etching accompanying the above.

<< Fourth Preferred Embodiment >> FIGS. 28 to 35 are sectional views showing a wiring pattern forming method according to a fourth preferred embodiment of the present invention. FIGS. 28 to 35 show, as an example, an example of application to a bit line of a DRAM as to a pattern formation method in which a pattern that is difficult to form simultaneously is divided into two photolithographic processes. In this step, 0.1% of the memory cell portion is used.
Fine line pattern of less than μm, 0.20 in peripheral circuit
The formation of a space pattern of μm or less is required. Hereinafter, the processing procedure of the fourth embodiment will be described with reference to these drawings.

First, as shown in FIG. 28, a silicon oxide film 9 is formed on a silicon substrate 1 and then a metal film 1 for wiring is formed.
After forming 0, a photoresist film 4 is applied on the metal film 10 and prebaked at 100 ° C. for 60 seconds. At this time, the rotation speed at the time of coating was adjusted so that the thickness of the photoresist film 4 was 585 nm.

Next, as shown in FIG. 29, the wiring pattern (L
(Line width) / S (space width) = 0.16 μm / 0.
Reticle with only 22μm) drawn (photomask)
5a via a KrF excimer laser (wavelength 248n
m) Exposure was performed using a stepper using 6 as a light source.
The illumination condition was NA = 0.55, and an off-axis method using a 2/3 annular illumination aperture was applied.

Subsequently, as shown in FIG. 30, after baking (PEB) at 110 ° C. for 60 seconds, 2.38% by weight of tetramethylammonium hydroxide (TMAH) was used.
By performing development for 60 seconds using the aqueous solution, a resist pattern 4b having a line width of 0.13 μm is obtained.

Before the photoresist film 4 is applied, an inorganic BARC film (silicon oxynitride film 8) or an organic BARC film is formed on the metal film 10 as an antireflection film as in the second and third embodiments. May be formed.

Next, as shown in FIG. 31, ions 7 were implanted into the resist pattern 4b under the conditions of 50 keV and 1 × 10 ¹⁶ / cm ^{2 using} argon as an ion species.

When ions are implanted into the resist pattern 4b, the pattern shrinks as shown in JP-A-4-127518, and the resist pattern having a line width of 0.13 μm is reduced to 0.10 μm. In order to obtain a 0.10 μm line pattern under the same illumination conditions and resist process conditions, the process margins such as the exposure latitude and the focus latitude are narrow, and the width is small. Difficult. Thus, by performing ion implantation on the resist pattern and utilizing the pattern shrinkage, it is possible to obtain a fine line pattern exceeding the limit of a normal pattern forming method.

The composition of the resist pattern 4b is changed by ion implantation to a composition different from that before the ion implantation.

However, in the exposure step shown in FIG.
If a resist pattern for the peripheral circuit region A2, which is a processing region of the above, is also formed at the same time, the space portion of the peripheral circuit pattern undesirably expands during ion implantation. In order to obtain a pattern having the desired dimensions, FIG.
At the time of forming the resist pattern 4b in the exposure step indicated by 9, a resist pattern for a peripheral circuit in a narrow space must be formed in advance, which is very difficult.

Then, after a resist pattern 4b is obtained through the process of FIG. 31, as shown in FIG. 32, a photoresist film 14b is formed on the entire surface of the metal film 10 including the memory cell formation region A1 and the peripheral circuit region A2. Is applied and formed. That is, the photoresist film 14 is formed again on the resist pattern 4b in the memory cell formation region A1. At this time, the application conditions are the same as when the first photoresist film 4 is formed.

Next, as shown in FIG. 33, a KrF excimer laser (wavelength: 248 nm) 6 is applied via a reticle (photomask) 5b drawn corresponding to the peripheral circuit area A2 except the memory cell formation area A1. Exposure is performed using a stepper as a light source. The off-axis method using a 2/3 annular illumination aperture with NA = 0.55 was applied as the illumination condition.

Subsequently, as shown in FIG. 34, after baking (PEB) at 110 ° C. for 60 seconds, 2.38% by weight of tetramethylammonium hydroxide (TMAH) was used.
By performing development for 60 seconds using an aqueous solution, a resist pattern 14b having a line width of 0.50 μm and a space width of 0.2 μm is obtained.

Since the resist pattern 4b is converted into a composition completely different from that of the photoresist film 14 by ion implantation, it is not affected by the exposure in the step shown in FIG. It is not removed and is reproduced exactly.

Then, as shown in FIG. 35, using the resist pattern 4b and the resist pattern 14c as a mask, the metal film 10 is etched to obtain a desired wiring pattern (metal pattern 10a).

According to the method of the fourth embodiment, a dense resist pattern 4a having a line width smaller than the mask size is formed on the memory cell pattern in the memory cell forming area A1 where a pattern with a constant pitch is drawn. A relatively sparse resist pattern 14b can be formed over the circuit region A2 without deterioration in accuracy, and wiring patterns having different densities can be formed accurately.

<< Fifth Preferred Embodiment >> FIGS. 36 to 40 and FIG. 42 are sectional views showing a wiring pattern forming method according to a fifth preferred embodiment of the present invention. FIG. 41 is an explanatory view showing a reticle on which a pattern in a DRAM capacitor forming step is drawn. In the fifth embodiment, it is assumed that a capacitor of a DRAM is formed. Hereinafter, the processing procedure of the fifth embodiment will be described with reference to these drawings.

First, as shown in FIG. 36, a polysilicon layer 2 is formed on a silicon substrate 1 to a thickness of 50 nm, and then a silicon oxide film 13 is formed to a thickness of 1500 nm.
A photoresist film 4 was applied on the silicon oxide film 13 and prebaked at 100 ° C. for 60 seconds. At this time,
The number of revolutions during coating was adjusted so that the thickness of the photoresist film 4 was 880 nm.

Next, as shown in FIG. 37, a KrF excimer laser (wavelength: 248 nm) 6 is used as a light source through a reticle (photomask) 5m (see FIG. 41) on which a pattern of a DRAM capacitor forming step is drawn (see FIG. 41). Exposure was performed using a stepper. The lighting condition is NA = 0.55
An off-axis method using a 2/3 annular illumination aperture was applied.

Subsequently, as shown in FIG. 38, after baking (PEB) at 110 ° C. for 90 seconds, 2.38% by weight of tetramethylammonium hydroxide (TMAH) was used.
By performing development for 60 seconds using the aqueous solution, a resist pattern 4m for the capacitor corresponding to the reticle is obtained.

Next, as shown in FIG. 39, ions 7 were implanted into the resist pattern 4m under the conditions of 50 keV and 1 × 10 ¹⁶ / cm ^{2 using} argon as an ion species. At this time, as shown in FIG. 42, ion implantation is performed from a direction inclined from the perpendicular VL of the wafer (the surface on which the resist pattern 4m is formed) by 15 to 20 °. By this method, FIG.
As shown in FIG. 2, most of the ions 7 are blocked by the surface and side surfaces of the resist pattern 4m, so that it is possible to prevent the ions from being directly implanted into the silicon oxide film 13 as the underlying substrate. The optimum inclination angle in the implantation of the ions 7 varies depending on the line width and pitch (line width + space width) of the resist pattern 4m and the film thickness of the resist pattern 4m.

4 m of resist pattern obtained after development
In (2), the pattern shrinkage occurred due to the ion implantation, and the line width of the remaining portion of the resist was reduced from 0.17 μm to 0.11 μm.

Then, as shown in FIG. 40, the silicon oxide film 13 and the polysilicon layer 2 are etched using the resist pattern 4m as a mask to form a wiring pattern (oxide film pattern 13a and polysilicon pattern 2a). obtain.

In the DRAM capacitor formation step, it is desirable to form a large opening pattern in order to obtain a large capacitance. By applying this method, it is possible to relatively easily enlarge the space width due to shrinking of the line width, so that it is effective. It is.

The same effect can be obtained by applying this method for the purpose of forming a large opening pattern in the self-aligned contact hole forming step of the DRAM.

<< Embodiment 6 >> The surface of aluminum or tungsten is highly uneven due to grains, and this often affects the formation of a resist pattern.

In particular, when aluminum is formed by a sputtering method, it is required to have a filling property in a contact hole formed for connection with a lower layer, but the filling property decreases as the contact hole size becomes smaller. Therefore, as a method of improving the embedding characteristics, there is a method of reflowing by heating after sputtering aluminum, or a method of sputtering while heating the substrate, but the size of each grain is larger than that of an aluminum film formed by a normal sputtering method. growing. Therefore, when a resist pattern is formed on a base substrate made of such an aluminum layer, the shape of the resist pattern is deteriorated due to the influence of light reflected from the grains, and the dimensional uniformity of the resist pattern is reduced.

FIGS. 43 to 45 are explanatory diagrams schematically showing the appearance of grains on various aluminum surfaces. FIG.
FIG. 44 is an explanatory diagram schematically showing a surface shape of an aluminum film formed by a normal sputtering method, and FIG. 44 schematically shows a surface shape of an aluminum film formed by sputtering while heating. Then, when the ion 7 is implanted into the base substrate under the conditions of 50 keV and 1 × 10 ¹⁶ / cm ^{2 using} argon as an ion species before the resist coating, as shown in FIG. 45,
The unevenness due to the grains on the substrate surface is reduced. The method of forming a wiring pattern according to the sixth embodiment is intended to alleviate the uneven shape.

FIG. 46 is a sectional view showing a characteristic portion of the wiring pattern forming method according to the sixth embodiment of the present invention.

As shown in the figure, a base substrate having a laminated structure of a silicon substrate 1, a silicon oxide film 15, and an aluminum layer 16 was subjected to 50 ke with argon as an ion species.
V is implanted under the conditions of 1 × 10 ¹⁶ / cm ² . After that, a wiring pattern is formed by a normal flow as shown in FIGS. 1 to 4 described in the first embodiment.

According to the wiring pattern forming method of the sixth embodiment, ions are implanted in advance into aluminum layer 16 having a grain on the surface.
Therefore, it is possible to suppress the deterioration of the shape of the resist pattern due to the influence of the reflected light from the grains, and to obtain the effect of improving the dimensional accuracy of the resist pattern.

<< Embodiment 7 >> As described above, since the surface of tungsten or aluminum has a severe unevenness due to grains, when forming a resist pattern on such an undersubstrate, the exposure step is superimposed. The accuracy and the measurement accuracy of the overlay inspection after pattern formation also deteriorate. For example, when the measurement is performed at the overlay inspection mark (two central square portions) shown in FIGS.
For a normal aluminum film (see FIG. 43), the measurement accuracy (3
σ) is about 20 nm, but in the aluminum film (FIG. 44) obtained by sputtering while heating, the measurement accuracy (3σ) deteriorated to about 100 nm.

Therefore, before application of the resist, 50 keV and 1 × 10 ¹⁶ / argon were used as an ion species with respect to the underlying substrate.
When ion implantation is performed under the condition of cm ² , as shown in FIG. 45, unevenness due to grains on the substrate surface is reduced.
Deterioration of overlay accuracy can be suppressed, and measurement accuracy (3σ) can be improved to about 50 nm.

FIG. 47 is a sectional view showing a characteristic portion of the wiring pattern forming method according to the seventh embodiment of the present invention.

As shown in the figure, an inspection mark (not shown) of the aluminum layer 16 is formed on a base substrate having a laminated structure of the silicon substrate 1, the silicon oxide film 15, and the aluminum layer 16.
A resist pattern 17 having an opening 18 is formed only on the mark forming area 19 including the photolithography using photolithography or the like, and ions 7 are implanted only on the mark forming area 19 of the aluminum layer 16 using the resist pattern 17 as a mask. afterwards,
A wiring pattern is formed by a normal flow as shown in FIGS. 1 to 4 described in the first embodiment.

As described above, in the seventh embodiment, when the underlying substrate is made of tungsten or aluminum, after finishing the processing of the tungsten or aluminum film, the overlay and the mark for overlay inspection formed on this film are formed. Ions are implanted only through the resist pattern 17 having the opening 18 only on the mark forming region 19 to be formed.

As a result, it is effective as a method of preventing the deterioration of the overlay accuracy at the time of photolithography in the next step by reducing the grain of the mark portion. Further, areas other than the mark forming area are reliably protected by the resist pattern 17 so as not to be adversely affected by the ion implantation.

<< Eighth Embodiment >><Premise> FIGS. 57 to 61 are cross-sectional views showing a gate pattern forming step which is one of the wiring pattern forming methods on which the eighth embodiment of the present invention is based. . Hereinafter, the processing procedure will be described with reference to these drawings.

First, as shown in FIG. 57, a silicon oxide film 12 is formed on a silicon substrate 1 to a thickness of 15 nm (150 °), and then a polysilicon layer 2 is formed to a thickness of 100 nm (1000 °).
Å) and the silicon oxide film 21 is further
After forming the silicon oxynitride film 8 to a thickness of 48 nm (480 Å), the photoresist film 4 is applied on the silicon oxynitride film 8 and
For 90 seconds. At this time, the rotation speed at the time of coating is adjusted so that the thickness of the photoresist film 4 becomes 585 nm (5850 °).

Next, as shown in FIG. 58, exposure was performed using a KrF excimer laser 6 as a light source through a reticle 5 on which a wiring pattern was drawn. The illumination condition was NA = 0.65, and the off-axis method using a 2/3 annular illumination aperture was applied.

Subsequently, a bake at 110 ° C. for 90 seconds (PE
After performing B), development is performed for 60 seconds using a 2.38% by weight aqueous solution of tetramethylammonium hydroxide (TMAH) to obtain a resist pattern 4a corresponding to the reticle as shown in FIG.

Then, as shown in FIG. 60, ions 7 were implanted into the resist pattern 4a. Here, ion implantation is performed at 1 × 10 ¹⁶ / cm ² (dose) at 50 keV (implantation energy) using argon as an ion species. As described above, the thickness of the resist pattern 4a is reduced by the ion implantation,
The etching resistance to the etching process for the silicon oxide film 21 and the silicon oxynitride film 8 is improved.

Next, as shown in FIG. 61, the silicon nitride oxide film 8 and the silicon oxide film 21 are etched using the resist pattern 4a as a mask. The polysilicon layer 2 is etched using the silicon nitride oxide film 8 and the silicon oxide film 21 as a mask to form a desired wiring pattern (polysilicon pattern 2).
Obtain a). The etching process may be performed on the silicon oxynitride film 8, the silicon oxide film 21, and the polysilicon layer 2 collectively using the resist pattern 4a as a mask.

At this time, the etching resistance of the resist pattern 4a to the etching process for the silicon oxide film 21 and the silicon oxynitride film 8 is improved by ion implantation, so that the resist pattern 4a has a thickness shown in FIG. It functions as a mask for etching even if it shrinks.

However, when ions are implanted into the resist pattern 4a, the formation of a hardened layer proceeds from the surface of the resist pattern 4a.
In addition, there is a problem in that gas generated from inside the resist pattern 4a during the dry etching process on the silicon oxide film 21 is trapped in the resist pattern 4a, and thereafter, there is a risk that the resist pattern 4a may burst. For this reason, the process window, which is the allowable range of the process conditions satisfying the dry etching specifications, is restricted.

In general, in a positive photoresist film, a chemical reaction occurs in a portion irradiated with light, and a reaction product is released.
In the novolak-quinonediazide resist widely used for g-line and i-line, nitrogen is used. In the chemically amplified resist used for KrF, compounds such as carbon dioxide, butene, and ethanol are mainly produced depending on the structure of the protecting group. It is considered that a gas generation phenomenon occurs due to generation of residual solvent and decomposition products of the polymer.

Embodiments 8 to 12 described below solve the rupture problem caused by gas generation of the ion-implanted photoresist film.

<Method> FIGS. 62 to 67 are cross sectional views showing a gate pattern forming step which is one of the wiring pattern forming methods according to the eighth embodiment of the present invention. Hereinafter, the processing procedure of the eighth embodiment will be described with reference to these drawings.

First, as shown in FIG. 62, a silicon oxide film 12 is formed on a silicon substrate 1 to a thickness of 15 nm, a polysilicon layer 2 is formed to a thickness of 100 nm, and a silicon oxide film 21 is formed to a thickness of 50 nm. After forming a silicon oxynitride film 8 with a thickness of 48 nm, a photoresist film 4 is applied on the silicon oxynitride film 8 and
Prebaking was performed for 0 seconds. At this time, the number of rotations at the time of coating is adjusted so that the thickness of the photoresist film 4 becomes 585 nm.

Next, as shown in FIG. 63, exposure was performed using a KrF excimer laser 6 as a light source through a reticle 5 on which a wiring pattern was drawn. The illumination condition was NA = 0.65, and the off-axis method using a 2/3 annular illumination aperture was applied.

Subsequently, a bake at 110 ° C. for 90 seconds (PE
After performing B), development is performed for 60 seconds using a 2.38% by weight aqueous solution of tetramethylammonium hydroxide (TMAH) to obtain a resist pattern 4a corresponding to the reticle as shown in FIG.

Next, as shown in FIG. 65, the resist pattern 4a is exposed using a stepper using a KrF excimer laser 19 as a light source.
Was performed at 100 ° C. for 90 seconds to obtain a resist pattern 4c. The KrF excimer laser 19
Has a wavelength of 248 nm.

By the exposure treatment and heat treatment shown in FIG. 65, the resist pattern 4a can be changed to a resist pattern 4c in which a decomposition reaction, which is one of the chemical reactions, has advanced.

Then, as shown in FIG. 66, ions 7 were implanted into the resist pattern 4c to obtain a resist pattern 4d. Here, argon is used as an ion species and ion implantation is performed at 1 × 10 ¹⁶ / cm ² at 50 keV. As a result of this ion implantation, as described above, the thickness of the resist pattern 4d shrinks from the resist pattern 4c, and the etching resistance to the etching process for the silicon oxide film 21 and the silicon nitride oxide film 8 is improved. For example, the resist pattern 14c before the ion implantation shown in FIG. 66 has a line width of 0.14 μm, but is reduced to 0.10 μm in the resist pattern 14d after the ion implantation.

Next, as shown in FIG. 67, the silicon nitride oxide film 8 and the silicon oxide film 21 are etched using the resist pattern 4d as a mask. The polysilicon layer 2 is etched using the silicon nitride oxide film 8 and the silicon oxide film 21 as a mask to form a desired wiring pattern (polysilicon pattern 2).
Obtain a). The silicon nitride oxide film 8, the silicon oxide film 21, and the polysilicon layer 2 may be etched using the resist pattern 4d as a mask.

At this time, the resist pattern 4d has a higher etching resistance to the etching process for the silicon oxide film 21 and the silicon oxynitride film 8 than the resist pattern 4c due to the ion implantation. Even if contracted in the step shown in FIG. 66, it functions as an etching mask without any problem.

Further, the resist pattern 4d is formed by the exposure processing and heat treatment (chemical reaction promoting processing) shown in FIG.
Since (4c) is a state in which the decomposition reaction has progressed, during the etching process on the silicon nitride oxide film 8 and the silicon oxide film 21, no gas is generated in the resist pattern 4d, and a problem such as rupture occurs in the resist pattern 4d. Not even.

In the present embodiment, as a wiring pattern forming method, a gate pattern forming step using the polysilicon layer 2 has been described. Of course, the present invention can be applied to other steps such as a bit line forming step, a metal wiring step, and a hole step. The invention can be applied.

<< Ninth Embodiment >> FIGS. 68 to 73 are cross sectional views showing a capacitor pattern forming step according to the ninth embodiment of the present invention. FIG. 74 is an explanatory view showing a reticle on which a pattern in a DRAM capacitor forming step is drawn. In the ninth embodiment, it is assumed that a capacitor of a DRAM is formed. Hereinafter, the processing procedure of the ninth embodiment will be described with reference to these drawings.

First, as shown in FIG. 68, a silicon nitride film 22 is formed on the silicon substrate 1 to a thickness of 50 nm, a silicon oxide film 23 is formed to a thickness of 1500 nm, and A photoresist film 4 was applied and prebaked at 100 ° C. for 60 seconds. At this time,
The number of revolutions during coating was adjusted so that the thickness of the photoresist film 4 was 880 nm.

Next, as shown in FIG. 69, a KrF excimer laser (wavelength: 248 nm) 6 is used as a light source through a reticle (photomask) 26 (see FIG. 74) on which a pattern for a DRAM capacitor formation step is drawn. Exposure was performed using a stepper. The lighting condition is NA = 0.65
An off-axis method using a 2/3 annular illumination aperture was applied.

Subsequently, as shown in FIG. 70, after baking (PEB) at 110 ° C. for 90 seconds, 2.38% by weight of tetramethylammonium hydroxide (TMAH) was used.
By performing development for 60 seconds using the aqueous solution, the resist pattern 25a for the capacitor corresponding to the reticle is formed.
Get.

Then, as shown in FIG. 71, the resist pattern 25a is exposed using a stepper using a KrF excimer laser 19 as a light source, and then baked at 100 ° C. for 90 seconds using a heat source 20. A resist pattern 25c was obtained.

By the exposure treatment and the heat treatment shown in FIG. 71, the resist pattern 25a can be changed to the resist pattern 25c in which the decomposition reaction has progressed.

Next, as shown in FIG. 72, ions 7 were implanted into the resist pattern 25c under the conditions of 50 keV and 1 × 10 ¹⁶ / cm ^{2 using} argon as an ion species to obtain a resist pattern 25d. .

The resist pattern 25d is contracted by ion implantation, and the line width of the remaining resist is 0.17 μm of the resist pattern 25c.
m to 0.11 μm.

Then, as shown in FIG. 73, the silicon oxide film 23 and the silicon oxynitride film 24 are etched using the resist pattern 25d as a mask, thereby forming a dielectric capacitor pattern (the silicon oxide film patterns 23a and 23a). A silicon oxynitride film pattern 24a) is obtained.

At this time, the etching resistance of the resist pattern 25d to the etching process for the silicon oxide film 23 and the silicon oxynitride film 24 is improved by the ion implantation from the resist pattern 25c. Even if the resist pattern 25c shrinks from the resist pattern 25c in the step 72, it functions as an etching mask without any trouble.

Further, since the decomposition reaction of the resist pattern 25d (25c) is progressing by the exposure processing and heat treatment shown in FIG. 71, the gas generation problem can be effectively suppressed as described above, and the resist pattern 25d There is no problem such as rupture.

In the DRAM capacitor forming step, it is desirable to form a large opening pattern in order to obtain a large capacitance, that is, to form an electrode made of polysilicon or the like having a large surface area. This is effective because the space width can be relatively easily expanded due to the contraction of the line width.

Although the capacitor pattern forming step has been described in the present embodiment, the method of the ninth embodiment is applied in the DRAM self-align contact hole forming step and the stack via hole forming step in order to form a large opening pattern. Thereby, a similar effect can be obtained.

<< Tenth Embodiment >><Problem> In the method of forming a wiring pattern according to the fourth embodiment shown in FIGS. 28 to 35, the photoresist film 4 which is the first photoresist film and the second photoresist The wiring pattern is formed by two-layer coating of a photoresist including a photoresist film 14 which is a photoresist film of FIG.

Also in this case, there is a problem that the first photoresist film may be ruptured when the resist pattern 14b of the photoresist film 14 formed on the resist pattern 4b of the photoresist film 4 is formed. Was.

That is, after the ions are implanted into the resist pattern 4b, the resist film 4b formed on the resist pattern 4b is exposed to light and baked during the exposure and baking processes. There was a problem that the pattern 4b burst. Such a phenomenon tends to occur particularly in the case of a large-area pattern in the resist pattern 4b. Embodiment 10 is a method for solving the above problem.

<Method> FIGS. 75 to 83 are sectional views showing a wiring pattern forming method according to the tenth embodiment of the present invention. In the tenth embodiment, the transistor portion is 0.1
The figure shows a gate step of forming a cover for providing a thin line pattern of μm or less and a contact hole for connection with an upper layer or a lower layer. Hereinafter, the processing procedure of the tenth embodiment will be described with reference to these drawings.

For high-speed operation of the device, it is necessary to form a transistor having a smaller line width. On the other hand, the contact hole cover needs to be formed larger to secure a contact area. Further, it is important to reduce the space between the covers as much as possible in order to highly integrate the device.

As described in the eighth and ninth embodiments, it is possible to form a thin line pattern in the transistor portion by utilizing the pattern shrinkage due to the ion implantation, but the contact cover portion is reduced. This is undesirable for the reasons described above. Thus, as in the fourth embodiment, it is effective to divide the process into two photolithography processes using two photoresist films.

First, as shown in FIG. 75, a silicon oxide film 1 having a thickness of 15 nm (150 °) is formed on a silicon substrate 1.
2. After forming a polysilicon layer 2 having a thickness of 100 nm (1000 °), a thickness of 50 nm is formed on the polysilicon layer 2.
(500 °) silicon oxide film 21, 48 nm thick
After forming the silicon nitride oxide film 8 of (480 °), a photoresist film 27 is applied and prebaked at 100 ° C. for 90 seconds. At this time, the rotation speed at the time of coating was adjusted so that the thickness of the photoresist film 27 became 585 nm.

Next, as shown in FIG. 76, KrF is applied via a reticle (photomask) 5a in which only the wiring pattern of the transistor formation region, which is the first processing region, is drawn.
Exposure was performed using a stepper using an excimer laser (wavelength: 248 nm) 6 as a light source. The lighting conditions are NA =
At 0.65, an off-axis method using a 2/3 annular illumination aperture was applied.

Subsequently, as shown in FIG. 77, after baking (PEB) at 110 ° C. for 90 seconds, 2.38% by weight of tetramethylammonium hydroxide (TMAH) was used.
By performing development for 60 seconds using an aqueous solution, a relatively dense resist pattern 27 having a line width of 0.14 μm is formed.
Obtain a.

Then, as shown in FIG. 78, the resist pattern 27a is exposed using a stepper using a KrF excimer laser 19 as a light source, and then baked at 110 ° C. for 90 seconds using a heat source 20. A resist pattern 27c was obtained. The wavelength of the KrF excimer laser 19 is 248 nm.

By the exposure treatment and the heat treatment shown in FIG. 78, the resist pattern 2 is compared with the resist pattern 27a.
The decomposition reaction of 7c can proceed.

Next, as shown in FIG. 79, ions 7 are implanted into the resist pattern 27c under the conditions of 50 keV and 1 × 10 ¹⁶ / cm ^{2 using} argon as an ion species to obtain a resist pattern 27d. . By this ion implantation, as described above, the film thickness of the resist pattern 27d contracts from the resist pattern 27c,
The etching resistance to the etching process for the silicon oxide film 21 and the silicon oxynitride film 8 is improved.

Then, as shown in FIG. 80, a photoresist film 29 is applied and formed on the entire surface including the resist pattern 27d. At this time, the application conditions are the same as when the first photoresist film 27 is formed.

Next, as shown in FIG. 81, a KrF excimer laser (wavelength) is applied through a reticle (photomask) 5b drawn corresponding to a contact hole formation region which is a second processing region excluding the transistor formation region. Is 24
Exposure is performed using a stepper having a light source of 8 nm) 6. The off-axis method using a 2/3 annular illumination aperture at NA = 0.65 was applied as the illumination condition.

Subsequently, as shown in FIG. 82, after baking (PEB) at 110 ° C. for 90 seconds, 2.38% by weight of tetramethylammonium hydroxide (TMAH) was used.
By performing development for 60 seconds using an aqueous solution, a relatively sparse resist pattern 29a is obtained.

At this time, since the decomposition reaction of the resist pattern 27d (27c) is progressing by the exposure processing and heat treatment shown in FIG. 78, the gas generation problem can be effectively suppressed as described above, Problems such as rupture do not occur in 27d.

As shown in FIG. 83, the silicon nitride oxide film 8 and the silicon oxide film 21 are etched using the resist pattern 27d and the resist pattern 29a as a mask.
After stripping the resist pattern 7d and the resist pattern 29a, the polysilicon layer 2 is etched using the patterned silicon nitride oxide film 8 and silicon oxide film 21 as a mask to obtain a desired wiring pattern (polysilicon pattern 2a). Note that the silicon nitride oxide film 8, the silicon oxide film 21, and the polysilicon layer 2 may be collectively subjected to the etching process using the resist pattern 27d and the resist pattern 29a as a mask.

At this time, since the etching resistance of the resist pattern 27d to the etching process for the silicon nitride oxide film 8 and the silicon oxide film 21 is improved by the ion implantation from the resist pattern 27c, the thickness of the resist pattern 27d is reduced. Even if it shrinks from the resist pattern 25c in the step indicated by 79, it functions without any trouble as an etching mask.

According to the method of the tenth embodiment, a dense resist pattern 27d having a line width smaller than the mask size is formed in the transistor forming region, and a relatively sparse resist pattern 29a is formed in regions other than the transistor forming region.
Can be formed without deteriorating accuracy, and wiring patterns having different roughness densities can be formed accurately.

In the present embodiment, as the wiring pattern forming method, the gate pattern forming step using the polysilicon layer 2 has been described.
Of course, the present invention can be applied to other processes such as a hole process.

<< Eleventh Embodiment >><Problem> Similar to the tenth embodiment, in the case of performing two separate photolithography processes, which are difficult to form simultaneously, a higher etching resistance is required. In this case, the wiring pattern is formed.

The method for forming a wiring pattern according to the eleventh embodiment is intended to obtain a finer pattern than that of the tenth embodiment.
It is assumed that an rF resist is used. The ArF resist is inferior in dry etching resistance to the KrF resist, and it is desired to reduce the resist film thickness. Therefore, in the twelfth embodiment, the second photoresist film is ion-implanted to improve the etching resistance.
This is the method.

<Method> FIGS. 84 to 94 are sectional views showing a wiring pattern forming method according to an eleventh embodiment of the present invention. In the eleventh embodiment, the transistor portion is 0.1
This figure shows a gate step of forming a cover for a thin line pattern of not more than μm and a contact hole for connection with an upper layer or a lower layer. Hereinafter, the processing procedure of the eleventh embodiment will be described with reference to these drawings.

First, as shown in FIG. 84, a silicon oxide film 12 having a thickness of 15 nm
After forming the polysilicon layer 2 having a thickness of 00 nm, a silicon oxide film 21 having a thickness of 50 nm and a silicon oxynitride film 8 having a thickness of 48 nm are formed on the polysilicon layer 2, and a photoresist film 31 is applied. Prebake at 100 ° C. for 90 seconds. At this time, the thickness of the photoresist film 31 is 4
The number of revolutions at the time of coating was adjusted to be 00 nm (4000 °).

Next, as shown in FIG. 85, a stepper using an ArF excimer laser (wavelength: 193 nm) as a light source through a reticle (photomask) 5a on which only a wiring pattern in a transistor formation region is drawn. Exposure was performed. The illumination condition was NA = 0.60, and an off-axis method using a 2/3 annular illumination aperture was applied.

Subsequently, as shown in FIG. 86, after baking (PEB) at 110 ° C. for 90 seconds, 2.38% by weight of tetramethylammonium hydroxide (TMAH) was used.
The resist pattern 31a having a line width of 0.12 μm is obtained by performing development for 60 seconds using an aqueous solution.

Then, as shown in FIG. 87, the resist pattern 31a is exposed using a stepper using the ArF excimer laser 30 as a light source, and then baked at 110 ° C. for 90 seconds using the heat source 20, A resist pattern 31c was obtained. The wavelength of the ArF excimer laser 30 is 193 nm.

By the exposure treatment and the heat treatment shown in FIG. 87, the resist pattern 3 is compared with the resist pattern 31a.
The decomposition reaction of 1c can proceed.

Next, as shown in FIG. 88, ions 7 are implanted into the resist pattern 31c under the conditions of 50 keV and 1 × 10 ¹⁶ / cm ^{2 using} argon as an ion species to obtain a resist pattern 31d. .

By the ion implantation, as described above, the thickness of the resist pattern 31d shrinks from the resist pattern 31c, and the etching resistance to the etching process for the silicon oxide film 21 and the silicon nitride oxide film 8 is improved. Further, the resist pattern 31d obtained after the ion implantation is reduced from the line width of 0.12 μm of the resist pattern 31c to 0.08 μm.

Therefore, as shown in FIG. 89, a photoresist film 34 is applied and formed on the entire surface including the resist pattern 31d. At this time, the application conditions are the same as when the first photoresist film 27 is formed.

Next, as shown in FIG. 90, ArF is formed via a reticle (photomask) 5b drawn corresponding to the contact hole forming region excluding the transistor forming region.
Exposure is performed using a stepper using an excimer laser (wavelength: 248 nm) 28 as a light source. The lighting conditions are NA =
At 0.60, an off-axis method using a 2/3 annular illumination aperture was applied.

Subsequently, as shown in FIG. 91, after baking (PEB) at 110 ° C. for 90 seconds, 2.38% by weight of tetramethylammonium hydroxide (TMAH) was used.
The resist pattern 34a is obtained by performing development for 60 seconds using an aqueous solution.

At this time, since the decomposition reaction of the resist pattern 31d (27c) is progressing by the exposure processing and heat treatment shown in FIG. 87, the gas generation problem can be effectively suppressed as described above, There is no problem such as rupture in 31d.

Next, as shown in FIG. 92, the resist pattern 31d and the resist pattern 34a are
Exposure was performed using a stepper using an excimer laser (wavelength: 193 nm) 30 as a light source, followed by baking at 100 ° C. for 90 seconds to obtain a resist pattern 31e and a resist pattern 34c.

Then, as shown in FIG. 93, ions 7 were implanted into the resist pattern 31e and the resist pattern 34c to obtain a resist pattern 31f and a resist pattern 34d. Here, an implantation energy of 50 keV and 1 × 10 ¹⁵ / cm ² are used with argon as an ion species.
The ion 7 was implanted under the following conditions.

By reducing the ion implantation amount in the ion implantation step shown in FIG. 93 from the ion implantation amount in the ion implantation step shown in FIG. 88, the resist pattern 31f and the resist pattern 34d shrink with respect to the resist pattern 31e and the resist pattern 34c. The amount can be kept to a minimum.

By the ion implantation step shown in FIG. 93, the etching resistance of the resist pattern 31f (the pattern of the transistor forming region) and the resist pattern 34d (the pattern other than the transistor forming region) can be made higher than the resist pattern 31e and the resist pattern 34c. .

As shown in FIG. 94, the silicon nitride oxide film 8 and the silicon oxide film 21 are etched using the relatively dense resist pattern 31f and the relatively sparse resist pattern 34d as a mask. , Resist pattern 31f and resist pattern 34
After stripping d, the polysilicon layer 2 is etched using the patterned silicon nitride oxide film 8 and silicon oxide film 21 as a mask to obtain a desired wiring pattern (polysilicon pattern 2a). Note that the silicon nitride oxide film 8, the silicon oxide film 21, and the polysilicon layer 2 may be collectively subjected to the etching process using the resist pattern 31f and the resist pattern 34d as a mask.

At this time, since the resist pattern 31f and the resist pattern 34d have improved the etching resistance to the etching process for the silicon nitride oxide film 8 and the silicon oxide film 21 from the resist pattern 31c by ion implantation, the resist pattern 31f Even if the film thickness shrinks in the ion implantation step shown in FIGS. 88 and 93, and the film thickness of the resist pattern 34d shrinks in the ion implantation step shown in FIG. 93, the resist pattern 34d functions as an etching mask without any problem.

Further, since the decomposition reaction of the resist patterns 31f (31e) and the resist patterns 34d (34c) is progressing by the exposure processing and heat treatment shown in FIG. 82, the gas generation problem is effectively suppressed as described above. Therefore, there is no problem such as rupture in the resist pattern 31f and the resist pattern 34d.

According to the method of the eleventh embodiment, a dense resist pattern 31f having a line width smaller than the mask size is formed in the transistor formation region, and a relatively sparse resist pattern 34d is formed in regions other than the transistor formation region.
Can be formed without deteriorating accuracy, and wiring patterns having different roughness densities can be formed accurately.

In the present embodiment, the gate pattern forming step using the polysilicon layer 2 has been described as the wiring pattern forming method.
Of course, the present invention can be applied to other processes such as a hole process.

<< Twelfth Preferred Embodiment >> FIGS. 95 to 99 are cross-sectional views showing a gate pattern forming step which is one of the wiring pattern forming methods according to the twelfth preferred embodiment of the present invention. Hereinafter, the processing procedure will be described with reference to these drawings.

First, as shown in FIG. 95, a silicon oxide film 12 having a thickness of 15 nm, a polysilicon layer 2 having a thickness of 100 nm, and a silicon oxide film 21 having a thickness of 50 nm are formed on a silicon substrate 1. After a silicon oxynitride film 8 was formed to a thickness of 48 nm, a photoresist film 4 was applied on the silicon oxynitride film 8 and prebaked at 100 ° C. for 90 seconds. At this time, the number of rotations at the time of coating is adjusted so that the thickness of the photoresist film 4 becomes 585 nm.

Next, as shown in FIG. 96, exposure was performed using a stepper using a KrF excimer laser 6 as a light source through a reticle 5 on which a wiring pattern was drawn. The illumination condition was NA = 0.65, and the off-axis method using a 2/3 annular illumination aperture was applied.

Subsequently, a bake at 110 ° C. for 90 seconds (PE
After B), development is performed for 60 seconds using a 2.38% by weight aqueous solution of tetramethylammonium hydroxide (TMAH) to obtain a resist pattern 4a corresponding to the reticle as shown in FIG.

Then, as shown in FIG. 98, the ion 7 was implanted into the resist pattern 4a in three steps, in the order of ions 7a, 7b and 7c. Here, boron is used as an ion species, and
Ions are implanted at 4 × 10 ¹⁵ / cm ² (dose amount) at keV (implantation energy), and ions 7b are 3 at 90 keV.
The ions are implanted at × 10 ¹⁵ / cm ² and the ions 7c are 40
Ion implantation is performed at 3 × 10 ¹⁵ / cm ² at keV. By the three-step partial ion implantation of these ions 7a to 7c, the thickness of the resist pattern 4a is reduced, and the etching resistance to the etching process for the silicon oxide film 21 and the silicon nitride oxide film 8 is improved.

FIG. 100 shows the ion implantation energy (ke).
5 is a graph showing a relationship between V) and an average range distance Rp (Å). In the figure, open circles represent boron, black circles represent phosphorus, white triangles represent arsenic, and black triangles represent antimony. The implanted ions are scattered by collisions with the atoms in the resist and draw complex miracles, while the average range Rp shown in FIG.
Are distributed around.

Therefore, the implantation of the ions 7a (first partial ion implantation) allows the lower portion of the resist pattern 4a,
The average range Rp of boron is set in the middle layer of the resist pattern 4a by the implantation of the ions 7b (second partial ion implantation) and in the upper layer of the resist pattern 4a by the implantation of the ions 7c (third partial ion implantation). Therefore, boron ions are implanted from the top to the bottom of the resist pattern 4a, thereby forming the resist pattern 4a.
The curing of a is performed almost uniformly from the top to the bottom.

Next, as shown in FIG. 99, the silicon nitride oxide film 8 and the silicon oxide film 21 are etched using the resist pattern 4a as a mask. The polysilicon layer 2 is etched using the silicon nitride oxide film 8 and the silicon oxide film 21 as a mask to form a desired wiring pattern (polysilicon pattern 2).
Obtain a). Note that the silicon nitride oxide film 8, the silicon oxide film 21, and the polysilicon layer 2 may be collectively subjected to etching using the resist pattern 4a as a mask.

At this time, since the resist pattern 4a is hardened almost uniformly from the top to the bottom in the film thickness direction, even if the resist pattern 4a is a large area pattern in which the resist pattern 4a is likely to be ruptured, the resist pattern 4a is ruptured. A normal etching process can be performed without performing.

<< Others >> In the above embodiment, argon (Ar) or boron (B) is used as the ion species to be implanted, but helium (He), neon (Ne), and nitrogen (N ₂ ) are used. ), Carbon monoxide (CO), phosphorus (P), arsenic (As), antimony (Sb), boron fluoride (BF), and the like.

Further, electron beam irradiation is performed instead of ion implantation for performing a curing process, and the wavelength λ is 250 to 450 nm.
A similar effect can be obtained by DeepUV irradiation in the vicinity. In short, it suffices if a curing process in a broad sense capable of contracting the pattern and improving the etching resistance can be performed on the resist pattern.

Further, as a photoresist film, KrF, A
Not limited to rF excimer resist, g-line resist, i
It is effective for any material such as a resist for a line, a resist for a VUV (F ₂ ) excimer, a resist for an electron beam, and a resist for an X-ray.

The exposure treatment and the heat treatment, which are the chemical reaction accelerating treatments described in the eighth to eleventh embodiments, are performed to accelerate the decomposition reaction of the resist pattern by the photoresist film. Therefore, only one of the exposure treatment and the heat treatment may be performed as long as the decomposition reaction of the resist pattern can be promoted.

[0213]

As described above, in the method of manufacturing a semiconductor device according to the first aspect of the present invention, by performing step (d), the film thickness of the first resist pattern is reduced by the dense pattern in the processed pattern. The difference in the amount of dimensional deviation from the first resist pattern, which occurs between the portion and the sparse pattern portion, is less than or equal to a predetermined reference,
In addition, since the film thickness is set to satisfy a condition that does not hinder the predetermined etching process, even if the processing pattern has a relatively large difference in density when the etching target is an insulator, the step (e) is performed. In addition, a processing pattern can be obtained with high dimensional accuracy.

Further, since the first resist pattern is ion-implanted in the step (d) to improve the etching resistance to a predetermined etching process, the thickness of the first resist pattern is reduced. However, it does not adversely affect the predetermined etching process.

In addition, the first resist pattern is ion-implanted in the process of step (d), whereby the roughness of the edge portion of the first resist pattern is reduced, and the first resist pattern having excellent linearity is obtained. Can be obtained.

The method of manufacturing a semiconductor device according to claim 2 is
Since the ions that are implanted in the step (d) are prevented from being implanted into the actual etching target by the ion blocking film, the ion etching does not adversely affect the actual etching target.

In the method of manufacturing a semiconductor device according to claim 3, since the silicon nitride film or the silicon oxynitride film is formed by using the plasma CVD method, the silicon nitride film or the silicon nitride oxide film can be formed with a uniform thickness. Does not adversely affect the resist pattern shape.

In the method of manufacturing a semiconductor device according to the fourth aspect, since the ion blocking film includes an organic anti-reflection film, the thickness of the organic anti-reflection film shrinks in a direction in which the step is reduced by ion implantation. The step of the object can be made flatter than before the ion implantation, and the dimensional non-uniformity of the processing pattern caused by the step during a predetermined etching process can be reduced.

In the method of manufacturing a semiconductor device according to the fifth aspect, in addition to the step (d), the step of the object to be etched can be largely flattened by the ion implantation performed during the execution of the step (a-3). In addition, it is possible to further reduce the dimensional non-uniformity of the processing pattern caused by the step during the predetermined etching process.

[0220] In the method of manufacturing a semiconductor device according to claim 6, a relatively dense first resist pattern utilizing a pattern contraction phenomenon caused by ion implantation and a relatively sparse first resist pattern utilizing a pattern contraction phenomenon caused by ion implantation. By performing a predetermined etching process using the second resist pattern as a mask, processed patterns having different densities can be accurately obtained.

In the method of manufacturing a semiconductor device according to the seventh aspect, the first resist pattern is not substantially removed during the execution of the step (g) due to a composition change caused by the ion implantation in the step (d). The formation process of the second resist performed in the step ()) can be executed by the simplest whole surface formation process.

[0222] In the method of manufacturing a semiconductor device according to the eighth aspect, the ion implantation in the step (d) is performed obliquely with respect to a perpendicular to the surface on which the first resist pattern is formed. Also, ions are hardly implanted into the etching object under the first resist pattern because the ion implantation into the etching object is prevented. Therefore, it is possible to avoid a problem that ions are implanted into the etching target.

In the method of manufacturing a semiconductor device according to the ninth aspect, the surface to be etched has an uneven shape, but the uneven shape is relaxed by the ion implantation in step (d). The adverse effects can be suppressed.

In the method of manufacturing a semiconductor device according to the tenth aspect, since the irregularities on the surface of the object to be etched are alleviated by the ion implantation in the step (d), reflection from the irregularities in the exposure treatment in the step (b) is performed. The adverse effects caused by the above can be suppressed.

[0225] In the method of manufacturing a semiconductor device according to the eleventh aspect, a mark for superimposing a mask is provided on the surface of the etching object. The measurement accuracy of this mark is degraded due to the unevenness of the surface.However, since the unevenness is reduced by the ion implantation in step (h), the overlay accuracy of the mask should be improved with the improvement of the measurement accuracy of the mark. Can be.

According to a twelfth aspect of the present invention, in the step (h-3), ions are implanted into the mark formation region of the etching target using the third resist pattern as a mask. The unevenness of the surface of the mark formation region is reduced by the ion implantation, so that the accuracy of mask overlay can be improved with the improvement of the measurement accuracy of the mark.

Further, the third resist pattern can reliably prevent ion implantation into an etching object other than the mark forming region.

In the method of manufacturing a semiconductor device according to the thirteenth aspect, a plurality of partial ion implantations having different implantation energies are performed to harden the first resist pattern in the film thickness direction with good uniformity. The predetermined etching process can be performed without interfering with the first resist pattern.

In the method of manufacturing a semiconductor device according to the fourteenth aspect of the present invention, the film thickness of the first resist pattern is reduced by performing the curing process in step (e). A processing pattern can be obtained with high dimensional accuracy.

In addition, since the decomposition reaction of the first resist pattern is accelerated by the chemical reaction accelerating process of step (d), the generation of gas in the first resist pattern during the execution of step (f) is reduced. The accompanying trouble can be reliably avoided.

[0231] In the method of manufacturing a semiconductor device according to the fifteenth aspect, a relatively dense first resist pattern utilizing a shrinkage phenomenon of a film thickness and a pattern dimension caused by a curing process, and a film thickness and a film thickness caused by a curing process are reduced. Relatively sparse second without utilizing the shrinkage phenomenon of pattern size
By performing a predetermined etching process using this resist pattern as a mask, processed patterns having different densities can be accurately obtained.

In the method of manufacturing a semiconductor device according to the present invention, the etching resistance of the second resist pattern with respect to a predetermined etching process can be improved by the curing process in the step (j). At this time, if the curing process of step (j) is performed so that the film thickness of the second resist pattern hardly shrinks, the relatively sparse second resist pattern can be maintained.

In addition, the decomposition reaction of the first and second resist patterns is accelerated by the chemical reaction accelerating processes of steps (d) and (i). Problems caused by generation of gas in the resist pattern can be reliably avoided.

[0234] In the method of manufacturing a semiconductor device according to the seventeenth aspect, the first or second resist pattern as an object is subjected to exposure processing and heat treatment, whereby a decomposition reaction in the first or second resist pattern is performed. Can be promoted.

In the method of manufacturing a semiconductor device according to the eighteenth aspect of the present invention, the first resist pattern having a relatively dense first resist pattern utilizing a shrinkage phenomenon of a film thickness and a pattern dimension caused by the curing process in step (d). By performing a predetermined etching process using a relatively sparse second resist pattern as a mask that does not use the contraction phenomenon of the film thickness and pattern dimension caused by the curing process, processing patterns having different density differences can be accurately detected. Obtainable.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a wiring pattern forming method that is a principle of the first embodiment;

FIG. 2 is a cross-sectional view illustrating a wiring pattern forming method according to the principle of the first embodiment;

FIG. 3 is a cross-sectional view illustrating a wiring pattern forming method according to the principle of the first embodiment;

FIG. 4 is a cross-sectional view illustrating a wiring pattern forming method that is a principle of the first embodiment;

FIG. 5 is a graph showing a comparison result of a pattern size between a resist pattern and a processed pattern after etching.

FIG. 6 is a graph showing space width dependency.

FIG. 7 is a cross-sectional view showing a wiring pattern forming method according to the first embodiment of the present invention;

FIG. 8 is a sectional view illustrating the wiring pattern forming method according to the first embodiment;

FIG. 9 is a sectional view illustrating the wiring pattern forming method according to the first embodiment;

FIG. 10 is a sectional view showing the wiring pattern forming method according to the first embodiment;

FIG. 11 is a sectional view illustrating the wiring pattern forming method of the first embodiment;

FIG. 12 is a graph showing space width dependency.

FIG. 13 is an explanatory diagram showing a resist pattern shape after development.

FIG. 14 is an explanatory view showing a resist pattern shape after ion implantation.

FIG. 15 is a cross-sectional view showing a wiring pattern forming method according to the second embodiment;

FIG. 16 is a cross-sectional view showing a wiring pattern forming method according to the second embodiment;

FIG. 17 is a cross-sectional view showing a wiring pattern forming method according to the second embodiment;

FIG. 18 is a cross-sectional view showing a wiring pattern forming method according to the second embodiment;

FIG. 19 is a cross-sectional view showing a wiring pattern forming method according to the second embodiment;

FIG. 20 is a cross-sectional view showing a wiring pattern forming method according to the second embodiment;

FIG. 21 is a cross-sectional view illustrating a wiring pattern forming method according to the third embodiment;

FIG. 22 is a cross-sectional view showing a wiring pattern forming method according to the third embodiment;

FIG. 23 is a cross-sectional view showing a wiring pattern forming method according to the third embodiment;

FIG. 24 is a cross-sectional view showing a wiring pattern forming method according to the third embodiment;

FIG. 25 is a cross-sectional view showing a wiring pattern forming method according to the third embodiment;

FIG. 26 is a sectional view illustrating the wiring pattern forming method according to the third embodiment;

FIG. 27 is a cross-sectional view showing a wiring pattern forming method according to the third embodiment;

FIG. 28 is a cross-sectional view showing a wiring pattern forming method according to the fourth embodiment;

FIG. 29 is a cross-sectional view illustrating the wiring pattern forming method of the fourth embodiment;

FIG. 30 is a cross-sectional view showing a wiring pattern forming method according to the fourth embodiment;

FIG. 31 is a cross-sectional view showing a wiring pattern forming method according to the fourth embodiment;

FIG. 32 is a cross-sectional view showing a wiring pattern forming method according to the fourth embodiment;

FIG. 33 is a cross-sectional view showing a wiring pattern forming method according to the fourth embodiment;

FIG. 34 is a cross-sectional view showing a wiring pattern forming method according to the fourth embodiment;

FIG. 35 is a cross-sectional view showing a wiring pattern forming method according to the fourth embodiment;

FIG. 36 is a sectional view showing the wiring pattern forming method according to the fifth embodiment;

FIG. 37 is a cross-sectional view showing a wiring pattern forming method according to the fifth embodiment;

FIG. 38 is a sectional view showing the wiring pattern forming method according to the fifth embodiment;

FIG. 39 is a sectional view showing the wiring pattern forming method according to the fifth embodiment;

FIG. 40 is a cross-sectional view showing a wiring pattern forming method according to the fifth embodiment.

FIG. 41 is an explanatory view showing a reticle on which a pattern in a DRAM capacitor forming step is drawn.

FIG. 42 is a sectional view showing a characteristic portion of the wiring pattern forming method according to the fifth embodiment;

FIG. 43 is an explanatory view schematically showing a surface shape of an aluminum film formed by a normal sputtering method.

FIG. 44 is an explanatory diagram schematically showing the surface shape of an aluminum film formed by sputtering while heating.

FIG. 45 is an explanatory diagram schematically showing a surface shape after ion implantation into an aluminum film formed by sputtering while heating.

FIG. 46 is a sectional view showing a characteristic portion of the wiring pattern forming method according to the sixth embodiment of the present invention;

FIG. 47 is a cross-sectional view showing a characteristic portion of the method for forming a wiring pattern according to the seventh embodiment of the present invention;

FIG. 48 is a cross-sectional view showing a conventional wiring pattern forming method.

FIG. 49 is a cross-sectional view showing a conventional wiring pattern forming method.

FIG. 50 is a cross-sectional view showing a conventional wiring pattern forming method.

FIG. 51 is a cross-sectional view showing a conventional wiring pattern forming method.

FIG. 52 is a graph showing a comparison result of pattern dimensions between a resist pattern and a processed pattern obtained after etching.

FIG. 53 is a graph showing space width dependency.

FIG. 54 is a cross-sectional view for explaining a shoulder drop of a resist pattern.

FIG. 55 is a cross-sectional view for explaining a shoulder drop of a resist pattern.

FIG. 56 is a cross-sectional view for explaining a shoulder drop of a resist pattern.

FIG. 57 is a cross sectional view showing a gate pattern forming step which is a premise of the eighth embodiment.

FIG. 58 is a cross sectional view showing a gate pattern forming step which is a premise of the eighth embodiment.

FIG. 59 is a cross sectional view showing a gate pattern forming step which is a premise of the eighth embodiment.

FIG. 60 is a cross-sectional view showing a gate pattern forming step which is a premise of the eighth embodiment.

FIG. 61 is a cross sectional view showing a gate pattern forming step which is a premise of the eighth embodiment.

FIG. 62 is a cross-sectional view showing a gate pattern forming step of the eighth embodiment;

FIG. 63 is a cross-sectional view showing a gate pattern forming step of Embodiment 8;

FIG. 64 is a cross-sectional view showing a gate pattern forming step according to the eighth embodiment;

FIG. 65 is a cross-sectional view showing a gate pattern forming step of Embodiment 8;

FIG. 66 is a cross-sectional view showing a gate pattern forming step of Embodiment 8;

FIG. 67 is a cross-sectional view showing a gate pattern forming step of Embodiment 8;

FIG. 68 is a cross sectional view showing a capacitor pattern forming step of Embodiment 9;

FIG. 69 is a cross sectional view showing a capacitor pattern forming step of Embodiment 9;

FIG. 70 is a cross sectional view showing a capacitor pattern forming step of Embodiment 9;

FIG. 71 is a cross sectional view showing a capacitor pattern forming step of Embodiment 9;

FIG. 72 is a cross-sectional view showing a capacitor pattern forming step of the ninth embodiment;

FIG. 73 is a cross-sectional view showing a capacitor pattern forming step of the ninth embodiment;

FIG. 74 is an explanatory diagram showing a reticle used in the ninth embodiment.

FIG. 75 is a sectional view showing the wiring pattern forming method of the tenth embodiment;

FIG. 76 is a sectional view showing the wiring pattern forming method of the tenth embodiment;

FIG. 77 is a sectional view showing the wiring pattern forming method of the tenth embodiment;

FIG. 78 is a sectional view showing the wiring pattern forming method of the tenth embodiment;

FIG. 79 is a sectional view showing the wiring pattern forming method of the tenth embodiment;

FIG. 80 is a cross-sectional view showing a wiring pattern forming method according to the tenth embodiment;

FIG. 81 is a cross-sectional view showing a wiring pattern forming method according to the tenth embodiment;

FIG. 82 is a cross-sectional view showing a wiring pattern forming method according to the tenth embodiment;

FIG. 83 is a cross-sectional view showing the wiring pattern forming method according to the tenth embodiment;

FIG. 84 is a cross-sectional view showing the wiring pattern forming method of the eleventh embodiment.

FIG. 85 is a cross-sectional view showing a wiring pattern forming method according to the eleventh embodiment;

FIG. 86 is a cross-sectional view showing the wiring pattern forming method according to the eleventh embodiment;

FIG. 87 is a cross-sectional view showing the wiring pattern forming method according to the eleventh embodiment;

FIG. 88 is a cross-sectional view showing the wiring pattern forming method according to the eleventh embodiment;

FIG. 89 is a cross-sectional view showing the wiring pattern forming method of the eleventh embodiment.

FIG. 90 is a cross-sectional view showing the wiring pattern forming method according to the eleventh embodiment;

FIG. 91 is a cross-sectional view showing the wiring pattern forming method according to the eleventh embodiment;

FIG. 92 is a cross-sectional view showing the wiring pattern forming method according to the eleventh embodiment;

FIG. 93 is a cross sectional view showing the wiring pattern forming method of the eleventh embodiment;

FIG. 94 is a cross-sectional view showing a wiring pattern forming method according to the eleventh embodiment;

FIG. 95 is a cross-sectional view showing a gate pattern forming step of Embodiment 12;

FIG. 96 is a cross-sectional view showing a gate pattern forming step of Embodiment 12;

FIG. 97 is a cross sectional view showing a gate pattern forming step of Embodiment 12;

FIG. 98 is a cross sectional view showing a gate pattern forming step of Embodiment 12;

FIG. 99 is a cross-sectional view showing a gate pattern forming step of Embodiment 12;

FIG. 100 is a graph showing the relationship between ion implantation energy and average range distance.

[Explanation of symbols]

1 silicon substrate, 2 polysilicon layer, 2a polysilicon pattern, 3,22 silicon nitride film, 3a silicon nitride pattern, 4,14,25,29,31,3
4 Photoresist film, 4a-4f, 4m, 14b, 1
7, 25a, 25c, 25d, 27a, 27c, 27
d, 29a, 31a, 31c to 31f, 34a, 34
c, 34d resist pattern, 5, 5a, 5b, 5
m, 26 reticle, 6,19 laser, 8,24
Silicon oxynitride film, 9, 12, 13, 15, 23
Silicon oxide film, 10 metal film, 11 organic BARC
Film, 16 aluminum layers, 19 mark formation area, A1 memory cell area, A2 peripheral circuit area.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) G03F 7/40 521 H01L 21/30 570 H01L 21/3065 574 21/3213 21/302 J 21/768 21 / 88 C 21/90 PF term (reference) 2H025 AA00 AA09 AB16 AC01 AC08 AD03 DA11 DA34 DA40 FA03 FA12 FA17 FA29 FA30 FA39 FA41 2H096 AA00 AA25 BA09 CA05 CA06 EA02 EA05 GA08 HA01 HA03 HA23 HA30 JA04 KA02 KA16 LA16 5F004 A DA23 DA26 DB02 DB03 DB07 EA03 EA06 EB02 FA02 5F033 HH04 HH07 HH08 HH19 LL07 PP15 QQ02 QQ04 QQ13 QQ26 QQ28 QQ29 QQ30 RR04 RR06 RR08 SS15 VV06 VV16 XX01 XX03 XX33 5F046 AA28 PA07

Claims (18)

[Claims] 1) forming an etching target on a semiconductor substrate; (b) forming a first resist on the etching target; and (c) patterning the first resist. (D) ion-implanting the first resist pattern, and the step (d) of ion-implanting the first resist pattern. The film thickness shrinks, and (e) a predetermined etching process is performed on the etching target using the first resist pattern after the execution of the steps (c) and (d) as a mask, thereby forming a processing pattern. Obtaining the first resist pattern after performing the step (d), wherein the film thickness of the first resist pattern is formed between a dense pattern portion and a sparse pattern portion in the processed pattern. Difference in dimensional deviation with respect to the first resist pattern of turns is equal to or less than a predetermined reference, and wherein the predetermined set to a thickness which satisfies the condition that no hindrance to the etching process, a method of manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the object to be etched includes an actual object to be etched and an ion blocking film, and the step (a) comprises: Forming the actual etching object on a substrate; and (a-2) forming the ion blocking film on the actual etching object, wherein the ion implantation of the step (d) is performed by a first step. A method of manufacturing a semiconductor device, comprising: ion implantation from above a resist pattern, wherein the ion blocking film prevents ions implanted in the step (d) from being implanted into the actual etching target. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the ion blocking film includes a silicon nitride film or a silicon nitride oxide film, and the step (a-2) uses a plasma CVD method. A method for manufacturing a semiconductor device, comprising a step of forming the ion blocking film. 4. The method of manufacturing a semiconductor device according to claim 2, wherein said ion blocking film includes an organic anti-reflection film. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the step (a) further includes: (a-3) implanting ions into the organic antireflection film, which is the ion blocking film. , A method of manufacturing a semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the object to be etched includes first and second processing regions, (F) forming a second resist on at least the second processing area after the step (d), wherein the resist pattern includes a pattern for an etching mask in the first processing area; ) Patterning the second resist to form the second resist
Obtaining a second resist pattern for an etching mask in the processing region, wherein the step (e) uses the second resist pattern as a mask in addition to the first resist pattern to perform the predetermined etching. A method for manufacturing a semiconductor device, comprising a step of executing a process. 7. The method of manufacturing a semiconductor device according to claim 6, wherein in the step (f), the second resist is formed on an entire surface of the etching target including the first resist pattern. The first resist pattern is formed by the composition change caused by the ion implantation of the step (d).
(g) A method for manufacturing a semiconductor device which is not substantially removed at the time of execution. 8. The method for manufacturing a semiconductor device according to claim 1, wherein the ion implantation in the step (d) includes an ion implantation performed obliquely with respect to a perpendicular to a surface on which the first resist pattern is formed. , A method of manufacturing a semiconductor device. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the object to be etched has an uneven shape on a surface, and (h) ions are applied to the object to be etched before performing the step (b). A method of manufacturing a semiconductor device, further comprising a step of implanting a semiconductor. 10. The method of manufacturing a semiconductor device according to claim 9, wherein, in the step (b), after the first resist is exposed through a reticle having a predetermined pattern, a developing process is performed. Thereby obtaining the first resist pattern. 11. The method for manufacturing a semiconductor device according to claim 9, wherein the object to be etched has a mark for superimposing a mask on a surface thereof. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the step (h) comprises: (h-1) forming a third resist on the object to be etched; 2) patterning the third resist so that an opening is formed on a mark forming region including the mark to obtain a third resist pattern; (h-3) the third resist Implanting ions into the mark formation region of the etching target using a pattern as a mask. 13. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation in the step (d) includes a plurality of partial ion implantations having different implantation energies. 14. (a) forming an etching target on a semiconductor substrate; (b) forming a first resist on the etching target; and (c) patterning the first resist. (D) performing a chemical reaction accelerating process for accelerating a decomposition reaction on the first resist pattern; and (e) performing a chemical reaction accelerating process on the first resist pattern. Performing a curing process including one of ion implantation, electron beam irradiation, and ultraviolet irradiation, and the curing process of the step (e) reduces the film thickness of the first resist pattern. (F) performing a predetermined etching process on the etching target using the first resist pattern after the execution of the steps (c) to (e) as a mask to obtain a processed pattern; Step further comprises a method of manufacturing a semiconductor device. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the object to be etched includes first and second processing regions, and the first resist pattern is an etching of the first processing region. Including a pattern for a mask, (g) forming a second resist on at least the second processing area after the step (e), and (h) patterning the second resist, The second
Obtaining a second resist pattern for an etching mask in the processing region of (a), wherein the step (f) comprises: using the second resist pattern as a mask in addition to the first resist pattern to perform the predetermined etching. A method for manufacturing a semiconductor device, comprising a step of executing a process. 16. The method of manufacturing a semiconductor device according to claim 15, wherein: (i) the step is performed before the step (f) and after the step (h), and at least for the second resist pattern. Performing a chemical reaction accelerating process for accelerating the decomposition reaction; and Performing a process. 17. The method according to claim 14, wherein
The method for manufacturing a semiconductor device according to claim 1, wherein the chemical reaction accelerating process includes at least one of an exposure process and a heat treatment for an object. 18. The method according to claim 18, wherein (a) the first and second
(B) forming a first resist on the etching target; and (c) patterning the first resist to form the first resist on the first resist.
Obtaining a first resist pattern on the processing region of (a), and (d) performing a curing process including one of ion implantation, electron beam irradiation, and ultraviolet irradiation on the first resist pattern. The curing process of the step (d) causes the film thickness of the first resist pattern to shrink, and Forming a resist; and (f) patterning the second resist to form the second resist.
And (g) performing a predetermined etching process on the etching target using the first and second resist patterns as masks. And further comprising a step of obtaining a processing pattern.