JP2004134553A - Process for forming resist pattern and process for fabricating semiconductor device - Google Patents

Process for forming resist pattern and process for fabricating semiconductor device Download PDF

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JP2004134553A
JP2004134553A JP2002297083A JP2002297083A JP2004134553A JP 2004134553 A JP2004134553 A JP 2004134553A JP 2002297083 A JP2002297083 A JP 2002297083A JP 2002297083 A JP2002297083 A JP 2002297083A JP 2004134553 A JP2004134553 A JP 2004134553A
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resist pattern
pattern
resist
forming
line width
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Hiroyuki Nakano
中野 博之
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Sony Corp
ソニー株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a process for forming a resist pattern having a trimming step of novel arrangement.
SOLUTION: A resist film 16 is deposited on an underlying film 14 deposited on a wafer 12. A resist material exhibiting such properties as the line width of a resist pattern shrinks through irradiation with an electron beam is used. The resist film is subjected to exposure processing according to a conventional method and then developed to form a resist pattern 18 of a specified line width. Subsequently, the resist pattern 18 is irradiated with an electron beam at an irradiation energy of 100eV-500keV to shrink the line width of the resist pattern 18 thus forming a resist pattern 20 having a shrunk line width. Relation between the level and exposure time of irradiation energy and the shrinkage of line width is established previously, and the level and exposure time of irradiation energy are determined depending on a desired shrinkage width. Finally, the underlying film 14 is etched using the resist pattern 20 having a shrunk line width as a mask thus forming an underlying film pattern 22.
COPYRIGHT: (C)2004,JPO

Description

【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明は、レジストパターンの形成方法及び半導体装置の製造方法に関し、更に詳細には、新規な構成のトリミング手法を適用したレジストパターンの形成方法及び半導体装置の製造方法に関するものである。 The present invention relates to a method of manufacturing a forming method and a semiconductor device of the resist pattern, and more particularly, to a method for manufacturing a forming method and a semiconductor device of a resist pattern applying the trimming method of the new configuration.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
近年、半導体装置の高集積化及びチップサイズの縮小化に伴い、半導体装置を構成する配線等の構成要素の一層の微細化が必要になって来ている。 In recent years, with high integration and reduction in chip size of the semiconductor device, further miniaturization of components such as a wiring constituting the semiconductor device have become necessary.
半導体装置の構成要素、例えばゲート層、コンタクト層、配線層のパターニングに必要なレジストパターンを形成するリソグラフィ処理の際では、現在は、露光光としてKrF、ArFなどを使った光露光が中心であるものの、将来、微細化の要請に応じて、回路パターンの線幅が100nm以下になったときのパターニングに必要な光リソグラフィとして、F 等の光露光技術、電子線露光技術、X線露光技術、EUV(極紫外光)などを適用した様々な露光方式が提案されている。 Components of the semiconductor device, for example, a gate layer, a contact layer, at the time of lithography process for forming a resist pattern required for patterning the wiring layer is present, light exposure is at the center using KrF, ArF or the like as an exposure light although the future, at the request of the miniaturization, as optical lithography required patterning when the line width of the circuit pattern becomes 100nm or less, F 2, etc. of the optical exposure technique, an electron beam exposure technique, X-rays exposure technique , various exposure methods of applying such EUV (extreme ultraviolet light) has been proposed.
【0003】 [0003]
本来であれば、光リソグラフィの延長という観点から、F が本命になりそうなものであるが、露光装置の部品に対する透過率の低さ、また157nmという短波長であるが故に空気中で吸収され易いこと、157nmという波長における材料の複屈折によるレンズ設計の困難さ等の理由から、従来の光学系をそのまま利用して露光装置を構成することが難しい。 If originally absorbed from the viewpoint of extension of optical lithography, but F 2 are those likely become the favorite, the transmittance of the low relative components of the exposure apparatus, and in is a short wavelength because the air that 157nm it tends to be, because of difficulties such lens design due to the birefringence of the material at the wavelength of 157 nm, it is difficult to configure the exposure apparatus using the conventional optical system as it is. その結果、F による光露光技術は、次世代の露光技術の1候補としての位置付けで開発が進められている。 As a result, light exposure technique using F 2 is developed in position as first candidate for the next generation exposure technology has been promoted.
【0004】 [0004]
電子線露光技術は、現状開発が進められている直描方式に加えて、4倍のマスクを縮小露光するEBステッパーも開発されている。 Electron beam exposure technique, in addition to the direct drawing type current has been developed, has been developed EB stepper to reduce exposure to 4-fold mask.
更には、1998年、Takao Utsumi 氏が考案し、特許公報2951947号に開示された、低エネルギー電子ビームのリソグラフィ技術の開発もはじまっている。 Furthermore, 1998, invented by Mr. Takao Utsumi, disclosed in Japanese Patent Publication 2,951,947, have also begun developing lithography low energy electron beam. Takao Utsumi 氏の考案による方式は、2keV程度の加速電圧を用いて、等倍のステンシルマスクで近接露光するという方式で線幅100nm以降の半導体装置のパターニングのための有力な方式として注目されている。 Method according to the invention of Mr. takao Utsumi, using an acceleration voltage of about 2 keV, has attracted attention as an effective method for patterning a semiconductor device having a line width of 100nm and later in a manner that proximity exposure at the same magnification of the stencil mask .
また、EUVは、日本ではASETが中心となり開発が進められている。 Furthermore, EUV is, in Japan has been developed become the center of ASET.
以上のように、様々な露光方式が線幅100nm以下の次世代リソグラフィ技術の候補として考えられているものの、それらは、未だ、本命の技術を決定できず、実用化されるに到っていない。 As described above, although various exposure methods have been considered as candidates for the following next-generation lithography technology linewidth 100 nm, they are still not able to determine the favorite techniques, not led to the practical use .
【0005】 [0005]
そこで、露光方式の開発とは別に、微小な線幅のレジストパターンを形成する方法として、レジストパターンをアッシングしてパターンを細らせるトリミングという手法が、現在、幅広く用いられている。 Therefore, apart from the development of the exposure system, as a method for forming a resist pattern of fine linewidth, technique of trimming of thinning the pattern a resist pattern by ashing, are currently widely used.
トリミング方法では、フォトレジスト膜にパターンを転写してレジストパターンを形成した後、レジストパターンにアッシング処理を施して所望の線幅までレジストパターンの線幅を細らせ、その縮小した線幅のレジストパターンをマスクとして下地層のエッチング加工を行っている。 The trimming method, after forming a resist pattern by transferring the pattern into the photoresist film, the resist pattern is subjected to ashing so thinning the line width of the resist pattern to the desired line width, registration of the reduced linewidth It is performed etching of the underlying layer pattern as a mask.
【0006】 [0006]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
しかし、従来のトリミング方法には、以下の問題があった。 However, the conventional trimming method, there has been less of a problem. つまり、第1の問題は、半導体装置のパターンの微細化に伴い、ウエハ全面にトリミング処理を施しても、レジストパターンの線幅をウエハ面内均一に縮小させることが難しいということである。 That is, the first problem is due to the miniaturization of patterns of semiconductor devices, be subjected to a trimming process on the entire surface of the wafer, that it is difficult to reduce the line width of the resist pattern in uniform wafer surface. また、第2の問題は、トリミング処理の効果がパターン形状に依存するために、レジストパターンの線幅縮小を制御性良く行うことが難しいということ、第3には、局所的なパターンの縮小が不可能なことである。 The second problem is that the effect of the trimming process is dependent on the pattern shape, that it is difficult to perform the line narrowing of the resist pattern with good controllability, the third, the reduction of local pattern it is impossible.
【0007】 [0007]
そこで、本発明の目的は、新規な構成のトリミング処理工程を有するレジストパターンの形成方法、及び半導体装置の製造方法を提供することである。 An object of the present invention is to provide a method for forming a resist pattern having a trimming step of novel structure, and a method of manufacturing a semiconductor device.
【0008】 [0008]
【課題を解決するための手段】 In order to solve the problems]
本発明者は、新規な構成のトリミング処理工程を開発する過程で、現在、半導体装置の製造工程で、レジストパターン形成用のレジスト樹脂として主に使用されている、PHS系、アクリル系、COMA系などのうちの一部のレジスト材は、電子線を照射することによりレジストパターンの線幅が細る、つまり縮幅するという現象が生じることに注目した。 The present inventors in the course of developing the trimming process of the novel structure, the current, in the manufacturing process of a semiconductor device, as a resist resin for a resist pattern formed are mainly used, PHS type, acrylic type, COMA system part of the resist material of such as the line width of the resist pattern by irradiating an electron beam is thinned, that is focused on the phenomenon that width reduction. 現実に、形成したレジストパターンの線幅測定を走査型電子顕微鏡(SEM)により行おうとしても、レジストパターンの線幅が縮小するために、実際のレジストパターンの線幅を測定することができないといった事態も生じている。 In reality, also the line width measurement of the formed resist pattern as attempted by a scanning electron microscope (SEM), for the line width of the resist pattern is reduced, say that it is not possible to measure the line width of the actual resist pattern situation also occurred.
【0009】 [0009]
本発明者は、電子線の照射による収縮するレジスト材を用いてレジストパターンを形成し、実験等により予め確立した、電子線のエネルギー・レベル及び照射時間とレジストパターンの縮小幅との関係に基づいて、次いで電子線を照射させてレジストパターンの線幅を縮小させることを着想し、試験によりこの着想の有効性を確認して、本発明を発明するに到った。 The present inventors, a resist pattern is formed by using a resist material which shrinks due to the irradiation of electron beam, established in advance by experiment or the like, based on the relationship between the energy levels and irradiation reduced width of the time and the resist pattern of the electron beam Te, then conceived that reducing the line width of the resist pattern by electron beam irradiation, to verify the validity of this concept by the test, were led to the invention of the present invention.
【0010】 [0010]
上記目的を達成するために、上述の知見に基づいて、本発明に係るレジストパターンの形成方法(以下、第1の発明方法と言う)は、ウエハ上に成膜された被加工層を加工する際に用いるレジストパターンの形成方法であって、 To achieve the above object, on the basis of the above findings, the resist pattern forming method according to the present invention (hereinafter, referred to as a first inventive method) are processed layer to be processed which is formed on the wafer a method for forming a resist pattern for use in,
電子線照射により収縮する性質を有するレジスト材からなるレジスト膜を被加工層上に成膜する工程と、 A step of forming a resist film composed of a resist material having the property of shrinking by electron beam irradiation onto the processed layer,
レジスト膜にリソグラフィ処理を施して一次レジストパターンを形成する工程と、 Forming a primary resist pattern is subjected to lithography processing the resist film,
一次レジストパターンに電子線を照射して収縮させ、パターン幅の狭い二次レジストパターンを形成する工程とを有することを特徴としている。 By irradiating an electron beam to the primary resist pattern is shrunk, it is characterized by a step of forming a narrow secondary resist pattern of the pattern width.
【0011】 [0011]
本発明方法で、加工とは、エッチング等の加工プロセスのみならず、イオン注入等の処理プロセスをも含む概念である。 In the present invention method, the processing and not only machining process such as etching is a concept including the processes such as ion implantation. 被加工層とは、エッチング等により加工される被加工層に限らず、イオン注入処理される被処理層をも含む概念である。 The layer to be processed is not limited to the processed layer to be processed by etching or the like, it is a concept including a processed layer to be ion-implantation process. 被加工層には絶縁膜上に形成された配線層等があり、被処理層には基板に形成する拡散層等がある。 The layer to be processed has such a wiring layer formed on the insulating film, the processed layer is a diffusion layer or the like to be formed on the substrate.
本発明方法で使用するレジスト材は、電子線照射により収縮する性質を有するレジスト材である限り、電子線照射により感光するレジスト材である必要はなく、光照射により感光するフォトレジスト材でも良い。 Resist material used in the method of the present invention, as long as a resist material having the property of shrinking by electron beam irradiation, not necessarily a resist material which is sensitive by electron beam irradiation, may be a photoresist material that is sensitive by light irradiation.
【0012】 [0012]
本発明方法の一次レジストパターンを形成する工程では、設計データに基づいて既知の露光方法によりレジスト膜にリソグラフィ処理を施する。 In the step of forming a primary resist pattern of the present invention method, a lithographic process on the resist film by a known exposure method based on the design data Hodokosuru. リソグラフィ処理はレジスト材に応じて光照射でも電子線照射でも良い。 The lithographic process may be electron beam irradiation in the light irradiation depending on the resist material.
本発明方法では、実験等により予め確立した、電子線のエネルギー・レベル及び照射時間と、レジストパターンの縮小幅との関係に基づいて、一次レジストパターンに電子線を照射して収縮させ、パターン幅の狭い所望の二次レジストパターンを形成する。 In the method of the invention, pre-established by experiments or the like, and the energy level and irradiation time of the electron beam, based on the relationship between the reduction width of the resist pattern, it is shrunk by irradiating an electron beam to the primary resist pattern, pattern width forming a narrow desired secondary resist pattern. 電子線の照射エネルギーは、例えば1keV以上500keV以下である。 The irradiation energy of the electron beam is, for example 1keV or 500keV or less.
【0013】 [0013]
電子線はウエハ面上に均一に照射することができ、しかも、電子線のエネルギー・レベル及び照射時間を正確に調節して電子線の強度を制御することが可能であるから、パターンの疎密及びパターンサイズの制約なく、レジストパターンのより高精度な線幅制御が可能である。 Electron beam can be uniformly irradiated on the wafer surface, moreover, since it is possible to control the intensity of the electron beam to accurately adjust the energy level and irradiation time of the electron beam, the pattern density and without limitation of pattern size, it is possible to more accurate linewidth control of the resist pattern.
本発明方法を適用することにより、150nm以下の微細なレジストパターンを高い線幅均一性及び良好な面内均一性のもとで実現することができる。 By applying the present invention method, it is possible to realize the following fine resist pattern 150nm under high line width uniformity and good surface uniformity.
【0014】 [0014]
本発明方法は、光リソグラフィのみならず他のリソグラフィ技術、例えばEB、X線、EUVによりリソグラフィ処理によりレジストパターンを形成する際にも適用できる。 The present invention, other lithographic techniques not photolithography only, applicable for example EB, X-ray, even when forming a resist pattern by lithography process by EUV.
更には、レジストパターンの形成である限り、半導体装置の製造以外の分野でも適用することができる。 Furthermore, as long as the formation of the resist pattern it can also be applied in fields other than the production of semiconductor devices. また、本発明方法によれば、段差基板上にも高精度で線幅の細いレジストパターンを作製することができる。 Further, according to the present invention, it is possible to produce a thin resist pattern line width even in a high precision on a stepped substrate.
【0015】 [0015]
線幅が縮小した二次レジストパターンを形成した際、二次レジストパターンと被加工層との境界面では、二次レジストパターンの最下層部分は、被加工層と比較的強固に密着しているために被加工層に引っ張られ、二次レジストパターンの開口内の被加工層上に薄く裾を引いた状態で残る。 When the line width to form a reduced secondary resist pattern, at the boundary surface between the secondary resist pattern and the work layer, the lowermost portion of the secondary resist pattern is relatively strongly adhered to the layer to be processed It pulled the processed layer to remain in a state of pulling the thin skirt onto the processed layer in the opening of the secondary resist pattern.
二次レジストパターンの開口内の被加工層上の最下層部分は、通常、二次レジストパターンをマスクにして被加工層をエッチングした際、エッチングの初期に除去されるので、エッチング加工上での問題は小さいものの、裾を引いた最下層部分が残存しないパターンを形成することが望ましい。 Lowermost portion on the layer to be processed in the opening of the secondary resist pattern is typically when etching the layer to be processed as a mask secondary resist pattern, since it is removed early in the etching on etching although the problem is small, it is desirable that the lowermost portion minus the hem to form a pattern does not remain.
【0016】 [0016]
そこで、本発明方法の好適な実施態様では、二次レジストパターンを用いて被加工層に加工処理を施す前に、二次レジストパターンにO プラズマ処理を施して、被加工層上に延在する二次レジストパターンの最下層部分を除去する。 Therefore, in the preferred embodiments of the method, the secondary resist pattern using before applying a processing layer to be processed, it is subjected to O 2 plasma treatment to the secondary resist pattern, extending over the layer to be processed removing the lowermost portion of the secondary resist pattern. プラズマ処理の所要時間は、10秒以上60秒以下である。 O 2 plasma treatment time required is 60 seconds or less 10 seconds or more.
これにより、良好な断面形状を備えたレジストパターンを形成することができる。 Thus, it is possible to form a resist pattern having a good sectional shape.
【0017】 [0017]
通常、半導体装置の製造過程では、リソグラフィ処理を施す際、マスクを原版として露光を行う。 Usually, in the manufacturing process of the semiconductor device, when performing a lithography process, and an exposure mask as an original. マスクはパターンサイズが小さくなればなるほど高価になりしかも、マスクパターンの最小線幅の広狭で、マスクの価格が決定される。 Mask becomes expensive as becomes smaller the pattern size Moreover, in wide and narrow of the minimum line width of the mask pattern, the price of the mask is determined. 例えば、マスクの極く一部の微小領域に線幅が小さいパターンが必要であるときには、マスク領域の一部に必要な線幅の小さなパターンの影響で、マスクコストが高騰する。 For example, when the line width small fraction of a minute region of the mask is required pattern is small, the influence of a small pattern having a line width required for a portion of the mask region, the mask cost is high.
また、メモリー回路とロジック回路が混載された混載LSIの作製プロセスなどでは、メモリー回路とロジック回路との間でデザインルールが異なり、ロジック回路の一部の領域の線幅が細いことが多い。 Further, like in the manufacturing process of the hybrid memory circuit and logic circuit are embedded LSI, different design rule between the memory circuit and the logic circuit, it is often the line width of the partial region of the logic circuit is narrow.
そこで、本発明者は、線幅の小さいレジストパターンを必要とする領域のみに電子線を照射してレジストパターンの線幅を縮小させることを着想し、次の第2の発明方法を発明するに到った。 The present inventors have conceived that by irradiating an electron beam only to the area in need of small resist pattern line width reducing the line width of the resist pattern, to invent the next second inventive method led was.
【0018】 [0018]
本発明に係る半導体装置の製造方法(以下、第2の発明方法と言う)は、線幅が比較的大きい第1の回路パターンと第1の回路パターンより線幅が小さい第2の回路パターンとが領域別に混在する半導体装置の製造方法において、半導体装置形成用のウエハ上に成膜された被加工層を加工する際に用いるレジストパターンを形成する際、 The method of manufacturing a semiconductor device according to the present invention (hereinafter, referred to as a second invention method) has a line width is relatively large first circuit pattern and second circuit pattern than a line width smaller first circuit pattern There method of manufacturing a semiconductor device mixed in each region, when forming a resist pattern to be used for processing the layer to be processed which is formed on a wafer for semiconductor device formation,
電子線照射により収縮する性質を有するレジスト材からなるレジスト膜を被加工層上に成膜する工程と、 A step of forming a resist film composed of a resist material having the property of shrinking by electron beam irradiation onto the processed layer,
レジスト膜にリソグラフィ処理を施して一次レジストパターンを形成する工程と、 Forming a primary resist pattern is subjected to lithography processing the resist film,
第2の回路パターンが形成される領域のみに電子線を照射して一次レジストパターンの線幅を収縮させ、パターン幅の狭い二次レジストパターンを形成する工程とを有することを特徴としている。 Only in the region where the second circuit pattern is formed is contracted the line width of the primary resist pattern by irradiating an electron beam, it is characterized by a step of forming a narrow secondary resist pattern of the pattern width.
【0019】 [0019]
本発明方法では、線幅の小さい第2の回路パターンの領域のみに電子線照射処理を行うことにより、マスクのコストを低減し、かつ電子線照射の作業能率を高め、パターン形成のコストを節減することができる。 In the method of the present invention, by performing the electron beam irradiation treatment only in the region of the smaller second circuit pattern line width, reducing the cost of the mask, and enhance the work efficiency of the electron beam irradiation, saving the cost of pattern formation can do.
【0020】 [0020]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
以下に、添付図面を参照し、実施形態例を挙げて本発明の実施の形態を具体的かつ詳細に説明する。 Hereinafter, with reference to the accompanying drawings, by way of example embodiments will be described an embodiment of the specific and detailed the present invention.
実施形態例1 Embodiment 1
本実施形態例は、第1の発明方法に係る露光方法の実施形態の一例であって、図1(a)から(d)は、それぞれ、本実施形態例の方法に従ってレジストパターンを形成する際の各工程の基板断面図である。 This embodiment is an example of an embodiment of an exposure method according to the first inventive method, FIG. 1 from (a) (d), respectively, when forming a resist pattern according to the method of this embodiment it is a substrate cross-sectional view of the steps of.
先ず、図1(a)に示すように、ウエハ12の下地膜14上に膜厚50nmから3μmのレジスト膜16を成膜する。 First, as shown in FIG. 1 (a), a resist film 16 of 3μm film thickness 50nm over the base film 14 of the wafer 12.
レジストには、電子線の照射によりレジストパターンの線幅が縮小する性質を有するレジスト材料を用いる。 The resist, using a resist material having a property of line width of the resist pattern is reduced by irradiation of an electron beam. レジスト膜の膜厚は、通常、50nm〜3μmの範囲で用いられ、微細な最先端リソグラフィ処理では、500nm以下の膜厚を用いることが多い。 Thick resist film is generally used in a range of 50Nm~3myuemu, a fine cutting edge lithography process, it is often used a film thickness equal to or less than 500 nm. 本実施形態例では、レジスト膜の膜厚は、100nmである。 In the present embodiment, the thickness of the resist film is 100 nm.
次いで、図1(b)に示すように、従来の方法に従ってレジスト膜に露光処理を施し、現像して、所定線幅のレジストパターン18を形成する。 Then, as shown in FIG. 1 (b), subjected to exposure treatment on the resist film in accordance with conventional methods, and developed to form a resist pattern 18 having a predetermined line width.
【0021】 [0021]
続いて、図1(c)に示すように、レジストパターン18に100eV以上500keV以下の照射エネルギーで電子線を30秒間の露光時間で照射して、レジストパターン18の線幅を縮小させ、線幅が縮小したレジストパターン20を形成する。 Subsequently, as shown in FIG. 1 (c), resist pattern 18 with an electron beam at 500keV following irradiation energy than 100eV was irradiated for 30 seconds exposure time, to reduce the line width of the resist pattern 18, the line width There is formed a resist pattern 20 with a reduced.
照射エネルギーのレベル及び露光時間と線幅の縮小幅との関係を予め確立しておき、所望の縮小幅に応じて照射エネルギーのレベル及び露光時間を定める。 Leave establish the relationship between the reduction width of the level and the exposure time and the line width of the radiation energy in advance, determining the level and exposure time of the radiation energy depending on the desired reduced-width. 本実施形態例の具体例では、レジストパターン18に1keVの照射エネルギーで電子線を30秒間の露光時間で照射して、レジストパターン18の線幅を20nmだけ縮小させることができた。 In embodiments of the present embodiment, the electron beam irradiation energy of 1keV the resist pattern 18 was irradiated for 30 seconds exposure time, the line width of the resist pattern 18 could be reduced by 20 nm.
次いで、図1(d)に示すように、線幅が縮小したレジストパターン20をマスクとして下地膜14をエッチングして、下地膜パターン22を形成する。 Then, as shown in FIG. 1 (d), a base film 14, a resist pattern 20 where the line width is reduced as a mask is etched to form a base film pattern 22.
【0022】 [0022]
以上の工程を経て、線幅の狭い下地膜パターン22を下地膜14上に形成することができる。 Through the above steps, a narrow underlying film pattern 22 having a line width can be formed over the base film 14. 照射時間を制御することによりレジストパターンのトリミング量を制御することがが可能となる。 Is possible to control the amount of trimming of the resist pattern becomes possible by controlling the irradiation time.
【0023】 [0023]
実施形態例2 Embodiment 2
本実施形態例は、第1の発明方法に係る露光方法の実施形態の別の例である。 This embodiment is another example of an embodiment of an exposure method according to the first inventive method. 図2(a)及び(b)は、それぞれ、本実施形態例の方法に従ってレジストパターンを形成する際の工程の基板断面図である。 2 (a) and (b) are respectively a substrate cross-sectional view illustrating a process for forming the resist pattern in accordance with the method of this embodiment.
実施形態例1で、図1(c)に示すように、電子線をレジストパターン18に照射して、線幅が縮小したレジストパターン20を形成した際、レジストパターン20と下地膜14との境界面では、レジストパターン20の最下層部分24は、下地膜14と比較的強固に密着しているために下地膜14に引っ張られ、図2(a)に示すように、レジストパターン20の開口26内の下地膜14上に薄く裾を引いた状態で残る。 In Embodiment 1, as shown in FIG. 1 (c), the boundary of irradiating an electron beam on the resist pattern 18, when forming a resist pattern 20 where the line width is reduced, a resist pattern 20 and the base film 14 in terms, the lowermost portion 24 of the resist pattern 20 is pulled in the base film 14 to have relatively firmly adhered to the base film 14, as shown in FIG. 2 (a), the resist pattern 20 opening 26 remain in a state in which the base film 14 minus the thin hem on the inside.
【0024】 [0024]
レジストパターン20の開口26内の最下層部分24は、通常、レジストパターン20をマスクにして下地膜14をエッチングした際、エッチングの初期に除去されるので、エッチング加工上での問題は小さいものの、薄く裾を引いた最下層部分24が残存しないパターンを形成することが望ましい。 Lowermost portion 24 of the opening 26 of the resist pattern 20 is typically when the resist pattern 20 by etching the underlayer film 14 as a mask, so is removed early in the etching, although the problems on etching is small, it is desirable to thin the lowermost portion 24 minus the hem to form a pattern does not remain.
そこで、本実施形態例では、下地膜14をエッチングする際、先ず、O ガスによるプラズマ処理を10秒以上60秒以下程度の間レジストパターン20に施して、薄く裾を引いた状態で残る最下層部分24を除去する。 Therefore, in this embodiment, when etching the underlying film 14, first, subjected to O 2 during the degree plasma treatment following 60 seconds 10 seconds Gas resist pattern 20, remains in a state of pulling the thin skirt top removing the lower portion 24.
これにより、図2(a)に示すように、薄く裾を引いた部分を有しない良好な断面形状のレジストパターン20を形成することができる。 Thus, it is possible to form the FIG. 2 (a), a resist pattern 20 of a good cross-sectional shape having no minus thin foot.
【0025】 [0025]
実施形態例3 Embodiment Example 3
本実施形態例は第2の発明に係る半導体装置の製造方法の実施形態の一例である。 This embodiment is an example embodiment of a method of manufacturing a semiconductor device according to the second invention. 図3(a)及び(b)は、それぞれ、本実施形態例の半導体装置の製造方法を説明する概念図であって、図3(a)はウエハ上の1ショットの領域を示し、図3(b)は図3(a)の1ショットの領域の拡大図である。 3 (a) and (b) are respectively a conceptual diagram illustrating a method of manufacturing a semiconductor device of the embodiment, FIG. 3 (a) shows one shot area on the wafer, FIG. 3 (b) is an enlarged view of a shot area in FIG. 3 (a).
本実施形態例では、線幅の比較的大きい第1の回路パターン、例えばメモリー回路と、第1の回路パターンより線幅の小さい第2の回路パターン、例えばロジック回路とが領域別に混在する混載LSIを製造する際のレジストパターンを形成する。 In the present embodiment, a relatively large first circuit pattern, for example memory circuits and, mixed LSI smaller second circuit pattern having a line width than that of the first circuit pattern, for example, where the logic circuit mixed in each region of the line width forming a resist pattern in manufacturing.
【0026】 [0026]
本実施形態例では、図3(a)に示すように、ウエハ28の1ショットの領域30のうち、図3(b)に示すように、メモリー領域32のメモリー回路に比べて回路パターンの線幅が細いロジック回路のロジック領域34のみに実施形態例1で説明した電子線照射を行い、細い線幅のレジストパターンを形成する。 In the present embodiment, as shown in FIG. 3 (a), of one shot area 30 of the wafer 28, as shown in FIG. 3 (b), the line of the circuit pattern than the memory circuit of the memory area 32 perform electron beam irradiation described only in the logic region 34 having a width narrow logic circuit in embodiment 1, to form a resist pattern of the thin line width.
これにより、電子線照射の領域を限定して、照射作業の効率を高め、緩いルールのマスクを使用することにより高騰するマスク費用を低減することが可能となり、パターン形成のコストを節減することができる。 Thus, by limiting the area of ​​the electron beam irradiation to increase the efficiency of irradiation operations, it is possible to reduce the mask cost of rise by using a mask of loose rule, it is reduced the cost of pattern formation it can.
また、実施形態例2で説明したように、電子線照射後、エッチング工程の前にO プラズマ処理を行ってレジストパターンの最下部の薄く裾を引いた部分を除去し、断面形状の良好なレジストパターンを形成するようにしても良い。 Further, as described in Embodiment Example 2, after the electron beam irradiation, the thin minus foot of the bottom of the resist pattern is removed by the O 2 plasma treatment prior to the etching step, a good cross-sectional shape resist pattern may be formed to.
【0027】 [0027]
【発明の効果】 【Effect of the invention】
第1の発明方法によれば、電子線照射により収縮する性質を有するレジスト材からなるレジスト膜に通常のリソグラフィ処理を施して一次レジストパターンを形成し、次いで一次レジストパターンに電子線を照射して収縮させ、パターン幅の狭い二次レジストパターンを形成することにより、パターンの疎密及びパターンサイズの制約なく、レジストパターンより高精度な線幅制御が可能である。 According to the first inventive method, the resist film composed of a resist material having the property of shrinking by electron beam irradiation is subjected to conventional lithography process to form a primary resist pattern, followed by irradiating an electron beam to the primary resist pattern deflated, by forming a narrow secondary resist pattern with a pattern width, without restriction of density and pattern size of the pattern, it is possible to highly accurate linewidth control over the resist pattern.
本発明方法を適用することにより、150nm以下の微細なレジストパターンを高い線幅均一性及び良好な面内均一性のもとで実現することができる。 By applying the present invention method, it is possible to realize the following fine resist pattern 150nm under high line width uniformity and good surface uniformity.
更には、比較的簡単なプロセスによりレジストパターンの線幅の高精度な線幅制御が可能であるから、レジストパターンの形成コストを軽減できる。 Furthermore, a relatively simple process because it is capable of high-precision line width control of the line width of the resist pattern, it can reduce the formation cost of the resist pattern.
【0028】 [0028]
第2の発明方法によれば、線幅が比較的大きい第1の回路パターンと第1の回路パターンより線幅が小さい第2の回路パターンとが領域別に混在する半導体装置の製造方法において、第2の回路パターンを形成する領域のみに第1の発明方法を適用することにより、マスクのコストを低減することができる。 According to the second inventive method, in a method of manufacturing a semiconductor device and a line width is relatively large first circuit pattern and the line width is smaller the first circuit pattern and the second circuit pattern are mixed in the each region, the by applying the first inventive method only in the region for forming the second circuit pattern, it is possible to reduce the cost of the mask.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】図1(a)から(d)は、それぞれ、実施形態例1の方法に従ってレジストパターンを形成する際の各工程の基板断面図である。 [1] Figures 1 (a) (d), respectively, is a substrate cross-sectional view of the step for forming the resist pattern according to the method of the first embodiment.
【図2】図2(a)及び(b)は、それぞれ、実施形態例2の方法に従ってレジストパターンを形成する際の工程の基板断面図である。 [2] Figure 2 (a) and (b) are respectively a substrate cross-sectional view illustrating a process for forming the resist pattern according to the method of Embodiment 2.
【図3】実施形態例3の半導体装置の製造方法を説明する概念図である。 3 is a conceptual diagram illustrating a method of manufacturing a semiconductor device of embodiment 3.
【符号の説明】 DESCRIPTION OF SYMBOLS
12……ウエハ、14……下地膜、16……レジスト膜、18……レジストパターン、20……レジストパターン、22……下地膜パターン、24……レジストパターンの最下層部分、28……ウエハ、30……1ショットの領域、32……メモリー領域、34……ロジック領域。 12 ...... wafer, 14 ...... base film, 16 ...... resist film, 18 ...... resist pattern, 20 ...... resist pattern, 22 ...... underlying film pattern, the lowermost portion of the 24 ...... resist pattern, 28 ...... wafer , 30 ...... 1 shot area, 32 ...... memory region, 34 ...... logic region.

Claims (4)

  1. ウエハ上に成膜された被加工層を加工する際に用いるレジストパターンの形成方法であって、 A method for forming a resist pattern to be used for processing the layer to be processed which is formed on the wafer,
    電子線照射により収縮する性質を有するレジスト材からなるレジスト膜を被加工層上に成膜する工程と、 A step of forming a resist film composed of a resist material having the property of shrinking by electron beam irradiation onto the processed layer,
    レジスト膜にリソグラフィ処理を施して一次レジストパターンを形成する工程と、 Forming a primary resist pattern is subjected to lithography processing the resist film,
    一次レジストパターンに電子線を照射して収縮させ、パターン幅の狭い二次レジストパターンを形成する工程とを有することを特徴とするレジストパターンの形成方法。 Primary resist pattern is irradiated to contract with an electron beam, a resist pattern formation method characterized by having a step of forming a narrow secondary resist pattern of the pattern width.
  2. 二次レジストパターンを用いて被加工層に加工処理を施す前に、二次レジストパターンにO プラズマ処理を施して、被加工層上に延在する二次レジストパターンの最下層部分を除去することを特徴とする請求項1に記載のレジストパターンの形成方法。 Before performing the processing in the layer to be processed using a secondary resist pattern, is subjected to O 2 plasma treatment to the secondary resist pattern, removing the lowermost portion of the secondary resist pattern extending over the layer to be processed the resist pattern forming process according to claim 1, characterized in that.
  3. 請求項1又は2の記載のレジストパターンの形成方法を適用してレジストパターンを形成し、 The resist pattern is formed by applying a method of forming a resist pattern according to claim 1 or 2,
    次いで、形成したレジストパターンを用いてエッチング加工又はイオン注入処理を行うことを特徴とする半導体装置の製造方法。 Then, a method of manufacturing a semiconductor device using the formed resist pattern and performing an etching process or an ion implantation process.
  4. 線幅が比較的大きい第1の回路パターンと第1の回路パターンより線幅が小さい第2の回路パターンとが領域別に混在する半導体装置の製造方法において、半導体装置形成用のウエハ上に成膜された被加工層を加工する際に用いるレジストパターンを形成する際、 The method of manufacturing a semiconductor device in which the first circuit pattern and a line width than that of the first circuit pattern having a line width is relatively large and a small second circuit pattern mixed in each region, formed on a wafer for a semiconductor device formed when forming a resist pattern to be used for processing the layer to be processed which is,
    電子線照射により収縮する性質を有するレジスト材からなるレジスト膜を被加工層上に成膜する工程と、 A step of forming a resist film composed of a resist material having the property of shrinking by electron beam irradiation onto the processed layer,
    レジスト膜にリソグラフィ処理を施して一次レジストパターンを形成する工程と、 Forming a primary resist pattern is subjected to lithography processing the resist film,
    第2の回路パターンが形成される領域のみに電子線を照射して一次レジストパターンの線幅を収縮させ、パターン幅の狭い二次レジストパターンを形成する工程とを有することを特徴とする半導体装置の製造方法。 Only in the region where the second circuit pattern is formed is contracted the line width of the primary resist pattern by irradiating an electron beam, and wherein a and a step of forming a narrow secondary resist pattern of the pattern width the method of production.
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