KR0135053B1 - Forming method of fine-pattern - Google Patents
Forming method of fine-patternInfo
- Publication number
- KR0135053B1 KR0135053B1 KR1019940009395A KR19940009395A KR0135053B1 KR 0135053 B1 KR0135053 B1 KR 0135053B1 KR 1019940009395 A KR1019940009395 A KR 1019940009395A KR 19940009395 A KR19940009395 A KR 19940009395A KR 0135053 B1 KR0135053 B1 KR 0135053B1
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- film
- photoresist
- forming
- etching
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
본 발명은 저온공정에서 형성한 CVD막 사이드월을 이용하여 공정이 간단하며, 형성된 미세패턴이 홀인 경우 홀의 측면 모양을 개선한 미세형상 형성방법에 관한 것이다.The present invention relates to a method for forming a microstructure in which the process is simple by using a CVD film sidewall formed in a low temperature process, and the side shape of the hole is improved when the formed micropattern is a hole.
본 발명은 반도체 소자 제조 공정에서 사용되는 미세형상 형성방법에 있어서, a) 하지층 위에 패턴이 형성될 패턴막을 형성하고, 패턴막 상에 포토레지스트를 코팅하고 노광 및 현상하여 포토레지스트패턴을 형성하는 단계와, b) 저온에서 CVD방식으로 박막을 증착하여 CVD막을 형성한 뒤, 에치백하여 포토레지스트패턴의 측면에 CVD막사이드월을 형성하는 단계와, c) 상기 사이드월과 포토레지스트패턴을 식각마스크로하여 하층의 패턴막을 식각하여 미세패턴을 형성하는 단계로 이루어진 미세형상 형성방법이다.The present invention relates to a method for forming a fine shape used in a semiconductor device manufacturing process, comprising: a) forming a pattern film on which a pattern is to be formed on a base layer, coating a photoresist on the pattern film, and then exposing and developing the photoresist pattern B) depositing a thin film by CVD at low temperature to form a CVD film, and then etching back to form a CVD film sidewall on the side of the photoresist pattern; and c) etching the sidewall and the photoresist pattern. A method of forming a microstructure comprising etching a lower pattern film using a mask to form a fine pattern.
Description
제1도는 종래의 미세형상 형성방법의 공정도이고,1 is a process chart of a conventional fine shape forming method,
제2도는 본 발명의 미세형상 형성방법의 제조공정도이다.2 is a manufacturing process chart of the method for forming a microshape of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11,21 : 하지층 12 : 산화막11,21: base layer 12: oxide film
13 : 제1폴리실리콘 14,24 : 포토레지스트13: first polysilicon 14,24: photoresist
15 : 제2폴리실리콘 16 : 폴리실리콘사이드월15: second polysilicon 16: polysilicon sidewall
25 : CVD막 26 : CVD막사이드월25 CVD film 26 CVD film sidewall
22 : 패턴막22: pattern film
본 발명은 반도체소자제조 공정 중에서 미세형상 형성방법에 관한 것으로서, 특히 미세 패턴을 형성함으로서 고집적 반도체소자의 생산에 적합하도록 한 미세형상 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine shape in a semiconductor device manufacturing process, and more particularly, to a method for forming a fine shape suitable for production of highly integrated semiconductor devices by forming a fine pattern.
반도체장치의 고집적화경향에 따라 소자의 사이즈를 줄이는 것이 반도체장치 제조의 관건이 되어왔다. 그런데 반도체제조공정 중에 포토리소그래피공정으로 콘텍홀 또는 비아홀 등의 홀형성을 위한 패턴을 형성하게 되는데, 이때에 사용하는 노광장치는 다음의 식에 따라 최소선폭이 결정되어 홀패턴의 크기에 한계가 존재하게 된다.Reducing the size of the device in accordance with the trend toward high integration of the semiconductor device has been a key to the manufacturing of the semiconductor device. However, during the semiconductor manufacturing process, a pattern for forming a hole, such as a contact hole or a via hole, is formed by a photolithography process. In this case, a minimum line width is determined according to the following equation, and thus the size of the hole pattern is limited. Done.
R=L·λ/ NAR = L · λ / NA
여기에서 R은 초점심도(Depth Of Focus)이고, λ는 노광장치의 파장이며, NA(Numerical Aperture)는 노광장치에 따라 주어지는 특성이고 K는 상수이다.Where R is the depth of focus, λ is the wavelength of the exposure apparatus, NA (Numerical Aperture) is a characteristic given by the exposure apparatus, and K is a constant.
종래에는 노광장치의 최소선폭보다 더 미세한 패턴을 형성하기 위하여 폴리실리콘사이드월을 이용하는 방법을 사용하였다.Conventionally, a method using a polysilicon sidewall has been used to form a pattern finer than the minimum line width of the exposure apparatus.
제1도는 종래의 미세형상 형성방법의 공정도이다.1 is a process chart of a conventional fine shape forming method.
도면을 참조로 폴리실리콘 사이드월을 이용한 미세형상 형상기술을 설명하면 다음과 같다.Referring to the drawings will be described a micro-shape shape technology using a polysilicon sidewall as follows.
제1도의 (a)와 같이 하지층(11)위에 홀을 형성할 산화막(12)을 증착하고, 산화막(12) 위에 제1폴리실리콘(13)을 증착한다.As shown in FIG. 1A, an oxide film 12 for forming holes is deposited on the base layer 11, and the first polysilicon 13 is deposited on the oxide film 12.
그 위에 포토레지스트(Photo Resist=P.R.)를 도포한 뒤, 포토리소그래피에 의하여 P.R.패턴(14)을 형성한다.After the photoresist (Photo Resist = P.R.) is applied thereon, the P.R.pattern 14 is formed by photolithography.
제1도의 (b)와 같이 P.R.패턴(14)을 마스크로하여 제1폴리실리콘(13)을 식각하여 격리영역의 제1폴리실리콘을 제거한다.As shown in FIG. 1B, the first polysilicon 13 is etched using the P.R.pattern 14 as a mask to remove the first polysilicon in the isolation region.
제1도의 (c)와 같이 P.R.패턴을 제거하고, 홀을 형성할 영역과 제1폴리실리콘 상에 제2폴리실리콘(15) 박막을 적층한다.As shown in (c) of FIG. 1, the P.R.pattern is removed, and the second polysilicon 15 thin film is laminated on the region where the hole is to be formed and the first polysilicon.
제1도의 (d)와 같이 이방성에치에 의하여 제 2 폴리실리콘(15)을 에치백하여 폴리실리콘사이드월(16)을 형성 및 홀을 형성할 부위의 산화막 표면을 개방한다.As shown in (d) of FIG. 1, the second polysilicon 15 is etched back by anisotropic etching to open the surface of the oxide film at the site where the polysilicon sidewall 16 is formed and holes are to be formed.
제1도의 (e)와 같이 폴리실리콘사이드월(16)을 마스크로하여 산화막(12)의 에치를 실시하여 노광장치의 최소선폭보다 미세한 사이즈의 홀을 형성할 수 있다.As illustrated in FIG. 1E, the oxide film 12 may be etched using the polysilicon sidewall 16 as a mask to form holes having a size smaller than the minimum line width of the exposure apparatus.
이와 같은 종래기술의 구조에서 폴리실리콘사이드월을 사용함에 의하여 노광장치의 최소선폭보다 크기가 축소되어 미세패턴이 가능하게 되었다. 그리고 폴리실리콘사이드월의 두께를 조절함으로서 미세형상 패턴의 크기조절이 가능하였고, 산화막과 폴리실리콘 간의 에치레이트 차이가 크기 때문에 산화막을 식각하여 홀을 형성할 때 폴리실리콘 박막이 식각에 대한 마스크로서 역할을 수행할 수 있었다.By using the polysilicon sidewall in the structure of the prior art as described above it is possible to reduce the size than the minimum line width of the exposure apparatus to enable a fine pattern. In addition, by controlling the thickness of the polysilicon sidewall, it was possible to control the size of the micro-shaped pattern, and because the difference in etch rate between the oxide film and the polysilicon was large, the polysilicon thin film served as a mask for etching when the hole was formed by etching the oxide film. Could be done.
그러나, 이러한 종래의 기술은 사이드월을 형성하기 위하여 제 1 및 제 2 폴리실리콘을 증착하는 공정 2회와, 에치공정 1회가 각각 추가되므로 공정수가 증가하는 문제와, 그에 따른 작업비용과 생산 시간의 증가하는 새로운 문제를 유발하였다.However, this conventional technique has a problem of increasing the number of processes since two steps of depositing the first and second polysilicon and one etch step are added to form a sidewall, respectively, and thus the operation cost and production time. Has caused a new problem of increasing.
다음으로는 폴리실리콘의 작업온도가 600℃이상인 열공정이어서 메탈공정 이후에서는 이 방법을 사용할 수 없다는 제약이 있었다.Next, there was a limitation that the method cannot be used after the metal process because the thermal process of the polysilicon temperature is more than 600 ℃.
그리고 열공정에 의하여 불순물로서 주입된 도우펀트가 확산하여 도우펀트농도를 감소시켰다.In addition, the dopant injected as an impurity by the thermal process diffused to reduce the dopant concentration.
또 식각공정 완료 후에는 산화막 위에 폴리실리콘의 잔류물이 남아있어서 소자의 신뢰도를 저하시키는 문제가 있었다.In addition, after completion of the etching process, a residue of polysilicon remained on the oxide film, thereby lowering the reliability of the device.
본 발명은 위와 같은 문제점을 개선하기 위하여 저온공정에서 형성한 CVD막 사이드월을 이용하며, 공정수도 줄이고, 형성된 미세패턴이 홀인 경우 홀의 측면 모양을 개선한 미세형상 형성방법을 제공하는 것이 본 발명의 목적이다.The present invention uses a CVD film sidewall formed in a low temperature process in order to improve the above problems, to reduce the number of processes, and to provide a method for forming a fine shape to improve the side shape of the hole when the formed micropattern is a hole of the present invention Purpose.
본 발명은 반도체 소자 제조 공정에서 사용되는 미세형상 형성방법에 있어서, 가) 하지층 위에 패턴이 형성될 패턴막을 형성하고, 패턴막 상에 포토레지스트를 코팅하고 노광 및 현상하여 포토레지스트패턴을 형성하는 단계와, 나) 저온에서 CVD 방식으로 박막을 증착하여 CVD막을 형성한 뒤, 에치백하여 포토레지스트패턴의 측면에 CVD막사이드월을 형성하는 단계와, 다) 상기 사이드월과 포토레지스트패턴을 식각마스크로하여 하층의 패턴막을 식각하여 미세패턴을 형성하는 단계로 구성한다.The present invention relates to a method for forming a fine shape used in a semiconductor device manufacturing process, comprising: a) forming a pattern film on which a pattern is to be formed on a base layer, coating a photoresist on the pattern film, and then exposing and developing the photoresist pattern (B) forming a CVD film by depositing a thin film by a CVD method at a low temperature, and then etching back to form a CVD film sidewall on the side of the photoresist pattern; and c) etching the sidewall and the photoresist pattern. The pattern layer in the lower layer is etched using a mask to form fine patterns.
제2도는 본 발명의 미세형상 형성방법에 의한 제조공정도를 도시한 것이다.2 is a manufacturing process chart according to the method for forming a microstructure of the present invention.
첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도의 (a)와 같이 하지층(21) 위에 패턴 예로서 홀이나 라인을 형성할 패턴막(22)을 형성한다. 이때 패턴막(22)은 산화막, 폴리실리콘 또는 A1등과 같은 금속 중의 하나로 형성한다.As shown in FIG. 2A, a pattern film 22 for forming holes or lines as a pattern example is formed on the base layer 21. At this time, the pattern film 22 is formed of one of metals such as oxide film, polysilicon or A1.
이러한 패턴막(22) 위에 포토레지스트를 코팅하고 노광 및 현상하여 홀을 형성할 영역의 패턴막 위의 포토레지스트를 제거하여 노관장비가 허용하는 치수로 포토레지스트패턴(24)을 형성한다.The photoresist is coated on the patterned film 22, exposed and developed to remove the photoresist on the patterned film in the region where holes are to be formed, thereby forming the photoresist pattern 24 to a size that is allowed by the furnace equipment.
다음 제2도의 (b)와 같이 250℃이하의 낮은 온도에서 CVD방식(또는 플라즈마 CVD방식)으로 박막을 증착하여 CVD막(25)을 형성한다. 여기서 CVD막(25)은 산화막(Si2O), 질화막(SiN) 또는 비정질 Si(Armorphous Si)중의 하나로 형성한다.Next, as shown in (b) of FIG. 2, the CVD film 25 is formed by depositing a thin film by a CVD method (or plasma CVD method) at a temperature lower than 250 ° C. The CVD film 25 is formed of one of an oxide film (Si 2 O), a nitride film (SiN), or amorphous Si (Armorphous Si).
제2도의 (c)와 같이 CVD박막을 에치백하여 포토레지스트패턴(24)의 측면에 CVD막사이드월(26)을 형성한다.As illustrated in FIG. 2C, the CVD thin film is etched back to form the CVD film sidewall 26 on the side surface of the photoresist pattern 24.
제2도의 (d)와 같이 앞에서 형성한 사이드월(26)과 포토레지스트패턴(24)을 식각마스크로하여 패턴을 형성할 부위의 패턴막(22)을 식각하여 원하는 미세패턴을 형성한다.As shown in (d) of FIG. 2, the pattern film 22 of the portion where the pattern is to be formed is etched using the sidewall 26 and the photoresist pattern 24 formed as an etching mask to form a desired fine pattern.
이때 산화막으로 형성한 패턴막(22)에 홀을 형성할 경우, 사이드월 역시 산화막으로 형성하여 패턴막의 식각공정 동안 사이드월(26)도 함께 제거함으로서 최종적으로 패턴막에 홀을 형성하는 식각이 완료되었을때에는 포토레지스트패턴 측면의 사이드월은 필요에 따라 왼전히 제거할 수도 있고, 일부 남길 수도 있다.In this case, when holes are formed in the pattern film 22 formed of an oxide film, the sidewalls are also formed of an oxide film, and the sidewalls 26 are also removed during the etching process of the pattern film, thereby finally forming the holes in the pattern film. When done, the sidewalls on the side of the photoresist pattern can be removed or left partially as needed.
또한 포토레지스트의 측면에 형성되는 사이드월 물질과 하층의 산화막간의 식각특성 차이에 따라 콘택프로파일을 다양하게 할 수 있다. 즉, 수직인 단면을 갖기 위해서는 식각특성이 이방성식가이 되어야하고, 단면이 경사를 갖기 위해서는 등방성식각과 이방성식각특성을 조절함으로서 원하는 단면을 얻을 수 있다.In addition, the contact profile may be varied according to the difference in etching characteristics between the sidewall material formed on the side of the photoresist and the oxide layer under the layer. That is, in order to have a vertical cross section, the etching characteristic must be anisotropic, and in order to have a slope, the desired cross section can be obtained by adjusting the isotropic etching and the anisotropic etching characteristic.
폴리실리콘으로 형성한 패턴막에 라인을 형성할 경우에도 사이드월과 포토레지스트패턴을 마스크로 식각하여 라인을 형성할 영역의 패턴막을 제거한다. 식각완료 후 남은 사이드월은 산화막 스트리퍼에 넣어 제거한다.When a line is formed on the pattern film formed of polysilicon, the sidewall and the photoresist pattern are etched with a mask to remove the pattern film of the region where the line is to be formed. After etching, the remaining sidewalls are removed by placing them in an oxide stripper.
이때 스트리퍼는 CVD산화막과 폴리실리콘에 대한 에치레이트의 차가 큰 스트리퍼를 사용한다.In this case, the stripper uses a stripper having a large difference in etch rate between the CVD oxide film and the polysilicon.
본 발명의 마지막 공정으로 제 2 도의 (e)에 도시한 바와 같이 포토레지스트패턴(24)을 제거하면 된다.As a final step of the present invention, the photoresist pattern 24 may be removed as shown in FIG.
본 발명의 또다른 실시예로서 포토레지스트패턴의 형성 후, CVD박막을 증착하기 전에 CVD막(25)의 형질변경방지공정을 추가하는 방법이 있다.As another embodiment of the present invention, there is a method of adding a transformation process of the CVD film 25 after the formation of the photoresist pattern and before the deposition of the CVD thin film.
이 공정은 포토레지스트의 증기(VAPOR)에 의해 CVD막의 형질이 변하는 것을 막기 위하여 포토레지스트를 경화하는 공정이다.This step is a step of curing the photoresist in order to prevent the CVD film from being changed by the vapor of the photoresist.
본 발명을 사용함으로서 노광장비의 최소선폭의 한계를 넘어선 미세 패턴의 가공이 가능하므로 고집적반도체소자의 제조가 가능하다.By using the present invention, it is possible to manufacture a fine pattern beyond the limit of the minimum line width of the exposure equipment, it is possible to manufacture a highly integrated semiconductor device.
또한 250℃ 이하의 저온공정이므로 메틸공정 이후에도 실시가능하다.In addition, since the low temperature process below 250 ℃ can be carried out after the methyl process.
또한 도우펀트농도에 영향을 주지 않는다.It also does not affect the dopant concentration.
공정이 축소되는 효과가 있고, 패턴 형성후 패턴 상에 잔류물이 남지 않는다.The process is reduced in size, and no residue remains on the pattern after pattern formation.
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940009395A KR0135053B1 (en) | 1994-04-30 | 1994-04-30 | Forming method of fine-pattern |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019940009395A KR0135053B1 (en) | 1994-04-30 | 1994-04-30 | Forming method of fine-pattern |
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| KR950030247A KR950030247A (en) | 1995-11-24 |
| KR0135053B1 true KR0135053B1 (en) | 1998-04-20 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100344767B1 (en) * | 1999-10-28 | 2002-07-19 | 주식회사 하이닉스반도체 | Method of defining micro-patterns in semiconductor devices |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100344767B1 (en) * | 1999-10-28 | 2002-07-19 | 주식회사 하이닉스반도체 | Method of defining micro-patterns in semiconductor devices |
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