KR100344767B1 - Method of defining micro-patterns in semiconductor devices - Google Patents

Abstract

PURPOSE: A method for forming a micro-pattern of a semiconductor device is provided to be capable of securing process margin and reducing fabrication cost by defining an active region and an isolation region using a two-step photolithography process. CONSTITUTION: A mask layer is formed on a substrate(200), wherein the substrate has the first and second pattern region. After coating photoresist on the mask layer, the first photoresist pattern is formed by exposing and developing the photoresist using the first exposure mask. An etching mask(230) is formed by selectively etching the mask layer using the first photoresist pattern as a mask. After removing the first photoresist pattern, the second photoresist pattern(25) is formed on the resultant structure. A plurality of grooves are formed in the substrate by carrying out an etching process using the etching mask and the second photoresist pattern as a mask.

Description

Method of defining micro-patterns in semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a micropattern of a semiconductor device. In particular, the process margin is defined by defining an active region and a device isolation region by profile grooved isolation (PGI) using two steps of photolithography using an existing exposure apparatus. The present invention relates to a method for forming an ultra-fine pattern of a semiconductor device, which ensures the manufacturing cost and reduces the manufacturing cost.

As the integration degree of the device increases, a profile grooved isolation (PGI) method is used as a method of forming an active region, which is an element formation region, and a device isolation region, which is a field region. This is performed by forming an etching mask through a photolithography process including exposure, development, and etching on a region other than the device isolation region of the substrate, and then removing a portion of the substrate not protected by the etching mask to a predetermined depth. After the groove is formed, the groove is formed by embedding the groove with an insulating material.

As the degree of integration of devices increases, the size of devices such as memory cells is inevitably reduced, and the active regions in which they are formed also become fine, but there is a limit in securing their formation margins. In particular, when using a deep ultra violet light source having a wavelength of about 248nm as an exposure light source and using a phase shift mask as a photomask, or when using a modified illumination, the fine pattern Although it is possible to form an active region having a, these also have a limit in improving the integration of the chip. In other words, as the distance between the active regions or the device isolation regions decreases, it becomes difficult to secure process margins such as causing a bridge phenomenon between individual patterns due to optical characteristics such as proximity effect.

1 is a layout of a device isolation region and an active region pattern formed according to the prior art.

Referring to FIG. 1, a device isolation region 11 made of an insulating material such as an oxide film and a plurality of active regions 12 are located on a surface of a semiconductor substrate (not shown) made of a semiconductor such as silicon.

The active regions 12 have a predetermined regular pattern and are spaced apart from each other. However, in the prior art, there is a limit in that the mutual separation distance S1 between the active regions 12 is reduced by the device isolation region 11 due to the optical characteristic.

2A to 2D are cross-sectional views taken along the cutting line I-I 'of FIG.

Referring to FIG. 2A, a nitride film 13 is formed by chemical vapor deposition on a semiconductor substrate 10 made of silicon or the like. In this case, the nitride film 13 is patterned to form a groove forming etching mask to be a device isolation region.

Then, a photoresist is applied on the nitride film 13, and then a photoresist pattern 14 made of the remaining photoresist is formed by performing exposure and development using a photomask defining a device isolation region. At this time, the portion of the substrate 10 corresponding to the exposed surface of the nitride film 13 becomes an element isolation region. However, in forming the photoresist pattern, a phase inversion mask or modified illumination may be used to further refine the gap between the exposed nitride film surfaces, but these methods also have difficulty in securing margins.

In addition, the pattern defined by the photomask has a regular arrangement at predetermined intervals, and each pattern is formed to have a zigzag shape. That is, the patterns of n columns and (n + 2) columns are arranged regularly in rows, and the patterns of (n + 1) columns are arranged such that the events of n and (n + 2) columns are located at. N is a natural number.

Referring to FIG. 2B, an nitride mask of an area not protected by the photoresist pattern 140 is removed by anisotropic dry etching to form an etching mask 130 exposing a surface corresponding to the device isolation region of the substrate.

Referring to FIG. 2C, the photoresist pattern is removed by oxygen ashing or the like, and then the surface of the etching mask 130 formed of the remaining nitride film is exposed.

Referring to FIG. 2D, the substrate G of the portion not protected by the etching mask 130 is removed to a predetermined depth to form the groove G1, which is a portion where an insulating material such as an oxide film of the device isolation region is to be buried. In this case, the groove G1 is formed by removing a predetermined portion of the substrate by anisotropic dry etching such as reactive ion etching or plasma etching. The distance between neighboring active regions is indicated by 'S1'. The region included in 'S1' becomes the device isolation region, and thus 'S1' indicates the width of the groove G1.

Subsequently, although not shown, an insulating material such as a high temperature low pressure dielectric (HLD) is deposited on the substrate 100 including the groove G1, and then grooved by a planarization process such as etch back or chemical mechanical polishing. Only the inside is left to form a field insulating film which is an element isolation region to complete the element isolation process.

However, the device isolation method of the semiconductor device according to the related art described above is difficult to overcome the limitation of the device integration. That is, as the separation distance between the widths of the active area patterns is reduced, the degree of integration can be improved, but there is a limit in reducing the distance.

In addition, there is a limit in the case of finely defining the patterns of the active region by using a phase inversion mask or modified illumination during exposure using ultraviolet rays having a wavelength of 248 nm.

Therefore, the device isolation method of the semiconductor device according to the related art has a problem of shortening the distance between the patterns, causing bridges between patterns due to optical characteristics of light, such as a proximity effect, and thus reducing process margins.

Accordingly, an object of the present invention is to define the active region and the device isolation region by PGI (profile grooved isolation) as two-stage photolithography using a conventional exposure apparatus to secure process margins and reduce manufacturing costs. An ultrafine pattern forming method of a semiconductor device is provided.

According to another aspect of the present invention, there is provided a method of forming a semiconductor device fine pattern, including forming a mask layer on a substrate in which a first pattern region and a second pattern region are staggered in a zigzag shape, and the mask Applying a photoresist on the layer, and performing exposure and development using a first exposure mask spaced apart from each other to define a matrix form, covering the mask layer portion over the first pattern region of the substrate. Forming a first photoresist pattern, forming an etching mask covering the first pattern region of the substrate by removing the mask layer portion not covered with the first photoresist pattern, and forming the first photoresist pattern; Removing the pattern, forming a second photoresist pattern covering the second pattern region of the substrate; It comprises the steps of removing the etch mask, and the second photo-resist pattern for forming a groove by removing the substrate region and the first group that the etching mask is not covered with the second photo-resist pattern to a predetermined depth.

1 is a layout of a device isolation region and an active region pattern formed according to the prior art;

2A through 2D are cross-sectional views illustrating a method of isolating a device of a semiconductor device according to the prior art;

3 is a substrate layout of a first step in the method for forming a fine pattern of a semiconductor device according to the present invention;

4 is a substrate layout of a second step in the method for forming a fine pattern of a semiconductor device according to the present invention.

5A through 5E are cross-sectional views showing a device isolation method of a semiconductor device according to the present invention. Explanation of symbols for major parts of the drawings. * 20,200: substrate 21: device isolation region 22: first active region 23: nitride film 24 : First photoresist pattern 25: second photoresist pattern / second etching mask 220: second active region 230: first etching mask

In the present invention, by forming a pattern of an etch mask defining a predetermined pattern in two steps, it is possible to define ultrafine patterns such as active regions by overcoming the limit resolution of general photolithography. That is, the shortening and the separation distance of the patterns can be reduced to suppress the bridge effect caused by the optical characteristics.

According to an exemplary embodiment of the present invention, ultrafine patterns having a separation distance of about 60 nm may be formed in consideration of only the overlap margin of the first exposure mask and the second exposure mask. This margin is a numerical value that overcomes the limitations of the deep ultraviolet ray wavelength used during exposure and is comparable to the process margin of the production of next-generation devices, such as giga-class devices and exposure using electron beams.

Therefore, according to the present invention, the process margin is improved, and the present invention can be applied to an apparatus using ultraviolet wavelengths, which greatly contributes to manufacturing cost reduction.

In addition, in the present invention, the pattern is defined using two types of exposure masks that define separate patterns, so that the pattern is densely populated (for example, memory cell region) and the non-dense region (for example, core / ferry region). ) Is defined as a separate step, and then implemented as a single etching process on the substrate, thereby improving the etching characteristics.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

3 is a substrate layout for a first step of the method for forming a fine pattern of a semiconductor device according to the present invention, and is defined by a first exposure mask, and FIG. 4 is a second step of the method for forming a fine pattern of a semiconductor device according to the present invention. The substrate layout for is defined by the second exposure mask.

Referring to FIG. 3, an element isolation region 21 made of an insulating material such as an oxide film and a plurality of first active regions 22 are regularly arranged on a surface of a semiconductor substrate (not shown) made of a semiconductor such as silicon. Are arranged in a row.

In addition, another second active region 220 is surrounded by four first active regions 22.

The first active regions 22 have a predetermined regular pattern and are spaced apart from each other. In particular, in the drawing, the device isolation region 21 made of an insulating material such as an oxide film has a predetermined first separation distance S2 between the first active regions 22. These first active regions 22 are defined by a first exposure mask (not shown).

In addition, the first active region 22 and the second active region 220 also have a predetermined second separation distance S3 in the longitudinal axis direction and are insulated by the device isolation region 21. In this case, the second active region 220 is defined to have a shape surrounded by four first active regions 22 forming a quadrangle by a second exposure mask (not shown).

Referring to FIG. 4, a device isolation region 21 made of an insulating material such as an oxide film and a plurality of first active regions 22 are regularly arranged on a surface of a semiconductor substrate (not shown) made of a semiconductor such as silicon. Are arranged in a row.

In addition, another second active region 220 is surrounded by four first active regions 22.

The first active regions 22 have a predetermined regular pattern and are spaced apart from each other. In particular, in the drawing, the device isolation region 21 made of an insulating material such as an oxide film has a predetermined first separation distance S2 between the first active regions 22. These first active regions 22 are defined by a first exposure mask (not shown).

In addition, the first active region 22 and the second active region 220 also have a predetermined second separation distance S3 in the longitudinal axis direction and are insulated by the device isolation region 21. In this case, the second active region 220 is defined to have a shape surrounded by four first active regions 22 forming a quadrangle by a second exposure mask (not shown). That is, an arrangement in which one second active region 220 is positioned at the center of a quadrangle formed by four first active regions is shown. In this case, the first active region 22 is also positioned at the center of the quadrangular structure formed by the four second active regions 220.

5A through 5E are cross-sectional views illustrating a method of isolating a device of a semiconductor device according to the present disclosure, and are taken along the line II-II ′ of FIGS. 3 to 4.

Referring to FIG. 5A, a nitride film 23 is formed by chemical vapor deposition on a semiconductor substrate 20 made of silicon or the like. In this case, the nitride film 23 is patterned in a predetermined shape to form an etching mask for forming a groove to be an element isolation region. In addition, the nitride film 23 can be formed in a form in which a pad oxide film (not shown) is interposed between the substrate 20 and the substrate 20.

After the photoresist is applied onto the nitride film 23, a first photoresist pattern 24 made of the remaining photoresist is exposed and developed by using a first exposure mask (not shown) defining a device isolation region. ). In a subsequent step, the second active region (not shown) becomes a predetermined region of the portion of the substrate 20 corresponding to the exposed surface of the nitride film 23. In this case, a portion of the substrate 20 under the nitride layer 23 covered by the first photoresist pattern 24 is a portion where an isolation region for insulating the first active region (not shown) is to be formed. As illustrated in FIG. 3, the first photoresist pattern 24 defining a portion to be formed is formed to expose the surface of the nitride film 23 including a portion to isolate the first active regions forming a square matrix. Therefore, since the photoresist pattern covering the portion where the second active region (not shown) is to be formed is not defined, it is easy to walk the separation distance S2 between the first photoresist patterns 24.

Referring to FIG. 5B, a first etching mask 230 including a remaining nitride film exposing a surface corresponding to an element isolation region of the substrate by removing an nitride film of a portion not protected by the first photoresist pattern by anisotropic dry etching. To form.

Next, the first photoresist pattern is removed by oxygen ashing or the like to expose the surface of the first etching mask 230 formed of the remaining nitride film.

Referring to FIG. 5C, a photoresist is applied to the surface of the substrate 230 including the surface of the first etching mask 230, and then a second exposure mask (not shown) defining a portion where the second active region is to be formed. Exposure and development are performed to remove the remaining photoresist except the upper portion of the substrate 20 corresponding to the second active region to form the second photoresist pattern 25. The second photoresist pattern 25 becomes the second etching mask 25 by the second photoresist pattern 25 itself without a separate etching mask forming process to cover the portion of the substrate 20 on which the second active region is to be formed. .

In this case, as shown in FIG. 4, the second photoresist pattern 25 is defined such that the second active region has a shape surrounded by four first active regions. That is, one second photoresist pattern 25 is formed at the central portion of the quadrangle formed by the four first etching masks 230, which are the areas where the four first active regions are to be formed. The minimum exposure distance for securing the distance S3 in which the second photoresist pattern 25 and the first etching mask 230 are spaced apart in the row axis direction is not formed by one exposure, as in the embodiment of the present invention. Since each pattern is defined as a separate exposure process, the margin for the size of 'S3' is excellent.

Referring to FIG. 5D, a groove, which is a portion where an insulating material such as an oxide layer of an element isolation region is to be buried, is removed by removing a substrate having a predetermined depth from a portion not protected by the etching mask 230 and the second photoresist pattern 25. Form. In this case, the groove is formed by removing a predetermined portion of the substrate by anisotropic dry etching such as reactive ion etching or plasma etching. 'S3' indicates the spaced distance in the row axis direction between the second photoresist pattern 25 and the first etching mask 230, as well as the spaced distance between the active regions, that is, the width of the groove.

Referring to FIG. 5E, the second photoresist pattern 25 is removed by oxygen ashing, and then the first etching mask made of a nitride film is removed by wet etching to form the surface of the first active region and the second active region, which are device forming regions. Expose

Subsequently, although not shown, an insulating material such as a high temperature low pressure dielectric (HLD) is deposited on the substrate 200 including the groove, and then left only in the groove by a planarization process such as etch back and chemical mechanical polishing. To form a field insulating film as a device isolation region to complete the device isolation process.

Therefore, the method of forming a micropattern of the semiconductor device of the present invention can reduce the shortening and the separation distance of the active region patterns, thereby suppressing the bridge effect caused by the optical characteristics, and the process margin securing the minimum separation distance is improved. Since it can be applied to a device using an ultraviolet wavelength, it contributes greatly to manufacturing cost reduction, and also has an advantage of improving the etching characteristics for pattern formation.

Claims (5)

delete Forming a mask layer on a substrate in which the first pattern region and the second pattern region are staggered in a zigzag shape; Applying photoresist on the mask layer; Forming a first photoresist pattern covering the mask layer portion over the first pattern region of the substrate by performing exposure and development using a first exposure mask spaced apart from each other to define a matrix shape; Removing an area of the mask layer not covered with the first photoresist pattern to form an etching mask covering the first pattern region of the substrate; Removing the first photoresist pattern; Forming a second photoresist pattern covering the second pattern region of the substrate; Removing a portion of the substrate not covered with the etching mask and the second photoresist pattern to a predetermined depth to form a groove; And removing the etching mask and the second photoresist pattern. The method of claim 2, wherein the mask layer is formed of a nitride film. The method of claim 2, wherein the first pattern region and the second pattern region are arranged in a square matrix structure, and the second pattern region is surrounded by a central portion of a quadrangle formed by four first pattern regions. Method for forming a fine pattern of a semiconductor device, characterized in that it is defined to be arranged in a mutually staggered form. The method of claim 2, wherein the method for forming a micropattern of the semiconductor device further comprises forming an isolation region by filling an insulating material in the groove.