JPH0228333A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0228333A JPH0228333A JP17972588A JP17972588A JPH0228333A JP H0228333 A JPH0228333 A JP H0228333A JP 17972588 A JP17972588 A JP 17972588A JP 17972588 A JP17972588 A JP 17972588A JP H0228333 A JPH0228333 A JP H0228333A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- silicon oxide
- oxide film
- lift
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title description 9
- 238000000034 method Methods 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 5
- 238000000206 photolithography Methods 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 abstract description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000005121 nitriding Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に係り、特にリセス
構造を有するＦＥＴのゲート電極の形成方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a gate electrode of an FET having a recessed structure.
（従来の技術）
第２図（ａ）〜（Ｃ）はリセス構造を有する従来のＧａ
ＡｓＦＥＴのゲート電極の製造工程を示す断面図である
。以下、これを用いて従来の製造工程について説明する
。(Prior art) Figures 2 (a) to (C) show conventional Ga
FIG. 3 is a cross-sectional view showing a manufacturing process of a gate electrode of an AsFET. Hereinafter, the conventional manufacturing process will be explained using this.
まず、第２図（ａ）に示すように、ＧａＡｓ基板１上に
写真製版によりホトレジスト２をバターニングした後、
これをマスクしてウェットエツチングによりリセス溝３
を形成する。次に、第２図（ｂ）に示すように、ゲート
金属４′を蒸着する。次に、第２図（ｅ）に示すように
、ホトレジスト２を有機溶剤により溶解し、同時に上部
に付着した不要なゲート金属４′を除去することにより
ゲート電極４を形成する。通常このような方法をリフト
オフ法と呼ぶ。First, as shown in FIG. 2(a), after patterning a photoresist 2 on a GaAs substrate 1 by photolithography,
Mask this and wet-etch the recess groove 3.
form. Next, as shown in FIG. 2(b), a gate metal 4' is deposited. Next, as shown in FIG. 2(e), a gate electrode 4 is formed by dissolving the photoresist 2 with an organic solvent and simultaneously removing unnecessary gate metal 4' attached to the top. This method is usually called a lift-off method.
従来のリセス溝３を有するＧａＡｓＦＥＴのゲート電極
４の形成方法では、第３図に示すように、ホトレジスト
２のプロファイルによってはホトレジスト２の側面にゲ
ート金属４′が付着し、金属残りのようなりフトオフ不
良が生じたり、ＧａＡｓ基板１の表面に直接ホトレジス
ト２を塗布するため、基板表面が汚染される恐れがある
。In the conventional method for forming the gate electrode 4 of a GaAsFET having a recess groove 3, as shown in FIG. Since the photoresist 2 is applied directly to the surface of the GaAs substrate 1, there is a risk that defects may occur or the surface of the substrate may be contaminated.
また、第２図に示したように、ホトレジスト２上でゲー
ト金属４′が横方向に成長しながら蒸着・堆積するため
、ゲート電極４の上層部分が細くなり、したがって、ゲ
ート電極４の低抵抗化には不利である等の問題点があっ
た。Further, as shown in FIG. 2, since the gate metal 4' is vapor-deposited and deposited on the photoresist 2 while growing laterally, the upper layer of the gate electrode 4 becomes thinner, resulting in a lower resistance of the gate electrode 4. There were problems such as being disadvantageous to
この発明は、上記のような問題点を解消するためになさ
れたもので、蒸着・リフトオフを用いずにリセス溝を有
するＦＥＴのゲート電極を形成することを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to form a gate electrode of an FET having a recess groove without using vapor deposition or lift-off.
（課題を解決するための手段）
この発明に係る半導体装置の製造方法は、リセス溝に絶
縁膜側壁を形成した後、ゲート電極を形成するものであ
る。(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention is to form a gate electrode after forming an insulating film sidewall in a recess groove.
〔作用）
この発明においては、リセス溝の側壁に絶縁膜を形成し
てゲート電極を形成することから、蒸着・リフトオフに
より生じるような不良が発生する恐れがなく、レジスト
を直接基板表面に塗布しないので基板表面が汚染させる
こともない。また、ゲート電極の上層部分が広くなるた
め、ゲート電極の低抵抗化も容易であり、かつ写真製版
による寸法より短いゲート長が得られる。[Function] In this invention, since the gate electrode is formed by forming an insulating film on the side wall of the recess groove, there is no risk of defects such as those caused by vapor deposition and lift-off, and the resist is not applied directly to the substrate surface. Therefore, the substrate surface will not be contaminated. Furthermore, since the upper layer portion of the gate electrode is widened, it is easy to reduce the resistance of the gate electrode, and a gate length shorter than that obtained by photolithography can be obtained.
以下、この発明の一実施例を第１図について説明する。 An embodiment of the present invention will be described below with reference to FIG.
第１図（ａ）〜（ｅ）はこの発明の一実施例による半導
体装置の製造方法を工程順に示す断面図である。まず、
第１図（ａ）に示すように、ＧａＡｓ基板１上にシリコ
ン窒化膜５を堆積させた後、写真製版によりホトレジス
ト２をパターニングし、このレジストパターンをマスク
にしてＲＩＥなどの異方性エツチングによりシリコン窒
化膜５をエツチングしリセス溝３を形成する。次に、第
１図（ｂ）に示すように、ホトレジスト２を除去した後
、シリコン窒化膜５より異方性エツチング速度の速いシ
リコン酸化膜６をプラズマＣＶＤ法などにより堆積する
。次に、第１図（Ｃ）に示すように、全面をＲＩＥなど
の異性性エツチングによりシリコン酸化膜６をエツチン
グし、リセス溝３にシリコン酸化膜側壁７を形成する。FIGS. 1A to 1E are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in order of steps. first,
As shown in FIG. 1(a), after depositing a silicon nitride film 5 on a GaAs substrate 1, a photoresist 2 is patterned by photolithography, and using this resist pattern as a mask, anisotropic etching such as RIE is performed. The silicon nitride film 5 is etched to form a recess groove 3. Next, as shown in FIG. 1(b), after removing the photoresist 2, a silicon oxide film 6 having a higher anisotropic etching rate than the silicon nitride film 5 is deposited by plasma CVD or the like. Next, as shown in FIG. 1C, the silicon oxide film 6 is etched on the entire surface by isomeric etching such as RIE to form a silicon oxide film sidewall 7 in the recess groove 3.
次に、第１図（ｄ）に示すように、スパッタ法などによ
りゲート金属４′を堆積した後、写真製版によりレジス
トパターンをマスクにしてＲＩＥなどでゲート金属４′
をエツチングし、第１図（ｅ）に示すように、ゲート電
極４を形成する。Next, as shown in FIG. 1(d), the gate metal 4' is deposited by sputtering or the like, and then the gate metal 4' is deposited by photolithography using the resist pattern as a mask by RIE or the like.
is etched to form a gate electrode 4 as shown in FIG. 1(e).
なお、上記実施例ではシリコン窒化膜５およびシリコン
酸化膜６の２種類の絶縁膜を用いた場合について説明し
たが、異性性エツチング速度を精度よく制御できれば同
−膜または別の絶縁膜を用いても同様の効果を得ること
ができる。In the above embodiment, two types of insulating films, silicon nitride film 5 and silicon oxide film 6, are used. However, if the isomeric etching rate can be controlled accurately, it is possible to use the same film or different insulating films. You can also get the same effect.
また、リセス溝３上にシリコン酸化膜側壁７を形成した
後、蒸着・リフトオフによりゲート電極４を形成するこ
とも可能であるが、この場合でもＧａＡｓ表面が直接露
出した部分がないため、リフトオフ不良が生じても後処
理が容易になる。It is also possible to form the gate electrode 4 by vapor deposition and lift-off after forming the silicon oxide film sidewall 7 on the recess groove 3, but even in this case, lift-off failure may occur because there is no directly exposed part of the GaAs surface. Even if this occurs, post-processing becomes easier.
また、上記実施例では、ＧａＡｓＦＥＴについて説明し
たが、リセス構造を有するゲートをもつＦＥＴならば他
の化合物半導体についても同様であり、もちろんこれら
ＦＥＴを用いた集積回路素子についても同様に適用でき
る。Further, in the above embodiment, a GaAs FET was described, but the same applies to other compound semiconductors as long as the FET has a gate with a recessed structure, and of course, the same can be applied to integrated circuit elements using these FETs.
以上説明したようにこの発明は、リセス溝に絶縁膜側壁
を形成した後、ゲート電極を形成するようにしたので、
基板表面の汚染やりフトオフ不良などの問題点を除去で
きるとともに、ゲート電極の低抵抗化が可能となり、Ｆ
ＥＴの高周波特性や雑音特性を改善することができる効
果が得られる。As explained above, in this invention, the gate electrode is formed after the insulating film sidewall is formed in the recess groove.
It is possible to eliminate problems such as contamination on the substrate surface and defective lift-off, and it is also possible to reduce the resistance of the gate electrode.
The effect of improving the high frequency characteristics and noise characteristics of ET can be obtained.
第１図はこの発明の一実施例による半導体装置の製造方
法の工程を示す断面図、第２図は従来の半導体装置の製
造方法の工程を示す断面図、第３図は従来例の不具合を
説明するための断面図である。
図において、１はＧａＡｓ基板、２はホトレジスト、３
はリセス溝、４はゲート電極、５はシリコン窒化膜、６
はシリコン酸化膜、７はシリコン酸化膜側壁である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第
図
第
図
第
図
手
続
補
正
書
（自発）FIG. 1 is a cross-sectional view showing the steps of a semiconductor device manufacturing method according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the steps of a conventional semiconductor device manufacturing method, and FIG. 3 is a cross-sectional view showing the steps of a conventional semiconductor device manufacturing method. It is a sectional view for explanation. In the figure, 1 is a GaAs substrate, 2 is a photoresist, and 3 is a GaAs substrate.
is a recess groove, 4 is a gate electrode, 5 is a silicon nitride film, 6
is a silicon oxide film, and 7 is a side wall of the silicon oxide film. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) Diagram diagram diagram procedure amendment (voluntary)
Claims (1)
において、リセス溝に絶縁膜側壁を形成した後、ゲート
電極を形成する工程を含むことを特徴とする半導体装置
の製造方法。1. A method for forming a gate electrode of a semiconductor device using a recess structure, the method comprising the step of forming a gate electrode after forming an insulating film sidewall in a recess groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17972588A JPH0228333A (en) | 1988-07-18 | 1988-07-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17972588A JPH0228333A (en) | 1988-07-18 | 1988-07-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0228333A true JPH0228333A (en) | 1990-01-30 |
Family
ID=16070781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17972588A Pending JPH0228333A (en) | 1988-07-18 | 1988-07-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0228333A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5231043A (en) * | 1991-08-21 | 1993-07-27 | Sgs-Thomson Microelectronics, Inc. | Contact alignment for integrated circuits |
| US5599598A (en) * | 1995-04-03 | 1997-02-04 | Husky Injection Molding Systems Ltd. | Multilayered hollow plastic article and method for obtaining same |
| KR100364710B1 (en) * | 1994-07-29 | 2003-02-25 | 엘지전자 주식회사 | Method for manufacturing semiconductor device |
-
1988
- 1988-07-18 JP JP17972588A patent/JPH0228333A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5231043A (en) * | 1991-08-21 | 1993-07-27 | Sgs-Thomson Microelectronics, Inc. | Contact alignment for integrated circuits |
| KR100364710B1 (en) * | 1994-07-29 | 2003-02-25 | 엘지전자 주식회사 | Method for manufacturing semiconductor device |
| US5599598A (en) * | 1995-04-03 | 1997-02-04 | Husky Injection Molding Systems Ltd. | Multilayered hollow plastic article and method for obtaining same |
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