JPH02199825A - Manufacture of electrode - Google Patents
Manufacture of electrodeInfo
- Publication number
- JPH02199825A JPH02199825A JP1914489A JP1914489A JPH02199825A JP H02199825 A JPH02199825 A JP H02199825A JP 1914489 A JP1914489 A JP 1914489A JP 1914489 A JP1914489 A JP 1914489A JP H02199825 A JPH02199825 A JP H02199825A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- film
- layer
- photoresist
- hydrofluoric acid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000010936 titanium Substances 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 13
- 239000000203 mixture Substances 0.000 abstract description 8
- 229910052681 coesite Inorganic materials 0.000 abstract description 7
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 7
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 229910052682 stishovite Inorganic materials 0.000 abstract description 7
- 229910052905 tridymite Inorganic materials 0.000 abstract description 7
- 229910000673 Indium arsenide Inorganic materials 0.000 abstract description 3
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 abstract description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 2
- 239000007788 liquid Substances 0.000 abstract 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 239000003960 organic solvent Substances 0.000 description 4
- 239000012528 membrane Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体装置の製造方法に係り、特にＴｉ層を含
む多層膜電極の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a multilayer electrode including a Ti layer.
（従来の技術）
化合物半導体デバイスの電極においては、チタンｌ白金
ｌ金（Ｔｉ／Ｐｔ／Ａｕ）多層膜がよく用いられている
［例えば、ＴＡＫＵＭＩ ＮＩＴＴＯＮＯｅｔ ａｌ、
ＪａｐａｎｅｓｅＪｏｕｒｎａｌ ｏｆ Ａｐｐｌｉｅ
ｄ Ｐｈｙｓｉｃｓ Ｖｏｌ、 ２５． Ｌ、 ８６５
（１９８６）］。(Prior art) Titanium/platinum/gold (Ti/Pt/Au) multilayer films are often used in electrodes of compound semiconductor devices [for example, TAKUMI NITTONO et al.
Japanese Journal of Applie
d Physics Vol, 25. L, 865
(1986)].
そしてその電極のパタン形成には二酸化珪素（Ｓ１０２
）膜を用いたリフトオフ法がよく用いられている。Silicon dioxide (S102) is used to form the electrode pattern.
) The lift-off method using a membrane is often used.
その方法としては、まずＳｉＯ２膜をフォトレジストと
基板の間にはさみ、フォトレジストをマスクとしてＳｉ
Ｏ□膜ををアンダーカット形状にエツチングする。次に
その上に電極金属を堆積し、フォトレジストを有機溶剤
で溶かし不要な金属膜を除去する。このようにして電極
のパタンが形成される【例えば、５ＨＩＮＩＣＨＩＲＯ
ＴＡＫＡＴＡＮＩ ｅｔ ａｌ、 ＪａｐａｎｅｓｅＪ
ｏｕｒｎａｌｏｆＡｐｐｌｉｅｄＰｈｙｓｉｃｓＶｏｌ
、２６．Ｌ、１７７０（１９８７月。The method is to first sandwich a SiO2 film between the photoresist and the substrate, and use the photoresist as a mask to
Etch the O□ film into an undercut shape. Next, an electrode metal is deposited on top of the photoresist, and the unnecessary metal film is removed by dissolving the photoresist with an organic solvent. In this way, an electrode pattern is formed [for example, 5HINICHIRO
TAKATANI et al, JapaneseJ
ournalofAppliedPhysicsVol
, 26. L, 1770 (1987.
このようなりフトオフ法の特徴は、適当な厚さの５ｔＯ
２膜を用いることにより、電極金属の厚さが変わっても
端部の形状の良好な電極を形成できることである。また
電極形成部の基板表面がプロセス中にフォトレジストで
覆われることがないため、フォトレジストの残留物の影
響を受けることなく電極を形成できる。The characteristic of this type of lift-off method is that the 5tO
By using two films, it is possible to form an electrode with a good end shape even if the thickness of the electrode metal changes. Furthermore, since the substrate surface of the electrode forming portion is not covered with photoresist during the process, electrodes can be formed without being affected by photoresist residue.
（発明が解決しようとする問題点）
このような従来の製造方法で形成されたＴｉ層を含む多
層膜電極では、Ｔｉ層の側面が電極側面に露出しており
、電極形成後に８１０２膜を除去する工程において、弗
酸系エツチング液によってＴｉ層が電極の側面からエツ
チングされるという欠点があった。(Problems to be Solved by the Invention) In a multilayer electrode including a Ti layer formed by such a conventional manufacturing method, the side surface of the Ti layer is exposed on the side surface of the electrode, and the 8102 film must be removed after electrode formation. In this step, there was a drawback that the Ti layer was etched from the side surface of the electrode by the hydrofluoric acid etching solution.
そのためオーム性電極の場合接触抵抗が増大するという
問題が生じた。また微細な電極の場合には膜剥がれが生
じてしまうこともあった。Therefore, in the case of ohmic electrodes, a problem arises in that contact resistance increases. Furthermore, in the case of fine electrodes, film peeling may occur.
本発明の目的は、弗酸系エツチング液によって電極中の
Ｔｉ層がエツチングされることのない電極の製造方法を
提供することにある。An object of the present invention is to provide a method for manufacturing an electrode in which the Ti layer in the electrode is not etched by a hydrofluoric acid etching solution.
（問題点を解決するための手段）
本発明の電極の製造方法は、半導体基板上に絶縁膜を堆
積する工程と、前記絶縁膜上にフォトレジストから成る
所望のパタンを形成する工程と、前記絶縁膜をエツチン
グする工程と、前記フォトレジスト上及び前記半導体基
板上全面に少なくともチタン（Ｔｉ）層を含む金属多層
膜を形成し前記フォトレジストを有機溶剤で溶かし少な
くともＴｉ層を含む多層膜電極を形成する工程と、前記
多層膜電極と前記絶縁膜の隙間を埋めるように前記多層
膜電極上及び前記絶縁膜上に耐弗酸性材料を堆積する工
程と、前記多層膜電極と前記絶縁膜の隙間に堆積した部
分を残して前記耐弗酸性材料をエツチングする工程と、
前記絶縁膜を弗酸により除去する工程とを含んで構成さ
れる。(Means for Solving the Problems) The electrode manufacturing method of the present invention includes the steps of: depositing an insulating film on a semiconductor substrate; forming a desired pattern made of photoresist on the insulating film; A step of etching an insulating film, forming a metal multilayer film containing at least a titanium (Ti) layer on the entire surface of the photoresist and the semiconductor substrate, and dissolving the photoresist with an organic solvent to form a multilayer film electrode containing at least a Ti layer. a step of depositing a hydrofluoric acid-resistant material on the multilayer electrode and the insulating film so as to fill the gap between the multilayer electrode and the insulating film; etching the hydrofluoric acid-resistant material leaving the portion deposited on it;
The method includes a step of removing the insulating film with hydrofluoric acid.
（作用）
本発明によれば、Ｔｉ層を含む多層膜電極の側面は耐弗
酸性材料により被覆される。このため絶縁膜を弗酸で除
去する工程を行ってもＴｉＭは弗酸によりエツチングさ
れない。(Function) According to the present invention, the side surfaces of the multilayer electrode including the Ti layer are coated with a hydrofluoric acid-resistant material. Therefore, even if the step of removing the insulating film with hydrofluoric acid is performed, TiM is not etched by the hydrofluoric acid.
（実施例） 次に本発明の実施例について図面を参照して説明する。(Example) Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｉ）は本発明の一実施例として、ｎ型
ＧａＡｓ能動層上にｎ型ＩｎＧａＡｓ層を設けその上に
電極を設けた構造のノンアロイオーム性電極を有する、
ＧａＡｓ ＭＥＳＦＥＴのソース電極及びドレイン電極
の製造方法を示す工程断面図である。FIGS. 1(a) to 1(i) show, as an embodiment of the present invention, a non-alloy ohmic electrode having a structure in which an n-type InGaAs layer is provided on an n-type GaAs active layer and an electrode is provided thereon.
FIG. 3 is a process cross-sectional view showing a method for manufacturing source and drain electrodes of a GaAs MESFET.
まず第１図（ａ）に示すように、半絶縁性ＧａＡｓ基板
１上にｎ型ＧａＡｓ能動層２を設け、ｎ型ＧａＡｓ能動
層２上にｎ型ＩｎｘＧａ１−ｘＡｓのＩｎ組成比Ｘを下
部から表面に向けて徐々にＯから１へ増加させたｎ型Ｉ
ｎＧａＡｓ傾斜組成層３を設け、ｎ型ＩｎＧａＡｓ傾斜
組成層３上にｎ型ＩｎＡｓ層４を設ける。次にｎ型Ｉｎ
Ａｓ層４上に５１０２膜５を化学的気相成長法により全
面に３００ｎｍの厚さに堆積し、ＳｉＯ２膜５上に第一
のフォトレジスト６を塗布して所望の電極パタンを形成
する。First, as shown in FIG. 1(a), an n-type GaAs active layer 2 is provided on a semi-insulating GaAs substrate 1, and an In composition ratio X of n-type InxGa1-xAs is applied from the bottom onto the n-type GaAs active layer 2. n-type I gradually increased from O to 1 toward the surface
An nGaAs gradient composition layer 3 is provided, and an n-type InAs layer 4 is provided on the n-type InGaAs gradient composition layer 3. Next, n-type In
A 5102 film 5 is deposited on the entire surface of the As layer 4 to a thickness of 300 nm by chemical vapor deposition, and a first photoresist 6 is applied on the SiO2 film 5 to form a desired electrode pattern.
さらに第１図（ｂ）に示すように、弗酸系エツチング液
により、５１０２膜５を、アンダーカット形状になるま
でエツチングする。Further, as shown in FIG. 1(b), the 5102 film 5 is etched using a hydrofluoric acid etching solution until it has an undercut shape.
次に、第１図（ｃ）に示すように、真空蒸着法によりＴ
ｉ７を２０ｎｍ、 Ｐｔ８を２０ｎｍ、Ａｕ９を２００
ｎｍの厚さに順次堆積する。Next, as shown in FIG. 1(c), T
20 nm of i7, 20 nm of Pt8, 200 nm of Au9
Sequentially deposited to a thickness of nm.
さらに第１図（ｄ）に示すように、フォトレジストを有
機溶剤で溶かし不要な金属膜を除去することにより、Ｓ
ｉＯ□膜５のエツチングされた部分にＴｉ／Ｐｔ／Ａｕ
電極が形成される。そして５１０２膜部分と電極部分と
の間には隙間が存在する。Furthermore, as shown in Figure 1(d), by dissolving the photoresist with an organic solvent and removing unnecessary metal films, S
Ti/Pt/Au is applied to the etched portion of the iO□ film 5.
Electrodes are formed. A gap exists between the 5102 membrane portion and the electrode portion.
次に第１図（ｅ）に示すように耐弗酸性材料である窒化
チタン膜（ＴｉＮ）４０を反応性バイアススパッタリン
グ法により、全面に５０ｋｍの厚さに堆積する。Next, as shown in FIG. 1(e), a titanium nitride (TiN) film 40, which is a hydrofluoric acid-resistant material, is deposited over the entire surface to a thickness of 50 km by reactive bias sputtering.
さらに第１図（０に示すようにＣＦ４ガスを用いた異方
性ドライエツチング法により、ＴｉＮ膜１０を前記隙間
部分を残し、前記オーム性電極及びＳｉＯ□膜５が表面
に露出するまでエツチングする。このことによリ、前記
オーム性電極の側面にＴｉＮの側壁部が形成される。Further, as shown in FIG. 1 (0), the TiN film 10 is etched by an anisotropic dry etching method using CF4 gas until the ohmic electrode and the SiO□ film 5 are exposed on the surface, leaving the gap. As a result, a TiN side wall portion is formed on the side surface of the ohmic electrode.
次に第１図（ｇ）に示すように、弗酸系エツチング液を
用いて、Ｓｉｏ２膜５を除去する。電極中のＴｉ層は、
弗酸に対して耐性のあるＴｉＮで覆われているため弗酸
によりエツチングされることはない。Next, as shown in FIG. 1(g), the Sio2 film 5 is removed using a hydrofluoric acid etching solution. The Ti layer in the electrode is
Since it is covered with TiN which is resistant to hydrofluoric acid, it will not be etched by hydrofluoric acid.
次に第１図（ｈ）に示すように第二のフォトレジスト１
１を塗布し、ソース電極及びドレイン電極形成のための
パタンを形成する。Next, as shown in FIG. 1(h), a second photoresist 1 is applied.
1 to form a pattern for forming a source electrode and a drain electrode.
さらに第１図（ｉ）に示すように、燐酸系エツチング液
によりｎ型１ｎＡｓ層４及びｎ型ＩｎＧａＡｓ傾斜組成
層３をエツチングすることにより、ソース電極及びドレ
イン電極を形成する。最後に第二のフォトレジスト１１
を有機溶剤により除去する。Further, as shown in FIG. 1(i), the n-type 1nAs layer 4 and the n-type InGaAs graded composition layer 3 are etched using a phosphoric acid-based etching solution to form a source electrode and a drain electrode. Finally, the second photoresist 11
is removed using an organic solvent.
以上説明した製造工程により、弗酸系エツチング液によ
り電極中のπ層がエツチングされることなく、本発明の
実施例であるＧａＡｓ ＭＥＳＦＥＴのソース電極及び
ドレイン電極を製造することができる。Through the manufacturing process described above, the source electrode and drain electrode of the GaAs MESFET according to the embodiment of the present invention can be manufactured without etching the π layer in the electrode by the hydrofluoric acid etching solution.
ここでＴｉＮ １．ｔ ＩｎＧａＡｓ及び電極中のＡｕ
及びｐｔとは反応しない。そのため電極の側面にＴｉＮ
側壁部が残ることによるＦＥＴ特性の変化は生じない。Here, TiN1. t InGaAs and Au in the electrode
and does not react with pt. Therefore, TiN on the side of the electrode
The remaining sidewall portion does not cause any change in FET characteristics.
また耐弗酸性材料としては、ＩｎＧａＡｓ、 Ａｕ、
Ｐｔと反応しない材料ならＴｉＮ以外のもの例えばＷＮ
ｘなどでもかまわない。また、Ｔｉ層を含む多層膜電極
としては、Ｔｉ／Ｐｔ／Ａｕ以外の組み合せ例えばＴｉ
／Ａｕなどであっても良い。In addition, examples of hydrofluoric acid-resistant materials include InGaAs, Au,
If it is a material that does not react with Pt, other than TiN, such as WN.
It may be x, etc. In addition, as a multilayer film electrode containing a Ti layer, combinations other than Ti/Pt/Au, such as Ti
/Au etc. may be used.
また本実施例では、本発明をＧａＡｓ ＭＥＳＦＥＴの
ソース電極及びドレイン電極に適用したが、本発明の電
極の製造方法は、高電子移動度トランジスタ（Ｈｉｇｈ
Ｅｌｅｃｔｒｏｎ Ｍｏｂｉｌｉｔｙ Ｔｒａｎｓｉ
ｓｔｏｒ）やヘテロ接合バイポーラトランジスタ（Ｈｅ
ｔｅｒｏ−ｊｕｎｃｔｉｏｎ ＢｉｐｏｌａｒＴｒａｎ
ｓｉｓｔｏｒ）など他の構造の半導体装置の電極の製造
にも適用できる。Further, in this example, the present invention was applied to the source electrode and drain electrode of a GaAs MESFET, but the electrode manufacturing method of the present invention is applicable to a high electron mobility transistor (High
Electron Mobility Transi
stor) and heterojunction bipolar transistor (He
tero-junction Bipolar Tran
The present invention can also be applied to manufacturing electrodes of semiconductor devices with other structures such as SISTOR.
（発明の効果）
以上説明したように、本発明の電極の製造方法において
は、Ｔｉ層を含む多層膜電極の側面が耐弗酸性材料によ
って覆われているため、弗酸系エツチング液によって電
極中のＴｉ層が側面からエツチングされることはない、
従って、接触抵抗の増大や膜剥がれが生じることなくＴ
ｉ層を含む電極を製造できる。(Effects of the Invention) As explained above, in the electrode manufacturing method of the present invention, since the side surfaces of the multilayer electrode including the Ti layer are covered with a hydrofluoric acid-resistant material, the electrode is etched with a hydrofluoric acid-based etching solution. The Ti layer is not etched from the side.
Therefore, T without increasing contact resistance or film peeling occurs.
An electrode including an i-layer can be manufactured.
また、電極形成後のプロセスにおいても、弗酸系エツチ
ング液を用いることが可能であり、プロセスの自由度を
広げることができる。Moreover, in the process after electrode formation, it is possible to use a hydrofluoric acid etching solution, and the degree of freedom in the process can be expanded.
第１図（ａ）〜（ｉ）は、本発明の一実施例を説明する
ための、ｎ型ＧａＡｓ能動層上にｎ型ＩｎＧａＡ４を設
けその上に電極を設けた構造のノンアロイオーム性電極
を有する、ＧａＡｓ ＭＥＳＦＥＴのソース電極及びド
レイン電極の製造方法を示す工程断面図である。
１・・・半絶縁性ＧａＡｓ基板、２・・・ｎ型ＧａＡｓ
能動層、３＝・ｎ型ＩｎＧａＡｓ傾斜組成層、４−ｎ型
ＩｎＡｓ層、５１１．Ｓｉｏ２膜、６１．・第一のフォ
トレジスト、７・・・Ｔｉ、８・・・ｐｔ、９・・−Ａ
ｕ、 １０・・・ＴｉＮ膜、１１・・・第二のフォトレ
ジスト。1(a) to (i) show a non-alloy ohmic electrode having a structure in which n-type InGaA4 is provided on an n-type GaAs active layer and an electrode is provided thereon, for explaining one embodiment of the present invention. FIG. 2 is a process cross-sectional view showing a method for manufacturing source and drain electrodes of a GaAs MESFET. 1... Semi-insulating GaAs substrate, 2... N-type GaAs
Active layer, 3=.n-type InGaAs graded composition layer, 4-n-type InAs layer, 511. Sio2 membrane, 61.・First photoresist, 7...Ti, 8...pt, 9...-A
u, 10... TiN film, 11... second photoresist.
Claims (1)
にフォトレジストの所望のパタンを形成する工程と、前
記フォトレジストをマスクに絶縁膜をエッチングする工
程と、前記フォトレジスト上及び前記半導体基板上全面
に少なくともチタン（Ｔｉ）層を含む金属多層膜を形成
し前記フォトレジストを除去することにより、フォトレ
ジスト上の金属多層膜を取り除きＴｉを含む金属多層膜
より成る多層膜電極を形成する工程と、前記多層膜電極
と前記絶縁膜の隙間を埋めるように前記多層膜電極上及
び前記絶縁膜上に耐弗酸性材料を堆積する工程と、前記
多層膜電極と前記絶縁膜の隙間に堆積した部分を残して
前記耐弗酸性材料をエッチングする工程と、前記絶縁膜
を弗酸により除去する工程とを備えてなることを特徴と
する電極の製造方法。a step of depositing an insulating film on a semiconductor substrate; a step of forming a desired pattern of photoresist on the insulating film; a step of etching the insulating film using the photoresist as a mask; and a step of etching the insulating film on the photoresist and the semiconductor. By forming a metal multilayer film containing at least a titanium (Ti) layer on the entire surface of the substrate and removing the photoresist, the metal multilayer film on the photoresist is removed to form a multilayer film electrode made of a metal multilayer film containing Ti. a step of depositing a hydrofluoric acid-resistant material on the multilayer electrode and the insulating film so as to fill the gap between the multilayer electrode and the insulating film; and depositing a hydrofluoric acid-resistant material in the gap between the multilayer electrode and the insulating film. 1. A method for manufacturing an electrode, comprising the steps of: etching the hydrofluoric acid-resistant material while leaving the removed portion; and removing the insulating film with hydrofluoric acid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1914489A JPH02199825A (en) | 1989-01-27 | 1989-01-27 | Manufacture of electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1914489A JPH02199825A (en) | 1989-01-27 | 1989-01-27 | Manufacture of electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02199825A true JPH02199825A (en) | 1990-08-08 |
Family
ID=11991254
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1914489A Pending JPH02199825A (en) | 1989-01-27 | 1989-01-27 | Manufacture of electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02199825A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5270228A (en) * | 1991-02-14 | 1993-12-14 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating gate electrode in recess |
| JPH0715026A (en) * | 1991-02-19 | 1995-01-17 | Hikari Keisoku Gijutsu Kaihatsu Kk | Semiconductor element |
| US5459331A (en) * | 1993-05-10 | 1995-10-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, heterojunction bipolar transistor, and high electron mobility transistor |
-
1989
- 1989-01-27 JP JP1914489A patent/JPH02199825A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5270228A (en) * | 1991-02-14 | 1993-12-14 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating gate electrode in recess |
| JPH0715026A (en) * | 1991-02-19 | 1995-01-17 | Hikari Keisoku Gijutsu Kaihatsu Kk | Semiconductor element |
| US5459331A (en) * | 1993-05-10 | 1995-10-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, heterojunction bipolar transistor, and high electron mobility transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4337115A (en) | Method of forming electrodes on the surface of a semiconductor substrate | |
| US4839304A (en) | Method of making a field effect transistor with overlay gate structure | |
| US5464500A (en) | Method for taper etching metal | |
| JP3210657B2 (en) | Heterojunction bipolar transistor | |
| US4843024A (en) | Method of producing a Schottky gate field effect transistor | |
| US5362658A (en) | Method for producing semiconductor device | |
| JPH02199825A (en) | Manufacture of electrode | |
| JPH0351095B2 (en) | ||
| KR960005662A (en) | Field emission cold cathode and its manufacturing method | |
| JPH0228333A (en) | Manufacture of semiconductor device | |
| KR940006710B1 (en) | Manufacturing method of mes fet | |
| JP2002517091A (en) | Method for manufacturing a schottky diode | |
| JPS6323669B2 (en) | ||
| JP2658884B2 (en) | Method for manufacturing semiconductor device | |
| JP4072248B2 (en) | Manufacturing method of semiconductor device | |
| JPH0358433A (en) | Manufacture of field effect transistor | |
| JPS6340323A (en) | Formation of fine pattern | |
| KR930024106A (en) | Contact Forming Method of Semiconductor Device | |
| JPS60254733A (en) | Pattern forming method | |
| JPS61154177A (en) | Manufacture of semiconductor device | |
| JPS60167326A (en) | Manufacture of semiconductor device | |
| JPS58135667A (en) | Semiconductor device | |
| JPS6154620A (en) | Manufacture of semiconductor device | |
| JPS60182747A (en) | Manufacture of semiconductor device | |
| JPH04307936A (en) | Manufacture of semiconductor device |