JP3304595B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of forming a T-type gate electrode by forming a gate electrode and a sidewall insulating film on a semiconductor substrate, and then forming a selective growth layer only on the semiconductor substrate on both sides of the sidewall insulating film. The present invention relates to a method of manufacturing a semiconductor device to be formed, and more particularly to a method of manufacturing a semiconductor device such as a HEMT or a MESFET, which has recently been improved in performance by shortening a gate length and reducing source parasitic resistance.

[0002]

2. Description of the Related Art FIG. 6 is a diagram for explaining a method of reducing source parasitic resistance in a conventional method of manufacturing a semiconductor device. In the conventional method, as shown in FIG. 1A, a gate electrode made of, for example, WSi and an insulating side wall insulating film made of, for example, SiON are formed on a semiconductor substrate, and then a gas source MBE method or the like is used. Then, a selective growth layer having a high impurity concentration (high concentration) and a low resistivity is formed only on the semiconductor substrate on both sides of the sidewall insulating film, and then, as shown in FIG. A method for forming a source electrode and a drain electrode thereon has been proposed. It is well known that this method can reduce source parasitic resistance.

In the above conventional method, at the stage of performing the selective growth, the semiconductor substrate is heated at a high temperature (for example, GaAs).
Is heated to about 600 ° C. when a material having a low melting point is used for forming the gate electrode.
The Schottky junction between metal and semiconductor is adversely affected. Therefore, the gate electrode is made of a material having a high melting point (for example, WSi
Etc.). On the other hand, usually, a metal having a high melting point has a high resistivity, and as the gate length is reduced, the gate resistance is further increased.

FIGS. 7 and 8 show that in such a case, a T-type gate electrode is formed on a WSi gate electrode using a metal having a low resistivity, for example, Au, in order to reduce the gate resistance. It is an explanatory view of a conventional method for manufacturing a semiconductor device. According to this conventional method, the semiconductor substrate on which the selective growth layer has been formed is once taken out of the crystal growth apparatus, and a resist layer for a mask is applied as shown in FIG. Next, cueing of the gate electrode portion is performed by milling the resist layer (see FIG. 7B), and a metal such as Au having a low resistivity is deposited (see FIG. 7C). reference). In FIG. 8A, the deposited metal is removed by etching leaving a masked portion to be left as an electrode, and the resist layer is dissolved and removed to form a T-type gate electrode.
Finally, a source electrode and a drain electrode are formed (see FIG. 8B), and a series of manufacturing steps is completed.

[0005]

In the above conventional method,
In order to mask portions other than the upper part of the gate electrode, it is necessary to temporarily remove the semiconductor substrate from the crystal growth apparatus, form a resist layer, mill the resist layer, deposit a metal layer, and pattern the metal layer. is there. But,
Such a process is troublesome and increases the manufacturing cost of the semiconductor device.

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, it is an object of the present invention to provide a method of forming a resist layer in which a resist is applied, and the applied resist is etched to locate the top of a gate electrode. An object of the present invention is to provide an inexpensive method for manufacturing a high-performance semiconductor device.

[0007]

FIG. 1 is a diagram illustrating the principle of the present invention. According to the method of manufacturing a semiconductor device of the present invention, after a gate structure including a gate electrode and a sidewall insulating film is formed on a semiconductor substrate, a first structure is formed on both sides of the gate structure on the substrate.
Is selectively grown, and at least one second semiconductor layer is selectively grown on the first semiconductor layer, and a T-type gate electrode is formed thereon. At that time, the first
And the second semiconductor layer does not deposit on the gate structure.

FIG. 2 is an explanatory diagram of a method of manufacturing a semiconductor device according to the present invention. The method of manufacturing a semiconductor device according to the present invention is characterized in that the first semiconductor layer and the second semiconductor layer have different selectivities to etching. First
After the formation of the high-concentration selective growth layer, which is a semiconductor layer of (a), a second semiconductor layer having a different selectivity to etching from the first semiconductor layer is formed as shown in FIG. Then, a T-type gate electrode is formed by depositing and patterning a metal layer, and the second selective growth layer is removed as shown in FIG.

Further, a method of manufacturing a semiconductor device according to the present invention
The second semiconductor layer is a non-doped layer in which an impurity portion is not doped.

Further, the method of manufacturing a semiconductor device according to the present invention
The first semiconductor layer and the second semiconductor layer are made of different semiconductor materials.

[0011]

According to the method of manufacturing a semiconductor device of the present invention, since the second semiconductor layer is formed following the formation of the first semiconductor layer, the T-type gate electrode is formed following the formation of the high concentration selective growth layer. The insulating layer on the high-concentration selective growth layer required at the time of forming the high-concentration selective growth layer can be continuously formed in the same crystal growth apparatus as the formation of the high-concentration selective growth layer.

By growing the second semiconductor layer having a different selectivity to the etchant from the first semiconductor layer, only the second semiconductor layer can be selectively removed after the formation of the T-type gate electrode.

Further, by forming the second semiconductor layer by a non-doped layer, the first semiconductor layer which is a high concentration selective growth layer is formed.
An insulator layer can be easily obtained above the semiconductor layer.

Further, the second semiconductor layer is grown with a semiconductor different from the first semiconductor layer, that is, for example,
By forming the first semiconductor layer of GaAs and forming the non-doped layer of InGaP, after forming the T-type gate electrode, only the non-doped layer is selectively removed (HC
1 solution), the capacitance (input capacitance) between the gate and source electrodes due to the high dielectric constant of the insulator layer formed of the non-doped semiconductor
Can be prevented from increasing.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 3 to 5 are views for explaining steps of a method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 3A is a diagram showing the structure of the epitaxial layer 2 and is formed on a GaAs substrate by MOCVD or the like.
GaAs: 5000 Å and AlGaAs
A HEMT structure is manufactured by growing s: 1000 Å, GaAs: 500 Å, AlGaAs: 50 Å, and n-type AlGaAs: 1000 Å (n = 2 × 10 ¹⁸ cm ⁻³ ). The ratio of Al to Ga in AlGaAs is A
l: Ga = 3: 7.

Next, as shown in FIG. 3B, 2,000 Å of WSi is deposited on the epitaxial layer 2 by a sputtering method.
A photoresist mask is formed thereon.

Further, the WSi is removed by dry etching, leaving the resist mask portion masked by the resist, and thereafter, the resist mask is removed by an organic solvent or the like. Thereby, the gate electrode 4 is formed. Furthermore, a thickness of 4
1000 Å of SiON is deposited (FIG. 3).
(C)).

_{Furthermore, CHF 3, C 2 F 6} , by a dry etching method using a mixed gas of H _e, by etching the SiON that is the deposition by the thickness of SiON, side walls 6 made of SiON on both sides of the gate electrode 4 Is formed (see FIG. 3D).

Next, as shown in FIG.
The surface of the epitaxial layer 2 exposed as a result of the dry etching of the ION is coated on the surface of the epitaxial layer 2 by a gas source MBE method.
At a temperature of 00 ° C., the n-type GaAs layer 8 (n = 2 × 10 ¹⁸ c
m ⁻³ ) is grown by 1000 Å, and then undoped InGaP layer 1 is grown in the same crystal growth apparatus.
0 grows by 1000 angstroms. At this time, the GaAs layer 8 or the InGaP layer 10 is formed on the gate electrode 4 made of WSi or SiO 2 constituting the gate structure.
It is not deposited on the gate sidewall 6 made of N, but is deposited selectively on the epitaxial layer 2.

Au is vapor-deposited on the surface of the sample obtained above by 5,000 angstroms by a vacuum vapor deposition method, and a resist mask is formed on the vapor-deposited Au (see FIG. 4B).

Next, of Au deposited on the sample on which the resist mask is formed, Au other than the portion where the resist mask is formed is removed by milling using Ar ions, and then an organic solvent or the like is used. Then, the resist mask is removed, and a T-type gate 12 is formed. After that, only the non-doped InGaP layer 10 is selectively removed with an HCl solution (see FIG. 4C).

Next, as shown in FIG. 5A, SiON is deposited on the entire surface of the sample by using a plasma CVD method so as to protect the sample.

Finally, as shown in FIG. 5B, a resist mask is formed on the portion of the sample other than the source electrode 14 and the drain electrode 16, and the SiON of the source electrode 14 and the drain electrode 16 is dry-etched. A
uGe / Au is vacuum-deposited, and Au is removed from portions other than the source electrode 14 and the drain electrode 16 by a lift-off method.
By removing Ge / Au and further applying a heat treatment (alloying), HEMT fabrication is completed.

In the description of the embodiment of the present invention, the non-doped InGaP layer 10 is removed.
The P layer 10 need not be removed.

[0026]

As described above, according to the present invention, in the manufacture of a semiconductor such as an HEMT using selective growth, the formation of a T-type gate is unnecessary without performing an extra resist coating step and cueing of the gate structure. It is possible to improve the performance of the semiconductor device, simplify the manufacturing process, and reduce the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is an explanatory view (No. 1) of a step in a method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 4 is an explanatory view (2) of a step in a method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 5 is an explanatory view (No. 3) of a step in the method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 6 is an explanatory diagram (part 1) of a conventional technique.

FIG. 7 is an explanatory view (part 2) of a conventional technique.

FIG. 8 is an explanatory view (part 3) of a conventional technique.

[Explanation of symbols]

 2 epitaxial layer 4 gate electrode 6 sidewall 8 n-type GaAs layer 10 non-doped InGaP layer 12 T-type gate 14 source electrode 16 drain electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/338 H01L 29/778-29/812

Claims (6)

(57) [Claims] 1. A semiconductor device comprising a gate electrode and a side wall formed on a semiconductor substrate.
Forming a gate structure comprising an edge film; and selectively forming a first semiconductor layer on both sides of the gate structure.
Growing at least one second semiconductor layer on the first semiconductor layer
Selectively growing and depositing a metal layer on the gate structure and the second semiconductor layer
The step of causingForming a resist mask on the metal layer;  Formed on the metal layerTheFor parts other than the resist mask
A method for manufacturing a semiconductor, comprising: a step of forming a T-type gate electrode by removing a metal layer; and a step of removing the resist mask. Wherein said first and the semiconductor layer and the second semiconductor layer, you <br/> characterized by comprising a semiconductor material that is different for each other physician 請 Motomeko first semiconductor method of manufacturing according. 3. The method according to claim 1, further comprising the step of growing the first semiconductor layer.
Continuously growing the second semiconductor layer.
A method for manufacturing a semiconductor device according to claim 1 . Wherein wherein the first semiconductor layer and the second semiconductor layer, one of claims 1 to 3, characterized in that selectivity for etching is made of different semiconductor materials from each other
A method for manufacturing a semiconductor device according to claim 1 . 5. The second semiconductor layer is a non-doped layer.
The method according to any one of claims 1 to 4, wherein
The manufacturing method of the semiconductor device described in the above. 6. The method according to claim 1 , further comprising the step of removing said second semiconductor layer.
The method according to any one of claims 1 to 4, wherein
A method for manufacturing a semiconductor device according to claim 1.