JPH0499335A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To enable a T-type opening to be formed even without using an electron beam exposure device and mass production property to be increased by constituting a coated layer with a plurality of layers and increasing etching rate of layers out of a plurality of layers as they are further away from a semi-insulation substrate. CONSTITUTION:A dummy gate 2 is formed on a semi-insulation substrate, for example a GaAs wafer 1. A first nitriding film 3 is formed in a state where the dummy gate 2 is coated and a second nitriding film 4 is formed on it. When chemical etching is performed, a second nitriding film 5, a first nitriding film 4, and a dummy gate 2 at a lower part of an opening 6 are eliminated. The first and second nitriding films 3 and 4 are formed so that the second nitriding film 4 has larger etching rate than the first nitriding film 3, the second nitriding film 4 with a larger etching rate can be etched more widely than the first nitriding film 3, thus enabling a T-type opening 7 which is wider at the upper part to be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a field effect transistor, and particularly to a method of manufacturing a gate electrode.

[Prior Art] Conventionally, as a method for manufacturing the above-mentioned gate electrode, for example, the second
There was something like the one shown in the picture. First, as shown in FIG. 2(a), a first resist layer 11 and a second resist layer
A resist layer 12 is applied in sequence. Next, as shown in FIG. 3B, the second resist layer 12 is exposed to electron beam using an electron beam exposure device, and then the first resist layer 1
1 is subjected to electron beam exposure to form a T-shaped opening 13. In this case, the second resist layer 12 is formed wider than the first resist layer 11. Then, as shown in FIG. 2C, vapor deposition is performed so that a gate metal layer 14a is formed within the T-shaped opening 13. Note that a gate metal layer 14b is formed on the second resist layer 12 during vapor deposition. This is the gate metal layer. Finally, the gate metal layer 14b, the first and second resist layers 1 are removed by a lift-off method as shown in FIG.
．． 1.12 is removed. As a result, the gate metal layer 14
A becomes the gate electrode 15. According to this manufacturing method, the gate length of the gate electrode 15 can be shortened and the electrode area can be increased, thereby reducing parasitic capacitance and gate resistance. It is possible to obtain an effective transistor.

[Problem to be solved by the invention] In the above manufacturing method, in order to form the T-shaped opening 13 and obtain a fine gate length, an electron beam exposure device with high drawing precision must be used. However, the equipment investment was expensive, and the processing speed was slow, resulting in poor productivity.

An object of the present invention is to obtain a fine gate length and a T-shaped opening without using an electron beam exposure device.

[Means for Solving the Problems] In order to achieve the above object, the first invention provides a step of forming a dummy gate with physical properties removable by chemical etching on one surface of a semi-insulating substrate by tri-etching. and forming a covering layer with physical properties removable by chemical etching on the surface so as to cover the dummy gate, and forming a portion of the covering layer corresponding to the dummy gate and the dummy gate. The steps include removing by chemical etching to form an opening and forming a gate metal layer in the opening.

Further, in a second invention, in the first invention, the above-mentioned coating layer is formed as a plurality of layers, and the etching rate of the plurality of layers increases as the distance from the layer in contact with the surface of the semi-insulating substrate increases. It is configured so that it becomes larger.

[Operation] According to the first invention, since the dummy gate is formed by tri-etching, it is etched to the inner side of the periphery of the resist pattern used for tray etching, so that a fine gate length can be obtained. You can get

Further, according to the second invention, the coating layer is composed of a plurality of layers,
The etching rate increases as the distance from the layer that is in contact with the top surface of the substrate increases.
When removing the portion corresponding to the dummy metal layer and the dummy metal layer by chemical etching, the coating layer having a high etching rate is etched to a wide width. A T-shaped opening can thus be obtained.

[Example] As shown in FIG. 1(a), a semi-insulating substrate, for example Ga
A dummy gate 2 is formed on an As wafer l.

For example, a nitride film 1, which can be chemically etched and does not dissolve when exposed to light, is formed on the wafer L, a resist is applied on the nitride film, and the resist is left in the area where the dummy gate 2 is to be provided. Remove other resists.

In this method, the nitride film other than that covered by the resist is removed by zero-order dry etching, which is performed by exposing the resist to light using a mask pattern, and then the resist is removed.

When tri-etching is performed, the nitride film is removed 0.1 to 0.2 .mu.I inside the peripheral edge of the remaining resist. Therefore, - using a boat fishing optical exposure device, 0.3
If a resist having a length of 0.54 m is left in the above region, a dummy gate 2 having a fine gate length of 0.2 to 0.3 μm can be formed.

Next, as shown in FIG. 2B, a first nitride film 3 is formed to cover the dummy gate 2, and a second nitride film 4 is formed over the first nitride film 3. These nitride films 3.4 may be formed by, for example, changing the composition of the first and second nitride films 3.4 so that when chemical etching is performed, the etching rate of the second nitride film 4 is higher. , and are formed with different thicknesses.

Next, a resist layer 5 is applied on top of the second nitride film 4,
As shown in FIG. 2C, an opening 6 is formed by exposure to correspond to the dummy gate 2.

As is clear from the figure (C), this opening 6 is longer than the dummy gate length.

Next, when chemical etching is performed, the second nitride film 5, first nitride film 4, and dummy gate 2 below the opening 6 are removed, as shown in FIG. 2D. Since the first and second nitride films 3.4 are formed so that the etching rate of the second nitride film 4 is higher than that of the first nitride film 3, the etching rate of the second nitride film 4 is higher than that of the first nitride film 3. Since the second nitride film 4 is etched wider than the first nitride film 3, a T-shaped opening 7 is finally formed which is wider toward the top, as shown in FIG. 3(d). .

Then, gate metal is deposited from the resist layer 5 side. As a result, a gate metal 8a is deposited inside the T-shaped opening 7, and a gate metal 8b is also deposited on the resist layer 5 at the same time, as shown in FIG. 2(e).

Next, the resist layer 5 and the gate metal 8b above it are removed by a lift-off method, as shown in FIG. 5(f).

Finally, the first and second nitride films 3.4 are removed by chemical etching. As a result, a T-shaped gate electrode 9 is obtained.

[Effects of the Invention] As described above, according to the first invention, since the dummy gate is formed using the tri-etching method, the gate length of the finally obtained gate electrode can be adjusted using an electron beam exposure device. It is possible to make it finer without using it. Further, according to the second invention, the coating layer is composed of a plurality of layers, and the etching rate of the plurality of layers increases as the distance from the semi-insulating substrate increases. A T-shaped opening can be formed without using an exposure device. According to the first and second aspects of the invention, it is not necessary to use an electron beam exposure device, and instead it is possible to use a boat-type exposure device, resulting in high mass productivity and good high-frequency characteristics. By obtaining field effect transistors, the yield can be improved and field effect transistors can be manufactured at low cost.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a method for manufacturing a field effect transistor according to the present invention, and FIG. 2 is a diagram showing a conventional method for manufacturing a field effect transistor. l...GaAs wafer, 2...dummy gate,
3...first nitride film, 4...second nitride film, 5
... Resis l~ layer, 7... T-shaped opening, 8a,
8b...Gate metal, 9...Gate electrode. Figure 2

Claims (2)

[Claims] (1) Forming a dummy gate with physical properties removable by chemical etching on one surface of a semi-insulating substrate by tri-etching, and forming a covering layer with physical properties removable by chemical etching on the surface of the dummy gate. forming an opening in the opening by removing a portion of the covering layer corresponding to the dummy gate and the dummy gate by chemical etching, and forming a gate metal layer in the opening. A method of manufacturing a field effect transistor, comprising: forming a field effect transistor. (2) In the method for manufacturing a field effect transistor according to claim 1, the covering layer is formed of a plurality of layers, and the plurality of layers are etched away from the layer contacting the surface of the semi-insulating substrate. A method for manufacturing a field effect transistor, characterized in that the field effect transistor is configured to have a large rate.