JPS6039875A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6039875A JPS6039875A JP14844083A JP14844083A JPS6039875A JP S6039875 A JPS6039875 A JP S6039875A JP 14844083 A JP14844083 A JP 14844083A JP 14844083 A JP14844083 A JP 14844083A JP S6039875 A JPS6039875 A JP S6039875A
- Authority
- JP
- Japan
- Prior art keywords
- films
- film
- etching
- insulating film
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 2
- 238000007598 dipping method Methods 0.000 abstract 1
- 238000005406 washing Methods 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体装置の製造方法のうら、特にセルファラ
インによって近接した電極間に他の電極領域を高精度に
形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming another electrode region between adjacent electrodes using a self-alignment line with high precision.
（ｂｌ 従来技術と問題点
半導体装置はその高集積化のため、ソース、ゲート、ド
レインの各電極が近接して設けられている。例えばＧａ
Ａｓ Ｆ Ｅ Ｔはマイクロ波帯における高利得、高出
力のショットキ障壁型電界効果トランジスタ（ＳＢ−Ｆ
ＥＴ）として知られているが、間隔数μｍのソース電極
とドレイン電極との間に幅１〜２μｍのゲート電極が設
けられた構造となる。(bl) Prior Art and Problems Due to the high integration of semiconductor devices, the source, gate, and drain electrodes are provided close to each other.For example, Ga
As FET is a high gain, high output Schottky barrier field effect transistor (SB-F) in the microwave band.
ET), it has a structure in which a gate electrode with a width of 1 to 2 μm is provided between a source electrode and a drain electrode with an interval of several μm.
このようなＦＥＴにおいて、更に高利得化、高出力化を
目指したリセス型と呼ばれる構造があり、第１図にその
実体図を示している。図示の様に、ＧａＡｓ基板１」二
にソース電極、ドレイン領域２とゲート電極３が設けら
れ、ゲート電極は半導体基板の凹部領域４に形成された
構造である。且つ、ゲート電極３とソース電極、ドレイ
ン電極２とは異なる材質からなり、ＧａＡｓＦＥＴでは
ゲート電極３はアルミニウム、ソース電極およびドレイ
ン電極２ば金（Ａｕ）系金属が使用される。Among such FETs, there is a structure called a recessed type which aims at higher gain and higher output, and FIG. 1 shows the actual structure thereof. As shown in the figure, a source electrode, a drain region 2, and a gate electrode 3 are provided on a GaAs substrate 1''2, and the gate electrode has a structure formed in a recessed region 4 of the semiconductor substrate. Furthermore, the gate electrode 3 and the source and drain electrodes 2 are made of different materials; in the GaAsFET, the gate electrode 3 is made of aluminum, and the source and drain electrodes 2 are made of a gold (Au) based metal.
このようなリセス構造の凹部領域形成概要を第２図およ
び第３図に示す。まず、第２図に示すように二酸化しノ
リコン（Ｓｉ０２）膜５とレジスト膜６とをマスクにし
てソース、ドレインの電極材料２を被着する。次いで、
レジスト膜６と５ｉ０２膜５とを除去し、同時にリフト
オフによってレジスト膜６上の電極材料を除去して、ソ
ース電極およびドレイン電極２を形成する。次いで、第
３図に示すように再びレジスト膜７をパターンニングし
て、これをマスクにして半導体基板１をエツチングし凹
部領域４を形成する。An outline of the formation of the recessed region of such a recessed structure is shown in FIGS. 2 and 3. First, as shown in FIG. 2, source and drain electrode materials 2 are deposited using a silicon dioxide (Si02) film 5 and a resist film 6 as masks. Then,
The resist film 6 and the 5i02 film 5 are removed, and at the same time, the electrode material on the resist film 6 is removed by lift-off to form the source electrode and the drain electrode 2. Next, as shown in FIG. 3, the resist film 7 is patterned again, and using this as a mask, the semiconductor substrate 1 is etched to form the recessed region 4.
しかし、上記形成方法によればソース電極、ドレイン電
極２と四部領域４との間に位置ずれを生じる欠点がある
。凹部領域４の位置ずれはゲート電極が位置ずれするこ
とになり、そのためにトランジスタ特性がバラツキを生
じる原因となる。However, the above-mentioned formation method has a drawback that misalignment occurs between the source and drain electrodes 2 and the four-part region 4. Misalignment of the recessed region 4 causes misalignment of the gate electrode, which causes variations in transistor characteristics.
（Ｃ） 発明の目的
本発明は、このような問題点を解消させ、セルファライ
ンによって高精度に電極間隔を形成する製造方法を提案
するものである。(C) Object of the Invention The present invention solves these problems and proposes a manufacturing method in which the electrode spacing is formed with high precision using self-alignment.
＋ｄ＋ 発明の構成
その目的は、第１絶縁膜を被覆した基板上に選択的にレ
ジスト膜を形成し、該レジスト膜をマスクにして前記露
出した第１絶縁膜を除去し、更に該レジスト膜下の周縁
部をサイドエッチする工程、次いで電極膜を被着し、該
電極膜上に第１絶縁膜とエツチングレートの異なる第２
絶縁膜を被覆した後、前記レジスト膜をエツチング除去
して、同時に該レジスト膜上面の電極膜と第２絶縁膜と
をリフトオフして除去する工程、次いで露出した第１絶
縁膜を除去して基板面の露出領域を工・ンチングする工
程が含まれてなる半導体装置の製造方法によって達成さ
れる。+d+ Structure of the Invention The object is to selectively form a resist film on a substrate covered with a first insulating film, remove the exposed first insulating film using the resist film as a mask, and further remove the exposed first insulating film under the resist film. Next, an electrode film is deposited on the electrode film, and a second insulating film having an etching rate different from that of the first insulating film is formed on the electrode film.
After covering the insulating film, the resist film is removed by etching, and at the same time, the electrode film and the second insulating film on the upper surface of the resist film are lifted off and removed, and then the exposed first insulating film is removed and the substrate is removed. This is achieved by a method for manufacturing a semiconductor device that includes a step of etching the exposed region of the surface.
（ｅｌ 発明の実施例
以下１図面を参照してＧａＡｓ Ｆ Ｅ Ｔの電極形成
の実施例によって詳細に説明する。(el) Embodiments of the Invention A detailed description will be given below of an embodiment of electrode formation of a GaAs FET with reference to the drawings.
第４図ないし第１０図は本発明にかかる形成方法の工程
順断面図である。まず、第４図に示すようにＧａＡｓ基
板ｌｌ上に化学気相成長（ＣＶＤ ）法によって膜厚約
５０００人の５Ｉ０２膜１２（第１絶縁膜）を被着し、
更にその上に膜厚１μｍ程度のポジ系レジスト膜１３を
パターンニングする。FIGS. 4 to 10 are cross-sectional views in the order of steps of the forming method according to the present invention. First, as shown in FIG. 4, a 5I02 film 12 (first insulating film) with a thickness of approximately 5000 was deposited on a GaAs substrate 1 by chemical vapor deposition (CVD).
Furthermore, a positive resist film 13 having a thickness of about 1 μm is patterned thereon.
次いで、第５図に示すようにレジスト膜１３をマスクに
して５ｉ０２膜１２を弗酸系エソチンダ液でエツチング
除去し、且つ過度にエツチングしてレジスト膜１３上周
縁部の５ｉ０２膜１２にサイドエッチを起こさせる。レ
ジスト膜１３の幅を５μｍとずれば、サイドエッチは周
縁からそれぞれ１μＩ１１程度まで進行させる。Next, as shown in FIG. 5, using the resist film 13 as a mask, the 5i02 film 12 is removed by etching with a hydrofluoric acid-based ethotinda solution, and the 5i02 film 12 at the upper peripheral edge of the resist film 13 is side-etched by excessive etching. make me wake up If the width of the resist film 13 is shifted to 5 .mu.m, the side etching will proceed from the periphery to about 1 .mu.I11.
次いで、第６図に示すようにその上面に林着法で膜厚２
０００人程度のオーミック電極１４を被着する。Next, as shown in Figure 6, a film with a thickness of 2
Approximately 1,000 ohmic electrodes 14 are deposited.
更に、第７図に示すようにその上にプラズマＣＶＤ法に
よって膜厚１０００人弱の窒化シリコン（Ｓｉ３Ｎ４）
膜１５（第２絶縁膜）を被着する。プラズマＣＶＤ法に
よって被着すれば、サイドエッチされた内面まで十分に
廻り込んでＳ １３Ｎ ４膜１５が被着される。Furthermore, as shown in Fig. 7, a silicon nitride (Si3N4) film with a thickness of less than 1000 nm is deposited on top of it by plasma CVD.
A film 15 (second insulating film) is deposited. If deposited by plasma CVD, the S 13N 4 film 15 will be deposited sufficiently around the side-etched inner surface.
次いで、第８図に示すようにアセトンに浸漬して超音波
洗浄するとレジスト膜１３上のＳ ｉ３Ｎ ４膜１５が
破壊されてレジスト膜１３が／８解し、同時にレジスト
膜上のＳ ｒ３Ｎ ４膜１５および電極１４がリフトオ
フによって除去される。次いで、第９図に示すように弗
酸系溶液によって露出した５ｉ０２１Ｗ１２を工。Next, as shown in FIG. 8, the Si3N4 film 15 on the resist film 13 is destroyed by ultrasonic cleaning by immersion in acetone, and the resist film 13 is reduced to 1/8, and at the same time the Sr3N4 film on the resist film is destroyed. 15 and electrode 14 are removed by lift-off. Next, as shown in FIG. 9, the exposed 5i021W12 was treated with a hydrofluoric acid solution.
チング除去する。Remove tinging.
次いで、第１Ｏ図に示すようにＳ ｉ３Ｎ ４膜１５を
マスクとして、ＧａＡｓ基板１１をアルカリ系溶液又は
弗酸系溶液によりエツチングして凹部領域１６を形成し
、最後にＣ］；４ ト０２ガスによるドライエツチング
によって５１３Ｎ ４ ＋１Ｗ １−５をエツチングし
て取り除（。Next, as shown in FIG. 1O, using the Si3N4 film 15 as a mask, the GaAs substrate 11 is etched with an alkaline solution or a hydrofluoric acid solution to form a concave region 16, and finally, a concave region 16 is etched using the Si3N4 film 15 as a mask. 513N 4 +1W 1-5 was removed by dry etching (.
このようにすれば、オーミック電極１４と凹部領域１６
の凹部領域とが高精度に形成され、従ってソース、ドレ
インの各電極と凹部領域との位置ずれ、率いては凹部領
域（リセス部）に設けられるゲート電極との位置ずれは
なくなる。In this way, the ohmic electrode 14 and the recessed region 16
The recessed region is formed with high precision, and therefore, there is no misalignment between the source and drain electrodes and the recessed region, and there is no misalignment between the gate electrode provided in the recessed region (recessed portion).
ここに、上記実施例は第１絶縁膜を５ｉ０２膜。Here, in the above embodiment, the first insulating film is a 5i02 film.
第２絶縁膜をＳ ｉ３Ｎ ４膜として説明したが、リフ
ｌ−オフが可能でエツチングレートが異なるものならば
、他の材質の膜を用いても差支えない。Although the second insulating film has been described as a Si3N4 film, films made of other materials may be used as long as they can be refloated and have different etching rates.
又、上記はリセス構造のＧａＡｓ Ｆ Ｅ Ｔ電極形成
の実施例であるが、リセス型でないＧａＡｓ Ｆ Ｅ
Ｔ ＪＰｓｉＦＥＴにも適用できることは勿論である。Further, although the above is an example of forming a GaAs FET electrode with a recessed structure, a GaAs FET electrode without a recessed structure
Of course, it can also be applied to TJPsiFET.
（ｆｌ 発明の効果
以上の説明から明らかなように、本発明によれば電極間
隔が極めて精度良く形成できて、高品質のトランジスタ
（ＦＥＴ）が得られる効果が大きいものである。(fl) Effects of the Invention As is clear from the above explanation, the present invention has a significant effect in that the electrode spacing can be formed with extremely high accuracy and a high quality transistor (FET) can be obtained.
第１図は５Ｂ−ＦＥＴの実体図、第２図および第３図は
従来の形成工程順断面図、第４図ないし第１Ｏ図は本発
明にかかる形成工程順断面図である。
図中、１，１１はＧａＡｓ基板、２はソース電極、ドレ
イン電極、３はゲート電極、４．１６は凹部領域。
５．１２は５ｉ０２膜、６，７．１３はレジスト膜、１
４第１図
第２＠
第３閏
第５図
−
第 ６閃
ビシ
ｆｆ１Ｂｌ’７１
−
＠１０１７１FIG. 1 is an actual diagram of a 5B-FET, FIGS. 2 and 3 are sectional views in the order of conventional forming steps, and FIGS. 4 to 10 are sectional views in order of the forming steps according to the present invention. In the figure, 1 and 11 are GaAs substrates, 2 is a source electrode and a drain electrode, 3 is a gate electrode, and 4.16 is a recessed region. 5.12 is 5i02 film, 6, 7.13 is resist film, 1
4 Figure 1 Figure 2 @ 3rd leap Figure 5 - 6th flash ff1Bl'71 - @10171
Claims (1)
成し、該レジスト膜をマスクにして前記露出した第１絶
縁膜を除去し、更に該レジスト膜下の周縁部をサイドエ
ッチする工程、次いで電極膜を被着し、該電極膜上に第
１絶縁膜とエンチングレートの異なる第２絶縁膜を被覆
した後、前記レジスト膜をエツチング除去して、同時に
該レジスト膜上面の電極膜と第２絶縁膜とをリフトオン
して除去する工程、次いで露出した第１絶縁膜を除去し
て基板面の露出領域をエツチングする工程が含まれてな
ることを特徴とする半導体装置の製造方法。A step of selectively forming a resist film on the substrate coated with the first insulating film, removing the exposed first insulating film using the resist film as a mask, and further side-etching the peripheral portion under the resist film. Then, after depositing an electrode film and covering the electrode film with a second insulating film having a different etching rate from the first insulating film, the resist film is removed by etching, and at the same time the electrode film on the upper surface of the resist film is removed. 1. A method of manufacturing a semiconductor device, comprising the steps of lifting-on and removing the first insulating film and the second insulating film, and then removing the exposed first insulating film and etching the exposed region on the substrate surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14844083A JPS6039875A (en) | 1983-08-12 | 1983-08-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14844083A JPS6039875A (en) | 1983-08-12 | 1983-08-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6039875A true JPS6039875A (en) | 1985-03-01 |
Family
ID=15452839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14844083A Pending JPS6039875A (en) | 1983-08-12 | 1983-08-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6039875A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014029983A (en) * | 2012-07-05 | 2014-02-13 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
-
1983
- 1983-08-12 JP JP14844083A patent/JPS6039875A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014029983A (en) * | 2012-07-05 | 2014-02-13 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
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