JPH0713982B2 - Method of manufacturing Schottky field effect transistor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a Schottky field effect transistor used for microwave communication or the like.

[Conventional technology]

Conventionally, when this type of Schottky field effect transistor is used in a high output amplifier circuit, the breakdown voltage between the gate and drain electrodes has been a practical problem. It is known that as a device structural factor that determines the breakdown voltage, electric field concentration occurs on the drain electrode side in the recess structure in which the high-concentration epitaxial layer is etched. As an effective device structure design technology for this, there is a graded recess structure having a gentle angle with respect to the substrate surface as shown in FIG. This is a method of preventing the concentration of an electric field by reducing the geometrical curvature of the recess structure.

On the other hand, as another factor to be considered in designing the device structure, there is a reduction in the distance between the source and drain electrodes, and it is expected to reduce the extrinsic resistance component with respect to the device characteristics.

In this respect, if the graded recess structure is simply adopted for the high-concentration epitaxial layer having a constant thickness, the resistance component between electrodes is rather increased. A graded recessed asymmetric shape is effective.

FIG. 5 shows a conventional technique based on the viewpoints described above.
There is an example using the crystal anisotropy of GaAs (Japanese Patent Application No. 55-88135). In this technique, on a GaAs substrate having a [112] plane 7, a drain electrode side is a [111] plane 9 and a source electrode side is a [(-1) (-
1) 1] By using the surface 8, an asymmetric recess structure in which the angles of the surface with respect to the substrate surface are 19 ° and 90 °, respectively, is realized.

[Problems to be solved by the invention]

However, the above-described conventional recess structure is effective only for a specific crystal orientation, and therefore has a drawback that it is significantly restricted in designing a device structure. Usually GaAs
Substrates used for manufacturing field effect transistors are [10
0] surface, the above-mentioned conventional example cannot be applied as it is.

The present invention has been made to address the above-mentioned problems, and enables an asymmetric recess structure that does not depend on the crystal orientation of the substrate to bring about an improvement in drain breakdown voltage, obtain an electrode with a fine gate length, and provide a recess structure. It is an object of the present invention to provide a method of manufacturing a Schottky field effect transistor which can form a gate electrode in a self-aligned manner, has excellent productivity, and has improved characteristics, uniformization, and miniaturization.

[Means for solving problems]

The method of manufacturing a Schottky field effect transistor according to the first aspect of the present invention includes a step of providing an opening in an insulating film formed on an active layer of a semiconductor substrate to expose the active layer, and a photoresist on the surface. And a step of forming a photoresist opening in a part of the insulating film on the source side and a part of the insulating film removal region following the step of applying a heat treatment to the photoresist to adjust the adhesion between the photoresist and the active layer. ,
A step of etching the active layer with an etching solution using a photoresist and an insulating film as a mask to form an asymmetric recess structure in the active layer; and a step of removing at least a part of the etching mask of the insulating film on the source electrode side without removing the source electrode. Forming a gate electrode in self-alignment with the side recess edge.

The method of manufacturing the Schottky field effect transistor according to the second aspect of the present invention comprises a step of exposing the active layer by providing an opening in an insulating film formed on the active layer of the semiconductor substrate and applying a photoresist to the surface. Then, a step of forming a photoresist opening over a part of the insulating film on the source side and a part of the subsequent insulating film removal region, a step of removing the insulating film in the exposed opening, and a contact between the photoresist and the active layer Property, a step of etching the active layer with an etching solution using a photoresist as a mask to form an asymmetric recess structure in the active layer, a gate electrode metal is attached using the photoresist as a mask, and a source electrode side is formed. And a step of forming a gate electrode by self-aligning with the recess edge of the.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a Schottky field effect transistor manufactured according to an embodiment of the present invention.

In FIG. 1, the source electrode 1 and the drain electrode 5 are made of ohmic electrode material AuGe or the like. Further, the gate electrode 3 is made of Al or the like that exhibits good Schottky characteristics with respect to the GaAs substrate 6, and can form an overlay structure on the insulating film 2 at the recess end on the side of the source electrode 1. For this insulating film 2, SiO ₂ or Si ₃ N ₄ can be used by the CVD method. Further, only the recess shape 4 on the drain electrode side is formed as a gentle structure with respect to the surface.

2 (a) to 2 (c) are cross-sectional views shown in the order of steps for explaining the manufacturing method of the embodiment of the present invention.

First, as shown in FIG. 2A, the active layer of the semiconductor substrate is
An insulating film SiO ₂ 102 is formed on 103, and an opening is provided in the insulating film 102 to form a recess structure to expose the active layer 103. A pattern is designed such that these processes are arranged between the source electrode metal 101 and the drain electrode metal 104.

Next, as shown in FIG. 2B, a photoresist is applied to the surface, exposed, and developed to expose a part of the insulating film 102 in the opening, and one of the insulating film removed regions following it. The part is also exposed.

Then, heat treatment is applied to the photoresist
The adhesion between the active layer 103 and 105 is adjusted. Next, using the photoresist 105 and the insulating film 102 as a mask, etching is performed using an etchant for the active layer 102 containing H ₂ O ₂ and H ₃ PO ₄ as main components to form an asymmetric recess structure 106.

Here, with respect to the etching solution, in order to easily allow the etching solution to enter the contact portion between the insulator SiO ₂ 102 and the photoresist 105 and the surface of the active layer 103, the etching shape should be an undercut shape. We are using. The undercut amount is controlled by utilizing the difference in adhesiveness between the materials on both sides of the opening of the photoresist 105, and an asymmetric recess structure is formed.

The control of the recess structure can be performed easily by performing heat treatment at 80 ° C. to 200 ° C. for 30 minutes to 1 hour in the resist 105 after patterning, for example, in the case of a positive resist containing a novolac resin as a main component, Can be controlled. This is a general processing method called so-called after-baking or post-baking for resist processing. On the contrary, it is also possible to reduce the adhesiveness by washing with water.

Further, the undercut on the drain side does not proceed indefinitely due to the presence of the insulating film 102 on the drain side. Therefore, the undercut does not reach the drain electrode portion, and the parasitic resistance of the drain does not become extremely large.

Next, as shown in FIG. 2C, after forming the recess structure 106, the gate electrode 107 is arranged by using a vapor deposition method or the like.
As is apparent from the figure, at this time, the gate electrode 107 is arranged so as to partially cover the insulating film 102. Then, the photoresist is removed by the lift-off method to obtain the device structure shown in FIG.

3 (a) to 3 (c) are cross-sectional views showing the manufacturing steps of another embodiment of the present invention in order of process steps.

First, as shown in FIG. 3 (a), FIG.
As shown in FIG. 2B, an opening is provided in the insulating film 202 formed on the active layer 203 of the semiconductor substrate to expose the active layer. Next, a photoresist is applied to the surface, and a photoresist opening is provided over a part of the source-side insulating film and a part of the subsequent insulating film-removed region.

Next, as shown in FIG. 3B, the exposed insulating film is removed by etching. In that case, a structure is formed in which the insulating film is in contact with the active layer on the source side of the opening and the photoresist is in contact with the active layer on the drain side. Then, heat treatment is performed to adjust the adhesion between the photoresist and the active layer.

Next, as shown in FIG. 3C, the active layer is etched using the photoresist 205 as a mask to form an asymmetric recess structure in the active layer. Then, a gate electrode metal 207 such as Al is deposited using the photoresist 205 as a mask, and the metal on the photoresist is removed by a lift-off method, whereby the gate electrode can be formed in self-alignment with the recess edge on the source electrode side. In this case, an electrode structure which does not cover the insulator SiO ₂ 202 can be obtained.

As described above, the present invention, by utilizing the difference in adhesion resistance to the etching solution of the mask material during etching of the recess structure formation, regardless of the substrate crystal plane,
This has the effect of forming an asymmetric recess structure.

This is an effect of improving the drain breakdown voltage in terms of device characteristics.

In addition, the formation of the asymmetric recess structure and the formation of the gate electrode can be processed in a continuous process. This will be described below.

As shown in the embodiments of FIGS. 2A to 2C and FIGS. 3A to 3C, the gate electrode is formed in alignment with the recess edge on the source electrode side. It may be attributed to the homogenization of characteristics such as mutual conductance in device manufacturing.
This means that the transconductance is greatly affected by factors in the device structure such as the recess shape on the source and gate electrodes and on the source electrode side. According to the present invention, not only the asymmetric recess structure is used, but also these effects can be achieved at the same time. Moreover, FIG.
In the embodiment shown in (c), since the insulator 102 is partially exposed and covered with the gate electrode material with respect to the resist opening dimension l ', the actual gate electrode dimension is l.
Stipulated in.

This has the effect of attaining a fine gate electrode size exceeding the minimum patterning limit of the resist in improving the device characteristics by miniaturizing the gate electrode size.
Such a method is possible by using an exposure apparatus technique which has been particularly developed in recent years. In steppers and the like, sophistication of alignment accuracy has been achieved far beyond the minimum patterning dimension, and the applicability of the above method is shown.

〔The invention's effect〕

As described above, according to the present invention, it is possible to manufacture an asymmetric recess structure that does not depend on the crystal orientation of the substrate, it is possible to improve the drain breakdown voltage, and to self-align an electrode with a fine gate length. It is possible to form the Schottky field effect transistor with high productivity, high reliability, and miniaturization.

[Brief description of drawings]

FIG. 1 is a sectional view of a Schottky field effect transistor manufactured according to an embodiment of the present invention, and FIGS.
FIG. 3C is a sectional view showing the manufacturing method of one embodiment of the present invention in the order of steps, and FIGS. 3A to 3C are for explaining a manufacturing method of another embodiment of the present invention. FIG. 4 is a cross-sectional view of the conventional graded recess structure, and FIG. 5 is a cross-sectional view of the conventional asymmetric recess structure utilizing crystal plane orientation. 1 ... Source electrode, 2 ... Insulating film, 3 ... Gate electrode,
4 ... Asymmetric recessed surface, 5 ... Drain electrode, 6 ...
... Active layer, 7 ... GaAs [112] plane, 8 ... GaAs [(-
1) (-1) 1] plane, 9 ... GaAs [111] plane, 101 ... Source electrode metal, 102, 202 ... Insulating film, 103, 203 ... Active layer, 104 ... Drain electrode metal, 105, 205 ... Photoresist , 106 ... Recessed surface, 107, 207 ... Gate electrode metal.

Claims (2)

[Claims] 1. A step of providing an opening in an insulating film formed on at least an active layer between a source and a drain of a semiconductor substrate to expose the active layer, and a part of the insulating film on the source side and a subsequent step. Forming a photoresist having an opening over a part of the exposed portion of the active layer, the adhesiveness with the active layer being lower than the adhesiveness between the active layer and the insulating film; A step of forming an asymmetric recess structure by selectively etching the active layer by using the insulating film exposed in the photoresist opening and the photoresist as a mask and using the insulating film on the drain side to stop undercut A method of manufacturing a Schottky field effect transistor, comprising: 2. A step of forming an opening in an insulating film formed on at least an active layer between a source and a drain of a semiconductor substrate to expose the active layer, and a part of the insulating film on the source side and the subsequent step. Forming a photoresist having an opening over a part of the exposed portion of the active layer, the adhesiveness with the active layer being lower than the adhesiveness between the active layer and the insulating film; The step of removing the insulating film in the photoresist opening and the active layer exposed in the photoresist opening by using the insulating film and the photoresist as a mask and using the insulating film on the drain side for stopping undercut And a step of selectively etching to form an asymmetric recess structure, a method of manufacturing a Schottky field effect transistor.