JPS5833714B2 - Method for manufacturing gallium arsenide Schottky barrier gate field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a Schottky barrier gate field effect transistor using a gallium arsenide semiconductor.

Schottky barrier gate field effect transistor (hereinafter 5)
The operation of the BGFET (BGFET) is based on the fact that a human input signal applied to the gate electrode changes the width of the Schottky barrier depletion layer formed under the gate electrode, thereby changing the conductance of the channel layer between the source and drain.

In order to obtain good electrical characteristics of the 5BGFET, the structural conditions must be met: first, the gate length must be as short as possible, and the gate wiring resistance must be low.

Second, parasitic resistance and capacitance between source and gate and between gate and drain should be as small as possible.

However, although various manufacturing methods have been used in the past, no method has been found that satisfies these conditions.

An example of a conventional manufacturing method using gallium arsenide (GaAs) will be explained with reference to FIG.

Figure 1 shows 5BG obtained by the most common manufacturing method.
This figure shows a cross section of the FET structure, and shows a carrier concentration of 5~ epitaxially grown on an insulating gallium arsenide substrate 1.
10×1016cfr1. -3, the surface of the n-type gallium arsenide crystal 2 was covered with a photoresist film, and by photolithography,
After removing the photoresist film in the source and drain regions, an electrode metal is deposited in a high vacuum, the deposited metal on the photoresist film is removed together with the photoresist film, and heat treatment is performed to make the source 3 and drain 4 ohms. Sex electrodes are shown.

Thereafter, using photoresist again, the crystal surface other than the n-type gallium arsenide surface in the gate region is covered with a gate metal by photolithography, and the gate metal on the photoresist film is removed together with the photoresist film in the same manner as above. This is a 5BGFET in which a gate electrode is formed.

Also, after depositing source and drain metal on the GaAs substrate except for the gate region, using this as a mask, G
The active layer of the aAs substrate is etched away to form a recess of a predetermined depth.

At this time, the GaAs substrate under the edge of the mask is also etched in the side direction, so that the source and drain metal edges have an eaves-like structure.

Japanese Unexamined Patent Publication No. 48-96289 discloses a method in which a gate metal is deposited by vapor deposition toward the concave portion using this eave as a shadow mask, and a gate electrode is formed in a self-aligned manner.

In addition, as another method of obtaining a gate electrode in a self-aligned manner, G
As an example, metal tin is provided as a first metal film on an aAs substrate, and nickel is used as a second metal film to form a two-layer film, and then a second metal film is formed using a photoresist using a commonly used method.
An opening is provided in the metal film, the first metal film is etched from the opening, and an opening larger than the opening in the first metal film is provided by undercutting.

That is, the structure is such that the second film protrudes like a canopy on the first metal film and a recess is provided.

A method of forming a gate electrode in a self-aligned manner by vapor depositing a gate metal toward this recess was disclosed in Japanese Patent Application Laid-Open No. 47-251.
4.

What these conventional examples all have in common is that the method of forming the gate electrode is that an eave-like protrusion is provided on the GaAs substrate and the gate electrode is self-aligned into the recess formed by the eave. The point is that it is provided.

On the other hand, although the purpose is different, molybdenum (MO) is used for the gate electrode and chromium (C) is used as the metal mask for Mo.
r) to form an ion-implanted layer in a self-aligned manner, then remove this Cr metal, and heat the ion-implanted layer to 800°C.
JP-A-49-46874 discloses a method of forming source and drain electrodes separately and non-aligned after activation by annealing for 10 minutes.

The biggest problem with this conventional method is firstly related to the method of forming the gate electrode.The unnecessary metal film deposited on the photoresist film in areas other than the gate area is removed together with the photoresist film. There is a limit to the thickness of the metal film that can be formed, and the resistance of the gate electrode becomes excessive.

In order to reduce the wiring resistance of this gate electrode, there is no choice but to thicken the film or increase the gate length, but increasing the gate length increases the gate capacitance (C) and has microwave characteristics. Not good.

Furthermore, the method of forming a recess and disposing the gate electrode within the recess has the disadvantage that if the thickness of the gate electrode is increased, the distance between the source and drain will inevitably increase.
In the case of a small opening, the gate metal is deposited on the side of the eaves, so the gate metal is deposited and the opening is sandwiched, and the cross-sectional shape of the deposited gate electrode is trapezoidal. Furthermore, it becomes triangular.

This results in a completely unfavorable structure from the perspective of wiring resistance, and in severe cases, it also has the fundamental drawback that the openings may be blocked first without achieving the necessary film thickness. There is.

Furthermore, in the method of forming a gate electrode by providing a recess in the active layer of a GaAs substrate, it is extremely difficult to control the thickness of the active layer.

Normally, the thickness of the active layer must be controlled very strictly, and this is done by wet etching or electrolytic etching, but in either method, it is difficult to control the etching solution temperature, its concentration, and the wettability of the etching solution to the object to be etched. It is significantly affected by the state of

For this reason, as the opening becomes minute and the recess becomes deeper,
The drawback is that it is extremely difficult to control.

Another problem with recesses with eaves is that cleaning is difficult because the eaves over the recesses cause poor circulation of cleaning fluid.

This method of forming the gate electrode within the recess has major drawbacks in terms of control and cleaning of the active layer.

Next, we will discuss a method of forming an ion implantation layer in a self-aligned manner using a gate electrode using a Si semiconductor.
To remove the etching, the substrate is exposed by ion bombardment etching, and after ion implantation, the Mo is laterally etched away from the ion implantation region to form a gate electrode.

This method has the disadvantage that during ion etching, ion bombardment is also applied to the substrate surface (active layer).

Furthermore, when applying the above method to GaAs and etching Mo in the lateral direction, there is currently a problem in that there is no etching solution that can precisely and efficiently etch only Mo without dissolving GaAs.

In addition, there is a photolithography process in the production of Schottky barrier gate field effect transistors, and in the photolithography process,
Pattern alignment is performed to form a photoresist mask in the source, drain, and gate regions, but the most advanced method, currently in the experimental stage, is electron beam exposure. The distance between the drains is about 2 μm.

However, the equipment used in this method is extremely expensive and there are problems with mass production.

In the commonly used exposure method, the gate length is 1 μm.
The limit is about 3 μm between m1 source and drain.

As described above, the pattern alignment process has become an important issue in the manufacture of 5BGFETs.

The object of the present invention is to easily create a 5BGFET that eliminates the above-mentioned drawbacks, that is, the gate length and the distance between the source and drain are extremely small, and the Schottky junction is small, so that the wiring resistance of the gate electrode is reduced without increasing the gate capacitance. It is an object of the present invention to provide a method for manufacturing a gallium arsenide Schottky barrier gate type field effect transistor which can be obtained in the following manner and does not require any pattern alignment process.

The present invention provides a method for manufacturing a Schottky barrier gate field effect transistor, in which a first metal film made of aluminum (AI) forming a Schottky contact is deposited on the surface of a gallium arsenide semiconductor, and a photographic film is photographed on the first metal film. Tungsten (5), molybdenum (Mo), titanium (Ti), which is not corroded by the etchant of the first metal film using etching technology,
Chromium (Cr), hafnium (Hf), platinum (Pt)
Forming a gate electrode pattern made of a second metal film made of one or more of the following,
Using the second metal film as a mask, the first part of the part not covered by the second metal film and the peripheral part under the second metal film is
, the first metal film having a smaller shape than that formed by the second metal film is left under the second metal film, and the gallium arsenide semiconductor surface is exposed approximately perpendicularly to the surface of the gallium arsenide semiconductor. A gallium arsenide Schottky barrier gate type characterized in that a metal film forming the source and drain electrodes is deposited thinner than the first metal film to form a source, gate, and drain electrode structure separated from each other. A method for manufacturing a field effect transistor is obtained.

An example of the implementation of the manufacturing method according to the present invention will be described below with reference to FIGS. 2 and 3.

FIG. 2 is a diagram for explaining the first embodiment of the manufacturing method according to the present invention, and schematically shows a cross section of the element in each step.

Figure a shows n with a carrier concentration of 5 x 1016 crrL-3 epitaxially grown on a semi-insulating gallium arsenide substrate 1.
lXl as a first metal film on the surface of the gallium arsenide layer 2.
High purity aluminum (
AI) 5 was deposited on 3000 people at a rate of about 1oooλ per minute by electron beam evaporation or resistance heating.

Next, a commonly used photoresist 6 is used to mask the other surface by photolithography, leaving a 15 μm long region corresponding to the gate electrode, and a hafnium (Hf) film is formed as a second metal film. Platinum (Pt) or titanium (
Ti) or chromium (Cr) or tungsten (
W) or molybdenum (Mo) with a thickness of 1000 Å or more, of which platinum (Pt)
If a metal other than A is used, platinum or gold (A
A second metal film having a length of 1.5 μm is obtained on the aluminum film 5 as shown in the figure.

Next, the aluminum serving as the first metal film 5 in the portion not covered by the second metal film and the peripheral portion under the second metal film is chemically etched with phosphoric acid heated to 60° C. to form a second metal film. The first metal film under the film is removed leaving a length of 0.5 μm.

At this time, the side etching of the AI is such that the gate electrode has an umbrella shape, so the actual gate length in Schottky contact cannot be confirmed just by looking at the surface with a microscope.

Therefore, the relationship between the etching time and the gate length was investigated regarding the capacitance (C) between the gate electrode and the source electrode, and the gate electrode was formed using this as a reference.

-To give an example, 3000 people will use AI, which is the first metal film,
As a second metal film, 600 layers of Ti and 1500 layers of Pi were placed on the Ti film, and 2000 layers of Au were placed on the Pi.
In the case of human adhesion, the A1 of the first metal film is 0.8 μm to 0.
．． Etching time of 30 seconds is required to form a thickness of 5 um, and at this time the gate capacitance is 1. OPF became 0.65PF.

Furthermore, to reduce the gate length from 0.5μm to 0.3μm, 1
Capacity can be obtained in 8 seconds from 0.65PF to 0.4
It was PF.

The cross-sectional shape at this time was observed using a SEM, and it was found that the AI was etched evenly on the left and right sides, and an extremely good umbrella-shaped gate electrode was obtained.

At this time, the gate wiring resistance is 45μm from 8μm.
m, it was 29Ω/mouth, which was found to be significantly reduced compared to the conventional method.

Next, 1,200 layers of gold-germanium alloy (Au-Ge) and 3,000 layers of platinum (PI) were deposited as source and drain electrode metals at a height of 5xlO" Torr or more in the direction almost perpendicular to the surface. C is obtained.

That is, there is an aluminum gate 51 with a gate length of 0.5 μm made of a first metal film on which a Schottky barrier is formed in the epitaxial layer 2, and a second metal film 7 and a metal film 8 are formed on the surface of the aluminum gate 51 with a gate length of 0.5 μm. An umbrella-shaped gate electrode protruding by .5 μm is obtained, and the source and drain electrodes are separated by this.

Next, this is heated to 380℃ to 500℃ in a hydrogen gas atmosphere.
Ohmic source electrode 3 and drain electrode 4 are obtained by heat treatment for several minutes at
A prototype of T is manufactured.

Next, a second embodiment of the present invention will be described with reference to FIG.

Figures a and b are exactly the same as the first embodiment, so the explanation will be omitted.

In Figure C, a gold electrode 80 is formed to a thickness of about 2 μm by plating on a second metal film 8 of platinum and gold formed by a vapor-deposited film. Membrane 5 is chemically etched with phosphoric acid to give a gate length of 0.5 μm.
form.

Furthermore, source and drain electrode metals were deposited almost perpendicularly to the substrate surface, and
After a few minutes of heat treatment at a temperature between 0.degree.

This method is applied to significantly reduce gate resistance or to strengthen the gate electrode.

In the examples, when hafnium or tungsten is used for the second metal film, the heat treatment to obtain an ohmic electrode can be performed at 500°C; when other metals are used, for example, platinum, titanium, chromium, molybdenum A suitable temperature is 400°C.

As described above, the first feature of the manufacturing method obtained according to the present invention is that an umbrella-shaped gate electrode can be obtained with a Schottky contact that is finer than the mask size and with reduced gate wiring resistance without increasing gate capacitance.

For example, using a mask dimension of 1.5 μm, an umbrella-shaped structure with a gate length of Schottky contact surface of 0.5 μm is obtained, and when the mask dimension is 0.5 μm, an umbrella structure with a gate length of Schottky contact surface of 0.3 μm is obtained. A gate electrode with a shaped structure is obtained.

In particular, a gate length of 0.5 μm can be obtained with good reproducibility and mass production without any problems.

Moreover, the gate electrode can have a thickness necessary and sufficient to obtain good characteristics as a field effect transistor.

For example, on top of the Schottky metal film of 3,000 Al, with an umbrella-like eaves protruding, 600 Ti and P
An umbrella-shaped gate electrode on which t is 1,500 and Au is 2,000 is formed, and AuGe--Ni metal is formed thereon.

The film thickness and source-drain distance can be formed without any particular restrictions.

Furthermore, the second feature is that a pattern alignment step in forming the source and drain electrodes is completely unnecessary, and the product yield is significantly improved.

The third feature is that 0.5 μm gate 5BGFE with a small source-drain distance can be easily fabricated using the conventional contact exposure method without using expensive and complicated electron beam exposure equipment.
Now you can get T.

In the above embodiments, a gallium arsenide semiconductor has been described, but the present invention can also be applied to a semiconductor such as silicon.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view schematically showing a Schottky barrier gate field effect transistor structure obtained by a conventional manufacturing method, and FIGS. 2 and 3 are diagrams for explaining the present invention. A schematic cross-sectional view of the element is shown. In each figure, 1 is semi-insulating gallium arsenide, 2 is an n-type gallium arsenide epitaxial layer, 3 and 4 are source and drain electrodes, respectively, 5 and 51 are Schottky barrier gate electrodes, and 5 is a first metal film 6 that is photosensitive. A resist film, 7 and 8 are second metal films, 80 is a plated gold film, and 9 and 10 are source and drain metal films.

Claims (1)

[Claims] 1 In a method for manufacturing a Schottky barrier gate field effect transistor, a first metal film made of aluminum (AI) forming a Schottky contact is provided on the surface of a gallium arsenide semiconductor, and a tungsten film that is not corroded by an etchant of the first metal film is provided. (5) A second metal film made of one or more of molybdenum (MO), titanium (Ti), chromium (Cr), hafnium (Hf), and platinum (Pt). forming a gate electrode mask pattern, and using the second metal film as a mask, remove the first metal film in a portion not covered by the second metal film and a peripheral portion under the second metal film; The first metal film having a smaller shape than the shape formed by the second metal film is
By leaving the metal film under the first metal film and forming the ohmic source and drain electrodes in a direction substantially perpendicular to the surface of the gallium arsenide semiconductor, the first metal film is also deposited. A method for manufacturing a gallium arsenide Schottky barrier gate field effect transistor, comprising forming source, gate and drain electrode structures separated from each other.