JPS6310905B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an MES FET.

The conventional manufacturing method of MES FET will be explained with reference to FIG. First, as shown in FIG. 1A, an n-type conductive layer 12 is formed on a semi-insulating substrate 11 by an epitaxial method or an ion implantation method. next,
After forming a resist mask by photolithography, high concentration ions are implanted into the semiconductor substrate (consisting of a semi-insulating substrate 11 and an n-type conductive layer 12), and by further annealing, the structure shown in FIG. As shown, source/drain regions 13 and 14 are formed on a semiconductor substrate. Next, by forming a resist pattern by photolithography, depositing an ohmic metal, and lifting off unnecessary parts, source/drain electrodes 15, 16 are formed on the source/drain regions 13, 14 as shown in FIG. 1B. Finally, a resist pattern is formed by photolithography, gate metal is deposited, and unnecessary parts are lifted off to form a gate electrode 17 at a predetermined position on the semiconductor substrate as shown in FIG. 1B.

By the way, in MES FET, the smaller the source-gate or gate-drain distance,
Furthermore, the smaller the gate length, the greater the high frequency characteristics. However, in the conventional manufacturing method using photolithography and mask alignment methods as described above, the gap between the source and gate or between the gate and gate depends on the accuracy of mask alignment.
There is a limit to reducing the distance between drains,
There was a limit to how high frequency characteristics could be improved. In addition, the conventional method described above requires mask alignment twice, which requires precision, and in particular, the gate electrode 17 may be damaged due to mask misalignment, etc.
4, the gate withstand voltage deteriorates, resulting in poor yield.

The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can manufacture MES FETs with improved high frequency characteristics with a high yield.

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 2A, 21 is a semi-insulating GaAs substrate, and first, an n-type conductive layer 22 is formed on the surface of the substrate 21 by epitaxial growth. Next, an insulating film (for example, a silicon oxide film) 23 is formed on the n-type conductive layer 22 by CVD, and then a metal (for example, platinum) pattern 24 is formed on the insulating film by photolithography, metal vapor deposition, or lift-off. 23.

Next, plasma etching is performed on the insulating film 23 using the metal pattern 24 as a mask to form source/drain windows (first and second windows) as shown in FIG. 2B.
25 and 26 are formed on the insulating film 23. At this time, an overhang portion (eaves) of the metal pattern 24 is formed by slightly overetching.

Next, high-concentration ion implantation of n-type conductive impurities (for example, Si ⁺ ) is performed into the semiconductor substrate (consisting of the semi-insulating GaAs substrate 21 and the n-type conductive layer 22 ) using the metal pattern 24 as a mask.
By performing annealing at about 900 DEG C., source/drain regions (first and second conductive regions) 27 and 28 are formed in the semiconductor substrate as shown in FIG. 2C.

Next, the entire surface of the semiconductor substrate including the metal pattern 24 is coated with a positive photoresist 29 as shown in FIG. 2D. At this time, since the width of the metal pattern 24 is approximately 2 μm at most, the thickness of the resist 29 on the metal pattern 24 can be made approximately half or less than that of the resist 29 on the semiconductor. Next, the entire surface of the resist 29 is exposed.
At this time, since the light is reflected by the metal (metal pattern 24), the exposure efficiency of the resist 29 on the metal pattern 24 can be more than doubled compared to other methods. Therefore, when the entire surface is exposed, only the resist 29 on the metal pattern 24 (particularly indicated by the shaded area 30) can be sufficiently exposed due to the thin thickness and high exposure efficiency. Therefore, when development is performed subsequently, the resist 29 (shaded area 30) on the metal pattern 24 can be completely removed, although not shown, and the metal pattern 24 can be exposed.

Thereafter, by etching and removing the metal pattern 24 and the insulating film 23 using the remaining resist 29 as a mask, a gate window (third window) 31 is formed as shown in FIG. expose the surface.

Next, gate metal is vapor-deposited on the gate window 31 and the resist 29, and unnecessary portions of the gate metal are lifted off using the resist 29, so that the gate electrode is aligned with the source/drain regions 27 and 28. 32 is formed on a semiconductor substrate as shown in FIG. 2F.

Finally, photolithography, vapor deposition of ohmic metal, and lift-off of ohmic metal are performed, and the second
As shown in Figure F, source/drain electrodes 33, 3
4 are formed on the source/drain regions 27 and 28.

As explained above, in the example, the directionality of ion implantation and the resist on the fine convex parts can be made thinner than the concave parts as shown in FIG. 2D, and the resist on the metal has high exposure efficiency. The source/drain regions 27 and 28 and the gate electrode 32 can be formed in a self-aligned manner by using the above method. This eliminates the need for mask alignment that requires precision, making the process reliable and easy, and improving yield.

Furthermore, since the source-to-gate spacing and the gate-to-drain spacing are determined by the amount of overetching of the insulating film 23 in the step B of FIG. 2, by controlling the amount of etching, it is possible to reduce the spacing to the submicron region. Therefore, series resistance is reduced and high frequency characteristics can be improved.

In addition, in the step C in Figure 2, since a metal with high masking performance is used as the ion implantation mask, there is no need to make the mask particularly thick (several thousand Å).
In addition, since this metal is separated from the semiconductor substrate by a heat-resistant insulating film, there is no particular restriction on the annealing temperature after ion implantation. Note that this annealing can also be omitted.

As described in detail in the embodiments above, in the method of manufacturing a semiconductor device of the present invention, the directionality of ion implantation, the resist on the fine convex parts can be made thinner than the concave parts, and the resist on the metal can be exposed to light. Taking advantage of the high efficiency, we have made it possible to form the first and second conductive regions and electrodes in a self-aligned manner. 1. The spacing between the second conductive regions can be reduced to the submicron region, resulting in an MES with improved high frequency characteristics.
FETs can be manufactured with high yield. Also,
According to the method of the present invention, in the step of exposing the metal after applying a resist in order to remove the eaves-forming metal and the insulating film of the gate portion, the resist on the fine convex portions as described above is thinner than the concave portions. Taking advantage of the fact that the resist on the metal has high exposure efficiency, the resist was removed from the metal due to the difference in exposure conditions between full-surface exposure and development. The process of removing metal and insulating film becomes easier. Furthermore, according to this method, the resist is removed only from above the metal of the gate part, and the resist is removed only from the first,
Since the second conductive region is covered with resist, it is possible to prevent gate electrode metal from being deposited on the first and second conductive regions.

[Brief explanation of the drawing]

FIG. 1 is a sectional view for explaining a conventional MES FET manufacturing method, and FIG. 2 is a sectional view for explaining an embodiment of the semiconductor device manufacturing method of the present invention. 21... Semi-insulating GaAs substrate, 22... N-type conductive layer, 23... Insulating film, 24... Metal pattern, 25,
26... Source/drain window, 27, 28... Source/drain region, 29... Positive photoresist,
31...Gate window, 32...Gate electrode, 33,3
4...Source/drain electrode.

Claims (1)

[Claims] 1. A step of forming an insulating film having a first window and a second window and a metal having an eave located on the insulating film on a semiconductor substrate, performing ion implantation into the semiconductor substrate using the metal as a mask, and further annealing. forming first and second conductive regions in the semiconductor substrate within the first window and the second window, respectively, with or without performing , and applying a resist to the entire surface of the semiconductor substrate; a step of removing only the resist on the metal by performing whole-surface exposure and development; a step of removing the metal and the insulating film to form a third window and exposing the surface of the semiconductor substrate; 1. A method for manufacturing a semiconductor device, comprising the steps of depositing metal on a resist, and then lifting off unnecessary portions of the metal using the resist.