JPS6284566A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase withstanding voltage between a source and a gate and withstanding voltage between the gate and a drain while reducing capacitance between the source and the gate by manufacturing a Schottky junction type field-effect transistor with a source region and a drain region in high concentration being separated only by predetermined distances horizontally from a gate electrode. CONSTITUTION:A gate electrode is formed at the central section of a substrate 21 in such a manner that resist patterns are shaped in regions on insulating films 28 on an active layer 22 shorter than a space in the horizontal direction between each region of respective region 24, 25 in high concentration and except a section of length l3 between two insulating films 28 and a surface protective film 23, the surface protective film 23 of the section of said length l3 is removed through etching from the upper section of the substrate 21 and an opening for forming the gate electrode 30 is shaped. The active layer 22 and the gate electrode 30 as a Schottky junction are evaporated to said opening while the resist patterns are removed by using a solvent, etc. through a lift-off, thus forming an electrode pattern for the gate electrode 30.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor and a method for manufacturing the same.

[Prior Art] FIG. 2 is a cross-sectional view of a self-aligned field effect transistor showing a conventional example.

In FIG. 2, in order to reduce the source resistance of the field effect transistor, a source region 14 and a drain region 15 are
A self-aligned field effect transistor is shown that is fabricated in a self-aligned manner to the gate region.

This self-aligned field effect transistor is manufactured as follows. First, after performing ion implantation to form an active layer in the main surface layer of the semi-insulating GaAs semiconductor substrate 11, for example, the gate electrode 13 is formed near the center on the main surface. Next, using this gate electrode 13 as a mask, ions are implanted toward the semiconductor substrate itt from the main surface other than the main surface of the semiconductor substrate By forming the source region 14 and the drain region 15, the source region 14 and the drain region 15 are connected to the gate region 1.
Self-align to 2. Further, a source electrode 16 and a drain electrode 17 are deposited on the main surface of the semiconductor substrate 11 in the source region 14 and drain region 15, respectively, and a self-aligned field effect transistor can be manufactured by the above method.

[Problems to be Solved by the Invention] However, conventional field effect transistors of this type have a highly doped source region 1 to reduce source resistance.
4 and the drain region 15 are close to each other, the breakdown voltage between the source and gate and the breakdown voltage between the gate and drain are low, making it impossible to apply a high operating voltage, or the voltage between the source and gate increases and becomes negligible in the high frequency region. I was cultivating flaws such as disappearing.

[Object of the Invention] The object of the present invention is to solve the above-mentioned problems, and to provide a field effect transistor that can improve the source-gate breakdown voltage and the gate-drain breakdown voltage, and reduce the source-gate capacitance. The purpose is to provide the manufacturing method.

[Structure of the Invention] The present invention provides a field effect transistor having an active layer formed on the main surface of a semiconductor substrate, and in which a source electrode, a gate electrode, and a drain electrode are juxtaposed on the same main surface of the active layer. With respect to the active layer gate region under the gate electrode that crosses the main surface of the active layer, a source region and a drain region containing a high concentration of impurities having the same conductivity type as the active layer are connected to the active layer gate region under the gate electrode. The source region, the drain region, and the active layer region are formed in a self-aligned manner with respect to the active layer gate region. It is characterized by being formed.

[Example] Figure 1 (a), (b), (c), (d)
, (e), (f), (g), (h) and (i) are cross-sectional views of a field effect transistor showing the manufacturing process of a self-aligned field effect transistor according to an embodiment of the present invention. Hereinafter, with reference to FIGS. 1(a) to (1),
A manufacturing process of a self-aligned field effect transistor, which is an embodiment of the present invention, will be described.

In FIG. 1(a), first, a semiconductor substrate 21, for example, a semi-insulating GaAs substrate 21, has its main surface layer coated with, for example, GaAs.
In the case of an s-substrate, an n-type active layer 22 is formed by implanting impurities such as Si or S by ion implantation.

Next, an insulating surface protection film 23 made of SiNx or the like is deposited on the main surface of the semiconductor substrate 21 by, for example, the p-cVD method. This surface protective film 23 also serves as a protective film during heat treatment in the manufacturing process.

Next, in FIG. 1(b), a highly doped source region 24 is formed.
and a region other than on the surface protective film 23 where the drain region 25 is formed, a region near the center where the gate electrode is provided, and a surface protective film 23 in two outer regions that are not on the main surface of the semiconductor substrate 21 and are not ion-implanted. On top, resist 2
6 to form an ion implantation mask pattern.

After that, resist 2, which is a mask pattern for ion implantation,
Ions having a high impurity concentration and having the same conductivity type as the active layer 22 are implanted from above the surface protection film 23 formed in a part of the region 6 toward the semiconductor substrate 21 . As a result, the main surface layer of the semiconductor substrate 21 in a region other than the region where the ion implantation mask pattern is formed has, for example, a source region 24 and a drain region that are thicker than the active layer 22 and contain a high concentration of impurities. A region 25 is formed. The thickness of the source region 24 and drain region 25 formed in the main surface layer of the semiconductor substrate 21 is not limited to being thicker than the active layer 22, and can be determined as desired.

Furthermore, in FIG. 1C, a thin film 27 such as AQ is deposited over the entire surface of the semiconductor substrate 21 by sputtering, vapor deposition, or the like. This thin film 27 is not etched by the plasma etching method using gas, but can be easily etched by other suitable etching methods, and the surface protective film 27 is etched by the etching method.
3 and the resist 26 may be thin films as long as they are not etched.

After this, as shown in FIG. 1(d), the resist 26 formed in the area near the center of the semiconductor substrate 21 and in both outer areas that are not on the main surface of the semiconductor substrate 21 and where ions are not implanted is etched using a plasma etching method using O gas. Etching is performed in the horizontal direction by a predetermined length Q from each end of the highly doped source region 24 and drain region 25 . That is, the resist 2 formed in the area near the center of the semiconductor substrate 21
6 is etched by a predetermined horizontal length I21 from the ends of the highly doped source region 24 and drain region 25 near the center of the semiconductor substrate 21, and is not etched onto the main surface of the semiconductor substrate 21 and is not ion-implanted. The resist 26 formed in both outer regions is etched by a predetermined horizontal length Q from the end of the highly doped source region 24 and drain region 25 far from the outer end of the semiconductor substrate 21 . Here, since the thin film 27 is deposited on the upper surface of each resist 26, the length of the resist 26 in the vertical direction does not change. Further, the predetermined length Q is determined by ±0°O1 μm using a plasma etching method using 0° gas.
It is possible to control with a degree of accuracy.

Hereinafter, the resist 26 etched by a length Q in the horizontal direction as described above will be referred to as 26a. Renost 2 above
After etching in step 6, thin film 2 is formed using an appropriate etching method.
Perform the removal of 7. FIG. 1(e) is a cross-sectional view of the field effect transistor after the thin film 27 has been removed.

Next, in FIG. 1(f), an insulating film 28 is deposited on the surface of the surface protective film 23 on the semiconductor substrate 21 formed as described above by sputtering or vapor deposition. Therefore, the surface protection film 23 and the resist 26 other than the area where the resist 26a whose length in the horizontal direction is shortened are formed.
An insulating film 28 is deposited on the region a. This insulating film 28
needs to be a material that has etching selectivity compared to the surface protective film 23, that is, it has such etching selectivity that the surface protective film 23 can be etched in the process described later, but the insulating film 28 cannot be etched. is necessary. For example, the surface protective film 2
As the etching method for 3, when using the method of etching using SiNx by I)-CVD method,
On the other hand, as an etching method for the insulating film 28,
A method of etching using a sputtering method using 5 inches is suitable.

In FIG. 1(g), after the insulating film 28 is deposited, the resist 26a is removed using a solvent or the like.

Next, in order to activate the active layer 2'2, the high concentration source region 24, and the drain region 25, the steps shown in FIG.
) is heat-treated on which the insulating film 28 is deposited.

Furthermore, regions other than the predetermined length Q for forming source and drain electrodes shorter than the horizontal length of each region 24.25 from the edge of each high concentration region 24.25 near the outside of the substrate 21 The surface protective film 23 and the insulating film 2
After forming a resist pattern (not shown) on the substrate 21, etching is performed from above the substrate 21 in FIG. 1(h) to form two openings 40a for forming a source electrode and a drain electrode.

40b. At this time, the insulating film 28 remains on the surface protection film 23 on both sides of the edge side of the opening having the horizontal length σ.

Next, a source electrode 29 and a drain electrode 3I that are in ohmic contact with the highly concentrated source region 24 and drain region 25 are deposited in the openings 40a and 40b, and the above-mentioned resist pattern is removed by lift-off using a solvent or the like. , the source electrode 29 and the drain electrode 31
form an electrode pattern.

After this, in order to provide a gate electrode in the center of the substrate 21, two insulating films 28 are formed on the active layer 22, which is shorter than the horizontal distance between the high concentration regions 24 and 25.
After forming a resist pattern (not shown) on the insulating film 28 and the surface protective film 23 other than the portion of length Q3 between the etching regions, etching is performed from above the substrate 21 to the above-mentioned length e3.
The surface protection @23 is removed to form an opening for forming the gate electrode 30. A gate electrode 30 which serves as a junction between the active layer 22 and a Schottky is deposited in the opening, and the resist pattern described above is removed using a solvent or the like by lift-off to form an electrode pattern of the gate electrode 30.

By going through the above field effect transistor manufacturing process, it is possible to manufacture a scigot key junction field effect transistor having a highly doped source region 24 and a drain region 25 that are horizontally separated from the gate electrode 30 by a predetermined distance I21. This makes it possible to improve the breakdown voltage between the source and gate and between the gate and drain, as well as reduce the capacitance between the source and gate, compared to conventional field effect transistors. The above predetermined distance M (1, is the horizontal length of the resist 26 which is a mask for high concentration ion implantation and the side etching amount q of the above resist 26
By controlling , a gate length of 1 μm or less can be easily obtained. where the above given distance #! Q1
A suitable value is 0.2 to 03 [μm].

In the above embodiment, since the gate electrode 30 is formed after the active layer 22 and the high concentration source region 24 and drain region 25 are heat-treated, it is not necessary to use a heat-resistant material for the gate electrode 30. The 30 types are no longer limited.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to manufacture a self-aligned field effect transistor with a short gate length. - There is an advantage that the withstand voltage between the drains can be improved and the capacitance between the source and gate can be reduced.

[Brief explanation of drawings]

Figure 1(a), Figure 1(b), Figure 1(C), Figure 1(
d), FIG. 1(e), FIG. 1(f), FIG. 1(g), FIG. 1(h), and FIG. 1(i) are self-aligned types that are one embodiment of the present invention. FIG. 2 is a cross-sectional view of a field-effect transistor showing the manufacturing process of the field-effect transistor, and FIG. 2 is a cross-sectional view of a self-aligned field-effect transistor showing a conventional example. 2... Semiconductor substrate, 12... Active layer, 13... Gate electrode, 14... High concentration drain region, 15... High concentration source region, 16... Source electrode, 17... - Drain electrode, 21... Semiconductor substrate, 22... Active layer, 23... Surface protection film, 24... High concentration source region, 25... High concentration drain region, 26... Resist, 26a ...Etched resist, 27...Thin film, 28...Insulating film, 29...Source electrode, 30...Gate electrode, 31...Drain electrode, 40a...For source electrode opening, 40b...opening for the drain electrode.

Claims (2)

[Claims] (1) having an active layer formed on the main surface of the semiconductor substrate;
In a field effect transistor in which a source electrode, a gate electrode, and a drain electrode are arranged side by side on the same main surface of the active layer, the active layer gate region under the gate electrode that crosses the active layer main surface is the same as the active layer. A source region and a drain region containing a high concentration of impurities having a conductivity type of are formed adjacent to an active layer region that allows the active layer gate region to extend along the main surface of the source region side and the drain region side. A field effect transistor characterized in that the source region, the drain region, and the active layer region are formed in self-alignment with the active layer gate region. (2) When forming a field effect transistor by arranging a source electrode, a gate electrode, and a drain electrode on the same surface of the active layer formed by ion implantation to form an active layer on the main surface of a semiconductor substrate. , a step of forming a first insulating film on the main surface of the active layer on the semiconductor substrate to protect the active layer, and a mask for forming a source region and a drain region containing a high concentration of impurities. A step of forming a resist layer which is an ion implantation pattern to be used, and a step of forming a source region and a drain region by ion-implanting impurities having the same conductivity type as the active layer at a high concentration using the resist layer as a mask. , a step of depositing a metal film or a second insulating film on the semiconductor substrate including the resist layer, a side etching step of etching the side surface of the resist layer, and removing the metal film or the second insulating film. a step of depositing a third insulating film on the semiconductor substrate including the side-etched resist layer;
a step of removing the side-etched resist layer; a step of activating the gate region in the active layer region to which ions have not been implanted; and a source region and a drain region adjacent to the gate region; and a step of activating the source region. and a step of removing a portion of the first and third insulating films formed on the drain region to open the source region and the drain region to form a source electrode and a drain electrode; A method for manufacturing a field effect transistor, comprising the step of: removing a part of the first insulating film to open a gate region and form a gate electrode.