JPH02181440A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a gate electrode deviated to the source region side simply, and to increase drain breakdown strength by implanting an impurity in high concentration while using an inorganic material film formed on a sidewall on the drain region side of the gate electrode and the gate electrode as masks. CONSTITUTION:A gate electrode 42 composed of a high melting-point metal is shaped onto a semiconductor substrate 1 to which an operating layer 2 is formed previously. A sidewall inorganic material film 21 is shaped onto a sidewall on the drain region side of the gate electrode 42. An impurity is implanted in high concentration while employing the gate electrode 42 and the sidewall inorganic material film 21 as masks, thus forming a source region 3 and a drain region 4 to the semiconductor substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor, and in particular to a method for manufacturing a field effect transistor (Schottky gate type field effect transistor).
MESFET).

[Conventional technology]

In MESFETs, the distance between the n-layer on the drain side and the gate electrode is made wider than the distance between the n-layer on the source side and the gate electrode, thereby increasing the drain breakdown voltage while keeping the series resistance at a small value. (It is considered that the drain conductance is lowered by
For example, a device using a dummy gate with a multilayer structure is already known (Japanese Patent Laid-Open No. 194781/1981).

[Problem to be solved by the invention]

However, in the above-mentioned method, manufacturing of the asymmetric dummy gate structure is complicated, and there are problems to be solved such as poor reproducibility.

[Means to solve the problem]

The method for manufacturing a field effect transistor according to the present invention includes a first step of forming a gate electrode made of a refractory metal on a semiconductor substrate on which an active layer has been formed in advance, and a sidewall inorganic material on the sidewall of the gate electrode on the drain region side. A second step of forming a material film, and a third step of injecting impurities at a high concentration using the gate electrode and its sidewall inorganic material film as a mask to form source and drain regions in the semiconductor substrate. shall be.

Further, the manufacturing method according to the present invention includes a first step of forming a gate electrode made of a high melting point metal on a semiconductor substrate on which an active layer has been formed in advance, and a reactive ion etching method after depositing an inorganic material film. A second step is to leave an inorganic material film on the sidewalls of the gate electrode by etching, and a resist pattern is formed to cover the inorganic material film on the drain region side of the gate electrode, and the inorganic material film is etched using this resist pattern as a mask. The third step involves selectively removing the inorganic material film to leave an inorganic material film on the drain region side of the gate electrode, and implanting impurities at a high concentration using this inorganic material film and the gate electrode as a mask to form the source and drain regions on the semiconductor substrate. A fourth step of forming a region.

[Effect]

According to the present invention, an inorganic material film is not formed on the side wall of the gate electrode on the source region side, but is formed on the side wall of the gate electrode on the drain region side. Source/drain regions are formed by ion implantation.

Therefore, it is possible to realize a gate electrode shifted toward the source region.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the attached figures.

FIG. 1 is a sectional view showing the manufacturing process of the embodiment.

First, a semiconductor substrate 1 made of GaAs, for example, is prepared, a photoresist film 11 is formed by a spin code method, etc., and patterned by photolithography. and,
An n-type impurity is ion-implanted through this patterned photoresist film 11 to form an n-type active layer 2 (as shown in FIG. 1(a)).

Next, the photoresist film 11 is removed by immersion in acetone or ashing, and a gate electrode material film 41 made of a high melting point metal is applied using a vacuum evaporation method or a sputtering method, and another resist film is applied thereon using a spin code method or the like. Apply 12. This resist film 12 is then patterned to leave the resist film 12 on the gate region (as shown in FIG. 1(b)). Thereafter, using the resist film 12 as a mask, the gate electrode material film 41 is selectively removed by reactive ion etching (RIE) or the like to form a gate electrode 42 made of a high melting point metal.

Next, using plasma CVD method or sputtering method,
An inorganic material x film 21 made of SIO, SIN, etc. is deposited (as shown in FIG. 1(c)), and the inorganic material film 21 is etched by RYE or the like. Then, Figure 1 (
As shown in d), the inorganic material film 21 remains on the sidewalls of the gate electrode 42.

Next, a resist film 13 is deposited by a spin code method and patterned by photolithography to cover the inorganic material film 21 on the drain region side of the gate electrode 42.

When the inorganic material film 21 is etched using this resist film 13 as a mask, the inorganic material film 21 remains only on the drain region side of the gate electrode 42 (the first
Figure (e) shown). Thereafter, the resist film 13 is removed by immersion in acetone or ashing, and then a resist film 14 is deposited by a spin code method or the like, and a window is opened in the FET formation region by photolithography, and the resist film 14 and the inorganic material film 21 are removed. Using the gate electrode 42 as a mask, n-type impurity ions are implanted. This ion implantation is performed at a high concentration, thereby forming a source region 3 in contact with the gate electrode 42 and a drain region 4 remote from the gate electrode (as shown in FIG. 1(f)).

Next, the resist film 14 is removed and annealing is performed at about 800° C. in an As Ha atmosphere to form the ion-implanted layer 2,
Activate 3.4. Thereafter, ohmic electrodes 45 and 46 are formed by the lift-off method, and the MESFET is completed by a self-alignment process (Fig. 1(g)).
(Illustrated).

In the MESFET of the above embodiment, the gate electrode 42
The source region 3 is in contact with the source region 3. In order to eliminate this, the inorganic material film 21 may be removed by etching after the step shown in FIG. 1(f), and the gate electrode 42 may be etched in the same direction.

〔Effect of the invention〕

As explained above in detail, in the present invention, an inorganic material film does not exist on the side wall of the gate electrode on the source region side, but exists on the side wall of the drain region side. Source/drain regions are formed by ion implantation using a mask. Therefore, it is possible to easily realize a MESFET having a gate electrode shifted toward the source region and having a high drain breakdown voltage.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an element according to manufacturing steps, showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Operating layer, 3... Source region, 4... Drain region, 11. 12. 13.
...Photoresist film, 21...Inorganic material film, 41.
. . . Gate electrode material film, 42 . . . Gate electrode, 45.
46...Ohmic electrode. Patent applicant: Sumitomo Electric Industries, Ltd. Patent attorney Yoshiki Hase: r-tan
(1/2) Chapter 10 (1)

Claims (1)

[Claims] 1. A first step of forming a gate electrode made of a high melting point metal on a semiconductor substrate on which an active layer has been formed in advance, and forming a sidewall inorganic material film on the sidewall of the gate electrode on the drain region side. and a third step of injecting impurities at a high concentration using the gate electrode and its sidewall inorganic material film as a mask to form source and drain regions in the semiconductor substrate. A method for manufacturing a field effect transistor. 2. A first step of forming a gate electrode made of a high melting point metal on a semiconductor substrate on which an active layer has been formed in advance, and etching after depositing an inorganic material film, and forming the inorganic material film on the sidewalls of the gate electrode. forming a resist pattern covering the inorganic material film on the drain region side of the gate electrode, and selectively removing the inorganic material film using this resist pattern as a mask to remove the inorganic material film on the drain region side of the gate electrode; a third step of leaving the inorganic material film on the drain region side of the semiconductor substrate; and implanting impurities at a high concentration using the inorganic material film remaining on the gate electrode and its sidewalls as a mask, and forming the source and drain regions on the semiconductor substrate. and a fourth step of forming a field effect transistor. 3. The method for manufacturing a field effect transistor according to claim 2, wherein the etching in the second step is reactive ion etching.