JPS6262071B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a high speed semiconductor device having a short gate length.

FIG. 1 is a process explanatory diagram of a conventional MESFET manufacturing method. First, as shown in FIG. 1A, an n-type conductive layer 12 is formed on a semi-insulating substrate 11 by ion implantation. .

Next, a resist mask is formed by photolithography, and then the semiconductor substrate (semi-insulating substrate 11 and n
By performing high concentration ion implantation into the type conductive layer 12) and further annealing, the structure shown in FIG.
Source and drain regions 13 and 14 shown in FIG. 1 are formed on this semiconductor substrate.

Next, a resist pattern is formed by photolithography, ohmic metal is deposited, and unnecessary parts are lifted off, as shown in FIG. 1B.
Source/drain electrodes 15, 16 are formed on the source/drain regions 13, 14, respectively, and finally, a resist pattern is similarly formed by photolithography, gate metal is evaporated, and unnecessary parts thereof are lifted off. As shown in B, gate electrode 1
7 is formed at a predetermined position on the semiconductor substrate.

By the way, in MESFET, the smaller the source-gate or gate-drain distance,
Furthermore, the smaller the gate length, the greater the high frequency characteristics. However, in the conventional manufacturing method using the photolithographic mask alignment method as described above, there is a limit to the reduction of the source-to-gate distance or the gate-to-drain distance due to limitations in mask alignment accuracy and resist pattern width.

Furthermore, in the above method, mask alignment that requires precision is required twice, and in particular, the gate electrode 17 may be removed from the source/drain region 1 due to mask misalignment or the like.
3 and 14, the gate withstand voltage deteriorates, resulting in poor yield.

Similarly, depending on the resist pattern width limit,
There is a limit to reducing the gate length, and
When the gate length is small, parasitic resistance due to the gate electrode increases, which has the disadvantage of limiting high frequency characteristics.

This invention was made in order to eliminate the above-mentioned conventional drawbacks, and has improved high frequency characteristics.
An object of the present invention is to provide a method for manufacturing a semiconductor device that can manufacture MESFETs with high yield.

Embodiments of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. First, in FIG. 2A, 21 is a semi-insulating GaAs substrate,
An n-type conductive layer 22 is formed on the surface of this semi-insulating GaAs substrate 21 by selective ion implantation and annealing.

Next, as shown in FIG. 2B, a resist pattern 23 having a window at the gate position on this n-type conductive layer 22 is formed by photolithography. Next, from the direction indicated by arrow A diagonally upward, titanium 2
Wear 4 about 0.1 to 0.33μ. There is no problem even if this titanium is replaced with an insulator such as silicon oxide.
At this time, the angle is such that a part of the titanium 24 comes into contact with the semi-insulating GaAs substrate 21.

Next, as shown in FIG. 2C, titanium 25 is further vapor-deposited from the other obliquely upward direction (the direction opposite to the direction of arrow A in FIG. 2B). Also at this time, some titanium 25 is attached to the semi-insulating GaAs substrate 21.
If this is done at an angle that makes contact with the resist pattern 23, a gate window surrounded by titanium 25 can be formed in the center of the resist pattern 23. Subsequently, platinum 26 as a gate electrode is deposited vertically from above.

Here, by performing lift-off using the resist pattern 23 and further removing the remaining titanium, a gate electrode 27 having an inverted convex cross-sectional structure as shown in FIG. 2D can be formed.

Finally, photolithography is performed to form source and drain electrodes 28 and 29 by lift-off of an ohmic metal such as Au--Ge, thereby manufacturing a MESFET having the structure shown in FIG. 2E.

Further, after forming the reverse convex gate electrode shown in FIG. When high concentration ion implantation is performed, the resist pattern is removed, and annealing is performed, source/drain regions 3 are formed in the semi-insulating GaAs substrate 21.
0,31 can be formed.

Thereafter, by lifting off the ohmic electrode, it is possible to manufacture a MESFET having highly doped source and drain regions, as shown in FIG. 2F.

As explained above, in the first embodiment, the second
As shown in Figure B and Figure 2C, titanium 24, 25
Resist pattern 2 is created using the directionality of vapor deposition.
By forming an even smaller gate window inside 3, an inverted convex gate electrode as shown in FIG. 2D can be obtained.

This allows the gate length to be adjusted to the resist pattern 23.
Since the gate electrode 27 can be controlled not only by the size of the window but also by the evaporation angle and thickness of the titanium 24 and 25, the gate electrode 27 having a very short gate length can be formed with high precision and high yield.

Further, since the gate electrode structure has an inverted convex shape, the gate electrode has a large cross-sectional area despite the short gate length, which has the advantage of reducing parasitic gate resistance due to the gate electrode 27.

Furthermore, since the gate electrode is made of a single metal, there is no risk of deterioration of the gate due to mutual diffusion of different metals, unlike gate electrodes made of multiple types of metals, which improves the reliability of the gate electrode. do.

In this way, the inverted convex gate electrode made of a single metal and its manufacturing method using oblique evaporation provide high reliability and excellent high frequency characteristics.
MESFETs can be manufactured with high yield.

In addition, in the case of an inverted convex gate electrode, the sides of the gate electrode have an overhang shape, so even if highly accurate ion implantation is performed using the gate electrode as a mask, the implanted region does not come into contact with the gate electrode. There is no risk of deterioration of gate breakdown voltage due to contact between the gate electrode and the highly doped source/drain regions.

Furthermore, the protrusion distance of the overhang is very small (1000 to 2000 Å), and the distance between the source and gate and between the gate and drain is determined by this distance, so the distance between the source and gate and between the gate and drain is determined. The resistance can be made very small.

In this way, by adding the ion implantation method, the high frequency characteristics of the FET can be further improved.

In the first embodiment, a method for manufacturing a semiconductor element having an inverted gate electrode 27 made of a single metal was explained, but as a second embodiment described below,
A method for forming source/drain electrodes in self-alignment will be explained with reference to FIG.

First, in the first embodiment, as shown in FIG. After that, as shown in FIG. 3A, a resist pattern 32 having a hole sized to include the source and drain regions is formed by photolithography.

Next, an ohmic metal 33 is deposited and lift-off is performed using a resist pattern 32 (FIG. 3B).

Finally, when the titanium 24 and 25 remaining on the semi-insulating GaAs substrate 21 are removed, the titanium 2
The ohmic metal 33 deposited on 4, 25 is also lifted off, and a MESFET having source/drain electrodes 28, 29 and gate electrode 34 can be manufactured.

In this way, the source/drain electrodes 28, 29
is formed in a predetermined position by self-alignment by a resist pattern 32 that does not require precision, and
At the same time, the gate electrode 34 and the source/drain electrode 2
Since the distance between 8 and 29 is determined by the thickness of titanium 24 and 25, the distance between gate electrode 34 and source/drain electrodes 28 and 29 can be made very small.

This allows for source-to-gate and gate-to-gate
Since the resistance between the drains can be reduced and the entire FET can be made small, MESFETs with excellent high frequency characteristics can be manufactured with high yield.

Here, in the second embodiment, the method of forming the source/drain electrodes 28 and 29 by self-alignment was explained, but the gate electrode 34 has a different type of metal (ohmic metal 33) adhered to its top surface. Therefore, there is a risk that the gate electrode 34 is altered due to mutual diffusion between the ohmic metal 33 and the gate electrode 34, and the gate electrode 34 is deteriorated.

In order to avoid this, a third embodiment will be explained next with reference to FIG. First, following the step shown in FIG. 2C of the first embodiment, titanium 35 is vapor-deposited from vertically above.

Next, when the steps shown in FIG. 3A and FIG. 3B shown in the second embodiment are performed, as shown in FIG. 4A,
The top surface of the platinum 26 serving as the gate metal and the ohmic metal 33 are separated by the titanium 35.

Finally, when all the titanium 24 and 25 remaining on the semi-insulating GaAs substrate 21 are removed, the ohmic metal 33 on the platinum 26 that will become the gate electrode is also lifted off by the titanium 35, as shown in FIG. 4B. Furthermore, it is possible to form a gate electrode 36 made of a single metal (platinum 26) without dissimilar metals on the gate electrode 36 (made of platinum 26).

In this way, in addition to the advantages of the second embodiment, the third embodiment has the gate electrode 3 made of a single metal.
6, which improves the reliability of the gate.

Here, after the process shown in FIG. 3A of the second and third embodiments, the resist pattern 32, the titanium 24,
25 and gate metal as a mask, semi-insulating
Impurity ions are implanted into the GaAs substrate 21, and after lift-off using a resist pattern 32, annealing is performed.Subsequently, as shown in FIG. 3A, a resist pattern 32 is formed again, and the same process is performed thereafter. , as shown in Figure 5, the source
Semi-insulating contact with drain electrodes 28, 29
Low resistance source/drain regions 37 and 38 can be formed in the GaAs substrate 21.

At this time, if the ion implantation energy is increased to form deep source/drain regions, the source/drain regions 37 and 38 will be closer to the gate electrode 36 due to the horizontal spreading effect of the implanted impurities. It can be brought closer.

Therefore, since a high concentration layer exists under the source and drain electrodes 37 and 38, each electrode is semi-insulated.
The contact resistance of the GaAs substrate 21 can be reduced, and similarly, the resistance between the source and drain can be reduced due to the high concentration layer existing up to the vicinity of the gate. In this way, by adding ion implantation,
Parasitic resistance can be reduced and high frequency characteristics can also be increased.

As detailed above, according to the method for manufacturing a semiconductor device of the present invention, the first metal or insulator is deposited diagonally in both directions on the first resist pattern having a window at the gate position on the semiconductor substrate. After that, a second metal for the gate electrode is deposited on the window at the gate position, and then the first metal or insulator is removed to form a single metal with an inverted convex cross-sectional structure. By forming a gate electrode with a resist pattern and performing ion implantation using this gate electrode and the second resist pattern as a mask, the source/drain regions are formed. Long gates can be formed.

Along with this, it is possible to manufacture MESFETs with short distances between the source and gate and between the gate and drain, and it is also possible to form the source and drain electrodes very close to the gate electrode by self-alignment, making it possible to manufacture MESFETs with improved high frequency characteristics. It can be manufactured with high yield.

[Brief explanation of the drawing]

Figure 1A and Figure 1B are process explanatory diagrams of the conventional MESFET manufacturing method, Figures 2A to 2F
3A to 3C are process explanatory diagrams of the first embodiment of the semiconductor device manufacturing method of the present invention, respectively, and FIGS. 3A to 3C are process explanatory diagrams of the second embodiment of the semiconductor device manufacturing method of the present invention, respectively. , Figures 4A and 4
FIG. 5 is a process explanatory diagram of a third embodiment of the semiconductor device manufacturing method of the present invention, and FIG. 5 is a process explanatory diagram of the fourth embodiment of the semiconductor device manufacturing method of the present invention. 21... Semi-insulating GaAs substrate, 22... N-type conductive layer, 23, 32... Resist pattern, 24, 2
5,35...Titanium, 26...Platinum, 27,34,3
6... Gate electrode, 28... Source electrode, 29... Drain electrode, 30, 37... Source region, 31, 38
...Drain region, 33...Ohmic metal.

Claims (1)

[Claims] 1. A first resist pattern having a hole is formed in a gate region above an operating region of a field effect transistor formed on a first surface of a semiconductor substrate, and the first resist pattern is deposited at the center of the hole. a first step of depositing the first metal or insulator obliquely in both directions at an angle that allows the first metal or insulator to be deposited on the semiconductor substrate around the hole without causing
After depositing a second metal as a gate electrode from the vertical direction on the semiconductor substrate, lifting off the first metal or insulator and the second metal using the first resist pattern, and then depositing the second metal on the semiconductor substrate. 1
A second process involves etching a metal or insulator to form a single metal gate electrode with an inverted convex cross-sectional structure;
A second resist pattern having a hole including a gate region is formed, and ions are implanted into the semiconductor substrate using the second resist pattern and the gate electrode as a mask to form source/drain regions in a self-aligned manner. A method for manufacturing a semiconductor device comprising the steps of 3. 2. A first resist pattern having a hole is formed in the gate region on the operating region of the field effect transistor formed on the first surface of the semiconductor substrate, and the first resist pattern is not deposited on the center of the hole but on the periphery of the hole. a first step of depositing the first metal or insulator obliquely in both directions from an angle that is such that it can be deposited on the semiconductor substrate;
A second step of depositing a second metal as a gate electrode from the vertical direction on the semiconductor substrate and then lifting off the first metal or insulator and the second metal using the first resist pattern. and,
A second resist pattern having holes is formed in the operating region of the field effect transistor including the source, gate, and drain regions, and a third metal having ohmic characteristics is deposited, and then the second resist pattern is removed. A method for manufacturing a semiconductor device comprising a third step of etching the first metal or insulator and lifting off the third metal to form source/drain electrodes in a self-aligned manner. 3. A first resist pattern having a hole is formed in the gate region on the operating region of the field effect transistor formed on the first surface of the semiconductor substrate, and the first resist pattern is not deposited on the center of the hole but on the periphery of the hole. a first step of depositing the first metal or insulator obliquely in both directions from an angle that is such that it can be deposited on the semiconductor substrate;
After a second metal is vapor-deposited as a gate electrode from the vertical direction on the semiconductor substrate, a fourth material made of the same material as the first metal or insulator is continuously deposited to form a first resist pattern. Yotsutte 1st
a second step of lifting off the metal or insulator, the second metal, and the fourth material, and forming a second resist pattern having holes in the operating region of the field effect transistor including the source, gate, and drain regions. The third one has ohmic properties.
After vapor deposition of the metal, the second resist pattern is removed and the third metal on it is removed at the same time, and the first metal or insulator and the fourth material are removed simultaneously and the third metal is removed on top of them. A method for manufacturing a semiconductor device comprising a third step of simultaneously removing the third metal remaining on the substrate and forming source/drain electrodes in a self-aligned manner using the third metal remaining on the substrate.