JPS5852881A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS5852881A JPS5852881A JP15069481A JP15069481A JPS5852881A JP S5852881 A JPS5852881 A JP S5852881A JP 15069481 A JP15069481 A JP 15069481A JP 15069481 A JP15069481 A JP 15069481A JP S5852881 A JPS5852881 A JP S5852881A
- Authority
- JP
- Japan
- Prior art keywords
- ion implantation
- resist
- source
- pattern
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 17
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 238000000206 photolithography Methods 0.000 abstract description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000002844 melting Methods 0.000 abstract description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052721 tungsten Inorganic materials 0.000 abstract description 2
- 239000010937 tungsten Substances 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0891—Source or drain regions of field-effect devices of field-effect transistors with Schottky gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は半導体素子の１１造方法に関し、詳しくはＭ
ＥＳ ＦＥＴの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing an ES FET.
従来のＭＥＳ ＦＥＴの製造方法を第１図により説明す
る。まず、第１図囚に示すように、半絶縁性基板１１上
にエピタキシャル法あるいはイオン注入法によってｎ型
導電層１２ｉ形成する。次に、ホトリンによってレノス
トマスクを形成してから、半導体基板（半絶縁性基板１
１とｎ型導電層１２からなる）に高濃度イオン注入を行
い、さらに熱処理によってアニールすることによって同
図に示すようにソース・ドレイン領域１３．１４を半導
体基板に形成する。続いて、ホトリソによるレジストパ
ターンの形成、オーミック金属の蒸着、その不要部のリ
フトオフを行って１１４１図（２）に示すようにソース
・ドレイン１１４ｉ１５．１６ｔ″ソースΦドレイン領
域１３．１４上に形成し、最後に同様にホトリンによる
レジストパターンの形成、ダート金属の蒸着、その不要
部のリフトオフ全行って同図に示すようにゲート電極１
７を半導体基板上の所定位置に形成する。A conventional method for manufacturing a MES FET will be explained with reference to FIG. First, as shown in FIG. 1, an n-type conductive layer 12i is formed on a semi-insulating substrate 11 by an epitaxial method or an ion implantation method. Next, a Renost mask is formed using photorin, and then a semiconductor substrate (semi-insulating substrate 1
1 and n-type conductive layer 12), and is further annealed by heat treatment to form source/drain regions 13 and 14 in the semiconductor substrate as shown in the figure. Subsequently, a resist pattern is formed by photolithography, ohmic metal is deposited, and unnecessary parts are lifted off to form the source/drain 114i15.16t'' source Φ drain region 13.14 as shown in FIG. 1141 (2). , Finally, the resist pattern is formed using photorin, the dirt metal is evaporated, and the unnecessary parts are lifted off to form the gate electrode 1 as shown in the figure.
7 is formed at a predetermined position on the semiconductor substrate.
ところで、 ＭＥＳ ＦＥＴにおいては、ソース拳ゲー
トまたはゲート・ドレイン間距離が小さい程、またダー
ト長が小さい程、高周波特性が犬となる。By the way, in a MES FET, the smaller the source-to-gate or gate-drain distance, or the shorter the dart length, the better the high frequency characteristics.
しかるに、上記のような従来のホトリソ、マスク合わせ
法による製造方法では、マスク合わせｆｆ度によってソ
ースーグート間あるいはゲート・ト・レイン間距離を小
さくすることに限界があシ、高周波特性を向上させるこ
とに限りがあった。また、上記従来の製造方法では、精
度ｔｉするマスク合わせ全２度必要とし、特にゲート電
極１７がソース・ドレづン領域１３．１４と接触すると
ダート耐圧劣化をもたらすため、マスクずれによって耐
圧の劣化や歩留シの低下が生じる欠点があった。However, in the conventional manufacturing method using photolithography and mask alignment methods as described above, there is a limit to reducing the source-to-gate or gate-to-train distance depending on the degree of mask alignment, and it is difficult to improve high frequency characteristics. There was a limit. In addition, in the conventional manufacturing method described above, it is necessary to align the masks twice with precision ti, and in particular, when the gate electrode 17 comes into contact with the source/drain regions 13.14, dirt breakdown voltage deteriorates. However, there were drawbacks such as a decrease in yield and yield.
この発明は上記の点に鑑みなされたもので、高周波特性
の改善を図ることができるとともに、耐圧の劣化や歩留
シの低下を防止することができる半導体素子の製造方法
を提供すること全目的とする。The present invention has been made in view of the above points, and its overall purpose is to provide a method for manufacturing a semiconductor device that can improve high frequency characteristics and prevent deterioration of breakdown voltage and decrease in yield. shall be.
以下この発明の実施例を第２図を参照して説明する。第
２図囚において、２１は半絶縁性ＧａＡｓ基板であシ、
まずその基板２１の表面上にエピタキシャル成長を行っ
てｎ型の導電＃２２に形成する。An embodiment of the present invention will be described below with reference to FIG. In Figure 2, 21 is a semi-insulating GaAs substrate;
First, epitaxial growth is performed on the surface of the substrate 21 to form n-type conductivity #22.
次に、ホトリソによるレジストパターンの形成、ゲート
金属の蒸着、その不要部のリフトオフを行って、タング
ステンのような高融点金属からなるダート電極２３ｔ−
半導体基板（半絶縁性ＧａＡｓ基板２１とｎ型導電層２
２からなる）の表面所定位置に同図に示すように形成す
る。Next, a resist pattern is formed by photolithography, gate metal is vapor deposited, and unnecessary parts thereof are lifted off to form a dirt electrode 23t- made of a high melting point metal such as tungsten.
Semiconductor substrate (semi-insulating GaAs substrate 21 and n-type conductive layer 2
2) at a predetermined position on the surface as shown in the figure.
次に、ホトリソを行ってレジストパターン２４を第２図
ＣＢ）に示すように半導体基板上の所定部分に形成する
。そして、このレジストノやターン２４および前記ゲー
ト１ｉ極２３をマスクとして、半導体基板に対するたと
えばシリコンのような導電型不純物イオンの第１のイオ
ン注入を前記第２図ω）に矢印で示すように−斜め方向
から行い、第１のイオン注入領域２５を半導体基板に形
成する。Next, photolithography is performed to form a resist pattern 24 on a predetermined portion of the semiconductor substrate as shown in FIG. 2CB). Then, using the resist nozzle, the turn 24, and the gate 1i pole 23 as a mask, a first ion implantation of conductivity type impurity ions such as silicon into the semiconductor substrate is carried out diagonally as shown by the arrow in FIG. 2 ω). A first ion implantation region 25 is formed in the semiconductor substrate.
続いて、前記と同一不純物イオンの第２のイオン注入を
、同じくレジストパターン２４およびダート電極２３を
マスクとして行う。ただし、この場合は、第２図Ｃ）に
矢印で示すように、前記斜め方向と反対の斜め方向から
イオン注入を行うものである。これによシ、半導体基板
に薗２のイオン圧入領域２６ｔ−形成する。Subsequently, a second ion implantation of the same impurity ions as described above is performed using the resist pattern 24 and the dirt electrode 23 as a mask. However, in this case, the ion implantation is performed from an oblique direction opposite to the above-mentioned oblique direction, as shown by the arrow in FIG. 2C). As a result, the ion press-in region 26t of the groove 2 is formed on the semiconductor substrate.
しかる後；熱処理によってイオン注入領域をアニールす
ることによシ、ソース領域２８．ドレイン領域２９を半
導体基板に形成する。Thereafter, by annealing the ion implanted region by heat treatment, the source region 28. A drain region 29 is formed in the semiconductor substrate.
その後は、紬記レジスト・？ターフ２４ｔ−除去した後
、再度ホトリンによるレジストパターンの形成を行い、
さらにオーミック金属の蒸着、その不要部のリフトオフ
を打うことによシ、第２図０に示すようにソース・ドレ
イン電極３０．３１’！にソース・ドレイン領域２８．
２９上に形成する。After that, Tsumugi resist? After removing the turf 24t, a resist pattern was formed again using photorin.
Furthermore, by depositing ohmic metal and lifting off the unnecessary parts, the source/drain electrodes 30 and 31' are formed as shown in FIG. source/drain regions 28.
29.
以上のように、実施例では、ダート電極２３をマスクと
してイオン注入を行うことにより、ダートを極２３とソ
ース・ドレイン領域２８．２９にセルファライン化する
ことができ、ソース・ドレインとダート間距融を極限ま
で小さくできる。しかも、イオン注入を斜め方向から行
っているために、ケ°−ト電極２３の下にまでイオン注
入領域を形成することができ、ゲート電極２３より狭１
／１ゲート長とすることができる。し友がって、高周波
特性、さらには高速特性が向上し、製造歩留りもセルフ
ァライン化により向上する。As described above, in the embodiment, by performing ion implantation using the dirt electrode 23 as a mask, the dirt can be self-aligned between the pole 23 and the source/drain regions 28 and 29, and the distance between the source/drain and the dirt can be melted. can be made as small as possible. Moreover, since the ion implantation is performed from an oblique direction, the ion implantation region can be formed even below the gate electrode 23, making it narrower than the gate electrode 23.
/1 gate length. As a result, high-frequency characteristics and even high-speed characteristics are improved, and manufacturing yields are also improved by using a self-aligned line.
また、ダートを極２３ ’にマスクとする斜め方向から
のイオン圧入ｔ、互いに反対方向から計２回行っている
ため、ダート電極２３より少し離れた位置には、２回の
イオン注入の重なりに工って高濃度領域（第２図Ｃ）に
符号２７で示す）が形成され、したがってソース・ドレ
イン領域２８．２９の直列抵抗の低減を図ることができ
るとともに、ソース・ドレイン電極３０．３１とのオー
ミック特性が改善される。また、同時に、ダート電極２
３に接する半導体基板の不純物濃度は、高濃度領域２７
０半分にすることができるため、ソース・ゲート間ある
いはゲート・ドレイン間の耐圧を、垂直にイオン注入し
てソース０ドレイン領域を形成する場合に比較して大き
くすることができる。In addition, since the ion injection from an oblique direction using the dirt as a mask at the pole 23' is carried out twice in total from opposite directions, there is an overlap between the two ion implantations at a position slightly away from the dirt electrode 23. As a result, a high concentration region (indicated by reference numeral 27 in FIG. 2C) is formed, which makes it possible to reduce the series resistance of the source/drain regions 28, 29 and to connect the source/drain electrodes 30, 31. ohmic characteristics are improved. At the same time, the dirt electrode 2
The impurity concentration of the semiconductor substrate in contact with 3 is the high concentration region 27
Since the voltage can be reduced to half of 0, the withstand voltage between the source and the gate or between the gate and the drain can be increased compared to the case where the source 0 drain region is formed by vertical ion implantation.
以上実施例で詳述したように、この発明の半導体素子の
製造方法によれば、ゲート電極をマスクとして両方向か
らの斜めイオン注入を利用することによシ、高周波特性
、高速特性、耐圧など電気的特性のすぐれた高信頼性の
ＭＥＳ ＦＥＴ ｋ歩留りよく製造することができる。As described in detail in the embodiments above, according to the method of manufacturing a semiconductor device of the present invention, by using diagonal ion implantation from both directions using the gate electrode as a mask, high frequency characteristics, high speed characteristics, breakdown voltage, etc. It is possible to manufacture highly reliable MES FETs with excellent physical characteristics at a high yield.
第１図は従来のＭＥＳ ＦＥＴの製造方法を説明するた
めの断面図、第２図はこの発明の半導体素子の製造方法
の実施例を説明する九めの断面図であ２１・・・半絶縁
性ＧａＡｓ基板、２２・・・ｎ型４１１層、２３・・・
ゲート電極、２５・・・第１のイオン注入領域、２６・
・・第２のイオン注入領域、２７．２８・・・ソース・
ドレイン領域。
特許出願人 沖電気工業株式会社FIG. 1 is a cross-sectional view for explaining a conventional method for manufacturing a MES FET, and FIG. 2 is a ninth cross-sectional view for explaining an embodiment of a method for manufacturing a semiconductor element according to the present invention. GaAs substrate, 22... n-type 411 layer, 23...
Gate electrode, 25...first ion implantation region, 26.
...Second ion implantation region, 27.28...Source.
drain area. Patent applicant Oki Electric Industry Co., Ltd.
Claims (1)
程と、このダート電極をマスクトシテー斜め方向から不
純物イオンのイオン注入を前記半導体基板に対して行う
工程と、前記斜め方向と反対の斜め方向から、同じくダ
ート電極をマスクとして不純物イオンのイオン注入を前
記半導体基板に対して行う工程と全具備してなる半導体
素子の製造方法。forming a gate electrode at a predetermined position on the surface of a semiconductor substrate, masking the dirt electrode and implanting impurity ions into the semiconductor substrate from an oblique direction, and from an oblique direction opposite to the oblique direction, A method for manufacturing a semiconductor device, which also includes a step of implanting impurity ions into the semiconductor substrate using a dirt electrode as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15069481A JPS5852881A (en) | 1981-09-25 | 1981-09-25 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15069481A JPS5852881A (en) | 1981-09-25 | 1981-09-25 | Manufacture of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5852881A true JPS5852881A (en) | 1983-03-29 |
Family
ID=15502394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15069481A Pending JPS5852881A (en) | 1981-09-25 | 1981-09-25 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5852881A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2592225A1 (en) * | 1985-12-20 | 1987-06-26 | Thomson Csf | POWER HYPERFREQUENCY TRANSISTOR |
| EP0412701A2 (en) * | 1989-07-31 | 1991-02-13 | Canon Kabushiki Kaisha | Thin film transistor and preparation thereof |
| JPH0513444A (en) * | 1991-10-23 | 1993-01-22 | Hitachi Ltd | Field-effect transistor |
| FR2709378A1 (en) * | 1993-01-29 | 1995-03-03 | Mitsubishi Electric Corp | Field-effect transistor and method for manufacturing such a transistor |
| US5471073A (en) * | 1993-01-29 | 1995-11-28 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor and method for producing the field effect transistor |
| GB2282262B (en) * | 1993-01-29 | 1997-04-23 | Mitsubishi Electric Corp | Field effect transistor and method for producing the field effect transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4979183A (en) * | 1972-12-01 | 1974-07-31 | ||
| JPS535581A (en) * | 1976-07-06 | 1978-01-19 | Toshiba Corp | Schottky gate type field effect transistor |
-
1981
- 1981-09-25 JP JP15069481A patent/JPS5852881A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4979183A (en) * | 1972-12-01 | 1974-07-31 | ||
| JPS535581A (en) * | 1976-07-06 | 1978-01-19 | Toshiba Corp | Schottky gate type field effect transistor |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2592225A1 (en) * | 1985-12-20 | 1987-06-26 | Thomson Csf | POWER HYPERFREQUENCY TRANSISTOR |
| EP0412701A2 (en) * | 1989-07-31 | 1991-02-13 | Canon Kabushiki Kaisha | Thin film transistor and preparation thereof |
| US5410172A (en) * | 1989-07-31 | 1995-04-25 | Canon Kabushiki Kaisha | Thin film transistor and preparation thereof |
| JPH0513444A (en) * | 1991-10-23 | 1993-01-22 | Hitachi Ltd | Field-effect transistor |
| FR2709378A1 (en) * | 1993-01-29 | 1995-03-03 | Mitsubishi Electric Corp | Field-effect transistor and method for manufacturing such a transistor |
| US5471073A (en) * | 1993-01-29 | 1995-11-28 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor and method for producing the field effect transistor |
| GB2282262B (en) * | 1993-01-29 | 1997-04-23 | Mitsubishi Electric Corp | Field effect transistor and method for producing the field effect transistor |
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